1 #define RAMINIT_SYSINFO 1
2 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
4 #define SET_NB_CFG_54 1
7 #define QRANK_DIMM_SUPPORT 1
9 //used by incoherent_ht
10 //#define K8_ALLOCATE_IO_RANGE 1
12 //used by init_cpus and fidvid
13 #define K8_SET_FIDVID 0
14 //if we want to wait for core1 done before DQS training, set it to 0
15 #define K8_SET_FIDVID_CORE0_ONLY 1
17 #if CONFIG_K8_REV_F_SUPPORT == 1
18 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
23 #include <device/pci_def.h>
24 #include <device/pci_ids.h>
26 #include <device/pnp_def.h>
27 #include <arch/romcc_io.h>
28 #include <cpu/x86/lapic.h>
29 #include "option_table.h"
30 #include "pc80/mc146818rtc_early.c"
32 #include "pc80/serial.c"
33 #include "arch/i386/lib/console.c"
34 #include <cpu/amd/model_fxx_rev.h>
35 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
36 #include "northbridge/amd/amdk8/raminit.h"
37 #include "cpu/amd/model_fxx/apic_timer.c"
39 #include "cpu/x86/lapic/boot_cpu.c"
40 #include "northbridge/amd/amdk8/reset_test.c"
42 #include "cpu/x86/bist.h"
44 #include "lib/delay.c"
46 #include "northbridge/amd/amdk8/debug.c"
47 #include "cpu/amd/mtrr/amd_earlymtrr.c"
48 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
50 #include "northbridge/amd/amdk8/setup_resource_map.c"
52 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
54 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
57 * GPIO28 of 8111 will control H0_MEMRESET_L
58 * GPIO29 of 8111 will control H1_MEMRESET_L
60 static void memreset_setup(void)
62 if (is_cpu_pre_c0()) {
63 /* Set the memreset low */
64 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
65 /* Ensure the BIOS has control of the memory lines */
66 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
68 /* Ensure the CPU has controll of the memory lines */
69 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
73 static void memreset(int controllers, const struct mem_controller *ctrl)
75 if (is_cpu_pre_c0()) {
77 /* Set memreset_high */
78 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
83 static inline void activate_spd_rom(const struct mem_controller *ctrl)
87 static inline int spd_read_byte(unsigned device, unsigned address)
89 return smbus_read_byte(device, address);
92 #include "northbridge/amd/amdk8/amdk8.h"
93 #include "northbridge/amd/amdk8/coherent_ht.c"
95 #include "northbridge/amd/amdk8/incoherent_ht.c"
97 #include "northbridge/amd/amdk8/raminit.c"
99 #include "lib/generic_sdram.c"
100 #include "lib/ramtest.c"
102 /* tyan does not want the default */
103 #include "resourcemap.c"
105 #include "cpu/amd/dualcore/dualcore.c"
116 #include "cpu/amd/car/copy_and_run.c"
117 #include "cpu/amd/car/post_cache_as_ram.c"
119 #include "cpu/amd/model_fxx/init_cpus.c"
121 #include "cpu/amd/model_fxx/fidvid.c"
123 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
124 #include "northbridge/amd/amdk8/early_ht.c"
126 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
128 static const uint16_t spd_addr[] = {
132 #if CONFIG_MAX_PHYSICAL_CPUS > 1
140 struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
142 int needs_reset; int i;
143 unsigned bsp_apicid = 0;
145 if (!cpu_init_detectedx && boot_cpu()) {
146 /* Nothing special needs to be done to find bus 0 */
147 /* Allow the HT devices to be found */
149 enumerate_ht_chain();
151 /* Setup the rom access for 4M */
152 amd8111_enable_rom();
156 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
159 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
163 /* Halt if there was a built in self test failure */
164 report_bist_failure(bist);
166 printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
168 setup_mb_resource_map();
170 print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
172 #if CONFIG_MEM_TRAIN_SEQ == 1
173 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
175 setup_coherent_ht_domain(); // routing table and start other core0
177 wait_all_core0_started();
178 #if CONFIG_LOGICAL_CPUS==1
179 // It is said that we should start core1 after all core0 launched
180 /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
181 * So here need to make sure last core0 is started, esp for two way system,
182 * (there may be apic id conflicts in that case)
185 wait_all_other_cores_started(bsp_apicid);
188 /* it will set up chains and store link pair for optimization later */
189 ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
191 #if K8_SET_FIDVID == 1
195 msr=rdmsr(0xc0010042);
196 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
202 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
204 init_fidvid_bsp(bsp_apicid);
206 // show final fid and vid
209 msr=rdmsr(0xc0010042);
210 print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
215 needs_reset = optimize_link_coherent_ht();
216 needs_reset |= optimize_link_incoherent_ht(sysinfo);
218 // fidvid change will issue one LDTSTOP and the HT change will be effective too
220 print_info("ht reset -\r\n");
221 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
224 allow_all_aps_stop(bsp_apicid);
226 //It's the time to set ctrl in sysinfo now;
227 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
232 dump_smbus_registers();
237 //do we need apci timer, tsc...., only debug need it for better output
238 /* all ap stopped? */
239 init_timer(); // Need to use TMICT to synconize FID/VID
240 sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
246 post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now