src/mainboard/tyan/s2881/romstage.c

   1 #define QRANK_DIMM_SUPPORT 1
   2
   3 #if CONFIG_LOGICAL_CPUS==1
   4 #define SET_NB_CFG_54 1
   5 #endif
   6
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <device/pci_def.h>
  10 #include <arch/io.h>
  11 #include <device/pnp_def.h>
  12 #include <arch/romcc_io.h>
  13 #include <cpu/x86/lapic.h>
  14 #include "option_table.h"
  15 #include "pc80/mc146818rtc_early.c"
  16 #include "pc80/serial.c"
  17 #include "arch/i386/lib/console.c"
  18 #include "lib/ramtest.c"
  19
  20 #if 0
  21 static void post_code(uint8_t value) {
  22 #if 1
  23         int i;
  24         for(i=0;i<0x80000;i++) {
  25                 outb(value, 0x80);
  26         }
  27 #endif
  28 }
  29 #endif
  30
  31 #include <cpu/amd/model_fxx_rev.h>
  32
  33 #include "northbridge/amd/amdk8/incoherent_ht.c"
  34 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  35 #include "northbridge/amd/amdk8/raminit.h"
  36 #include "cpu/amd/model_fxx/apic_timer.c"
  37 #include "lib/delay.c"
  38
  39 #include "cpu/x86/lapic/boot_cpu.c"
  40 #include "northbridge/amd/amdk8/reset_test.c"
  41 #include "northbridge/amd/amdk8/debug.c"
  42 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  43
  44 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  45 #include "cpu/x86/bist.h"
  46
  47 #include "northbridge/amd/amdk8/setup_resource_map.c"
  48
  49 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  50
  51 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  52
  53 static void memreset_setup(void)
  54 {
  55    if (is_cpu_pre_c0()) {
  56         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  57    }
  58    else {
  59         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  60    }
  61         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  62 }
  63
  64 static void memreset(int controllers, const struct mem_controller *ctrl)
  65 {
  66    if (is_cpu_pre_c0()) {
  67         udelay(800);
  68         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  69         udelay(90);
  70    }
  71 }
  72
  73 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  74 {
  75         /* nothing to do */
  76 }
  77
  78 static inline int spd_read_byte(unsigned device, unsigned address)
  79 {
  80         return smbus_read_byte(device, address);
  81 }
  82
  83 #include "northbridge/amd/amdk8/raminit.c"
  84 #include "resourcemap.c"
  85 #include "northbridge/amd/amdk8/coherent_ht.c"
  86 #include "lib/generic_sdram.c"
  87
  88 #include "cpu/amd/dualcore/dualcore.c"
  89
  90 #include "cpu/amd/car/copy_and_run.c"
  91
  92 #include "cpu/amd/car/post_cache_as_ram.c"
  93
  94 #include "cpu/amd/model_fxx/init_cpus.c"
  95
  96 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  97 #include "northbridge/amd/amdk8/early_ht.c"
  98
  99 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 100 {
 101         static const uint16_t spd_addr [] = {
 102                         (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 103                         (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 104 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 105                         (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 106                         (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 107 #endif
 108         };
 109
 110         int needs_reset;
 111         unsigned bsp_apicid = 0;
 112
 113         struct mem_controller ctrl[8];
 114         unsigned nodes;
 115
 116         if (!cpu_init_detectedx && boot_cpu()) {
 117                 /* Nothing special needs to be done to find bus 0 */
 118                 /* Allow the HT devices to be found */
 119
 120                 enumerate_ht_chain();
 121
 122                 /* Setup the amd8111 */
 123                 amd8111_enable_rom();
 124         }
 125
 126         if (bist == 0) {
 127                 bsp_apicid = init_cpus(cpu_init_detectedx);
 128         }
 129
 130 //      post_code(0x32);
 131
 132         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 133         uart_init();
 134         console_init();
 135
 136         /* Halt if there was a built in self test failure */
 137         report_bist_failure(bist);
 138
 139         setup_s2881_resource_map();
 140 #if 0
 141         dump_pci_device(PCI_DEV(0, 0x18, 0));
 142         dump_pci_device(PCI_DEV(0, 0x19, 0));
 143 #endif
 144
 145         needs_reset = setup_coherent_ht_domain();
 146
 147         wait_all_core0_started();
 148 #if CONFIG_LOGICAL_CPUS==1
 149         // It is said that we should start core1 after all core0 launched
 150         start_other_cores();
 151         wait_all_other_cores_started(bsp_apicid);
 152 #endif
 153
 154         needs_reset |= ht_setup_chains_x();
 155
 156         if (needs_reset) {
 157                 print_info("ht reset -\r\n");
 158                 soft_reset();
 159         }
 160
 161         enable_smbus();
 162 #if 0
 163         dump_spd_registers(&cpu[0]);
 164 #endif
 165 #if 0
 166         dump_smbus_registers();
 167 #endif
 168
 169         allow_all_aps_stop(bsp_apicid);
 170
 171         nodes = get_nodes();
 172         //It's the time to set ctrl now;
 173         fill_mem_ctrl(nodes, ctrl, spd_addr);
 174
 175         memreset_setup();
 176         sdram_initialize(nodes, ctrl);
 177
 178 #if 0
 179         dump_pci_devices();
 180 #endif
 181
 182         post_cache_as_ram();
 183 }
 184