src/mainboard/amd/pistachio/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #define RAMINIT_SYSINFO 1
  21 #define K8_SET_FIDVID 1
  22 #define QRANK_DIMM_SUPPORT 1
  23 #if CONFIG_LOGICAL_CPUS==1
  24 #define SET_NB_CFG_54 1
  25 #endif
  26
  27 #define DIMM0 0x50
  28 #define DIMM1 0x51
  29
  30 #include <stdint.h>
  31 #include <string.h>
  32 #include <device/pci_def.h>
  33 #include <arch/io.h>
  34 #include <device/pnp_def.h>
  35 #include <arch/romcc_io.h>
  36 #include <cpu/x86/lapic.h>
  37 #include "option_table.h"
  38 #include "pc80/mc146818rtc_early.c"
  39 #include "pc80/serial.c"
  40 #include "arch/i386/lib/console.c"
  41
  42 #define post_code(x) outb(x, 0x80)
  43
  44 #include <cpu/amd/model_fxx_rev.h>
  45 #include "northbridge/amd/amdk8/raminit.h"
  46 #include "cpu/amd/model_fxx/apic_timer.c"
  47 #include "lib/delay.c"
  48
  49 #include "cpu/x86/lapic/boot_cpu.c"
  50 #include "northbridge/amd/amdk8/reset_test.c"
  51 #include "superio/ite/it8712f/it8712f_early_serial.c"
  52
  53 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  54 #include "cpu/x86/bist.h"
  55
  56 #include "northbridge/amd/amdk8/setup_resource_map.c"
  57
  58 #include "southbridge/amd/rs690/rs690_early_setup.c"
  59 #include "southbridge/amd/sb600/sb600_early_setup.c"
  60 #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
  61
  62 /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
  63 static void memreset(int controllers, const struct mem_controller *ctrl)
  64 {
  65 }
  66
  67 /* called in raminit_f.c */
  68 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  69 {
  70 }
  71
  72 /*called in raminit_f.c */
  73 static inline int spd_read_byte(u32 device, u32 address)
  74 {
  75         return smbus_read_byte(device, address);
  76 }
  77
  78 #include "northbridge/amd/amdk8/amdk8.h"
  79 #include "northbridge/amd/amdk8/incoherent_ht.c"
  80 #include "northbridge/amd/amdk8/raminit_f.c"
  81 #include "northbridge/amd/amdk8/coherent_ht.c"
  82 #include "lib/generic_sdram.c"
  83 #include "resourcemap.c"
  84
  85 #include "cpu/amd/dualcore/dualcore.c"
  86
  87 #include "cpu/amd/car/copy_and_run.c"
  88 #include "cpu/amd/car/post_cache_as_ram.c"
  89
  90 #include "cpu/amd/model_fxx/init_cpus.c"
  91
  92 #include "cpu/amd/model_fxx/fidvid.c"
  93
  94 #include "northbridge/amd/amdk8/early_ht.c"
  95
  96 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  97 {
  98         static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
  99         int needs_reset = 0;
 100         u32 bsp_apicid = 0;
 101         msr_t msr;
 102         struct cpuid_result cpuid1;
 103         struct sys_info *sysinfo =
 104             (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE -
 105                                 CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 106
 107         if (!cpu_init_detectedx && boot_cpu()) {
 108                 /* Nothing special needs to be done to find bus 0 */
 109                 /* Allow the HT devices to be found */
 110                 enumerate_ht_chain();
 111
 112                 sb600_lpc_port80();
 113                 /* sb600_pci_port80(); */
 114         }
 115
 116         if (bist == 0) {
 117                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 118         }
 119
 120         enable_rs690_dev8();
 121         sb600_lpc_init();
 122
 123         /* Pistachio used a FPGA to enable serial debug instead of a SIO
 124          * and it doens't require any special setup. */
 125         uart_init();
 126         console_init();
 127
 128         post_code(0x03);
 129
 130         /* Halt if there was a built in self test failure */
 131         report_bist_failure(bist);
 132         printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
 133
 134         setup_pistachio_resource_map();
 135
 136         setup_coherent_ht_domain();
 137
 138 #if CONFIG_LOGICAL_CPUS==1
 139         /* It is said that we should start core1 after all core0 launched */
 140         wait_all_core0_started();
 141         start_other_cores();
 142 #endif
 143         wait_all_aps_started(bsp_apicid);
 144
 145         /* it will set up chains and store link pair for optimization later,
 146          * it will init sblnk and sbbusn, nodes, sbdn */
 147         ht_setup_chains_x(sysinfo);
 148
 149         /* run _early_setup before soft-reset. */
 150         rs690_early_setup();
 151         sb600_early_setup();
 152
 153         post_code(0x04);
 154
 155         /* Check to see if processor is capable of changing FIDVID  */
 156         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 157         cpuid1 = cpuid(0x80000007);
 158         if( (cpuid1.edx & 0x6) == 0x6 ) {
 159
 160                 /* Read FIDVID_STATUS */
 161                 msr=rdmsr(0xc0010042);
 162                 printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 163
 164                 enable_fid_change();
 165                 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 166                 init_fidvid_bsp(bsp_apicid);
 167
 168                 /* show final fid and vid */
 169                 msr=rdmsr(0xc0010042);
 170                 printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 171
 172         } else {
 173                 printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
 174         }
 175
 176         post_code(0x05);
 177
 178         needs_reset = optimize_link_coherent_ht();
 179         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 180         rs690_htinit();
 181         printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 182
 183         post_code(0x06);
 184
 185         if (needs_reset) {
 186                 print_info("ht reset -\r\n");
 187                 soft_reset();
 188         }
 189
 190         allow_all_aps_stop(bsp_apicid);
 191
 192         /* It's the time to set ctrl now; */
 193         printk(BIOS_DEBUG, "sysinfo->nodes: %2x  sysinfo->ctrl: %p  spd_addr: %p\n",
 194                      sysinfo->nodes, sysinfo->ctrl, spd_addr);
 195         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 196
 197         post_code(0x07);
 198
 199         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 200
 201         post_code(0x08);
 202
 203         rs690_before_pci_init();
 204         sb600_before_pci_init();
 205
 206         post_cache_as_ram();
 207 }
 208