src/mainboard/tyan/s2885/romstage.c

   1
   2 #include <stdint.h>
   3 #include <string.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include "option_table.h"
  10 #include "pc80/mc146818rtc_early.c"
  11 #include "pc80/serial.c"
  12 #include "arch/i386/lib/console.c"
  13 #include "lib/ramtest.c"
  14
  15 #if 0
  16 static void post_code(uint8_t value) {
  17 #if 1
  18         int i;
  19         for(i=0;i<0x80000;i++) {
  20                 outb(value, 0x80);
  21         }
  22 #endif
  23 }
  24 #endif
  25
  26 #include <cpu/amd/model_fxx_rev.h>
  27
  28 #include "northbridge/amd/amdk8/incoherent_ht.c"
  29 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  30 #include "northbridge/amd/amdk8/raminit.h"
  31 #include "cpu/amd/model_fxx/apic_timer.c"
  32 #include "lib/delay.c"
  33
  34 #include "cpu/x86/lapic/boot_cpu.c"
  35 #include "northbridge/amd/amdk8/reset_test.c"
  36 #include "northbridge/amd/amdk8/debug.c"
  37 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  38
  39 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  40 #include "cpu/x86/bist.h"
  41
  42 #include "northbridge/amd/amdk8/setup_resource_map.c"
  43
  44 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  45
  46 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  47
  48 static void memreset_setup(void)
  49 {
  50    if (is_cpu_pre_c0()) {
  51         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  52    }
  53    else {
  54         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  55    }
  56         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  57 }
  58
  59 static void memreset(int controllers, const struct mem_controller *ctrl)
  60 {
  61    if (is_cpu_pre_c0()) {
  62         udelay(800);
  63         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  64         udelay(90);
  65    }
  66 }
  67
  68 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  69 {
  70         /* nothing to do */
  71 }
  72
  73 static inline int spd_read_byte(unsigned device, unsigned address)
  74 {
  75         return smbus_read_byte(device, address);
  76 }
  77
  78 #define QRANK_DIMM_SUPPORT 1
  79
  80 #include "northbridge/amd/amdk8/raminit.c"
  81 #include "northbridge/amd/amdk8/coherent_ht.c"
  82 #include "lib/generic_sdram.c"
  83
  84  /* tyan does not want the default */
  85 #include "resourcemap.c"
  86
  87 #if CONFIG_LOGICAL_CPUS==1
  88 #define SET_NB_CFG_54 1
  89 #endif
  90 #include "cpu/amd/dualcore/dualcore.c"
  91
  92 #include "cpu/amd/car/copy_and_run.c"
  93
  94 #include "cpu/amd/car/post_cache_as_ram.c"
  95
  96 #include "cpu/amd/model_fxx/init_cpus.c"
  97
  98 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  99 #include "northbridge/amd/amdk8/early_ht.c"
 100
 101 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 102 {
 103         static const uint16_t spd_addr [] = {
 104                         (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 105                         (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 106 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 107                         (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 108                         (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 109 #endif
 110         };
 111
 112         int needs_reset;
 113         unsigned bsp_apicid = 0;
 114
 115         struct mem_controller ctrl[8];
 116         unsigned nodes;
 117
 118         if (!cpu_init_detectedx && boot_cpu()) {
 119                 /* Nothing special needs to be done to find bus 0 */
 120                 /* Allow the HT devices to be found */
 121
 122                 enumerate_ht_chain();
 123
 124                 /* Setup the amd8111 */
 125                 amd8111_enable_rom();
 126         }
 127
 128         if (bist == 0) {
 129                 bsp_apicid = init_cpus(cpu_init_detectedx);
 130         }
 131
 132 //      post_code(0x32);
 133
 134         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 135         uart_init();
 136         console_init();
 137
 138 //      dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 139
 140         /* Halt if there was a built in self test failure */
 141         report_bist_failure(bist);
 142
 143         setup_s2885_resource_map();
 144 #if 0
 145         dump_pci_device(PCI_DEV(0, 0x18, 0));
 146         dump_pci_device(PCI_DEV(0, 0x19, 0));
 147 #endif
 148
 149         needs_reset = setup_coherent_ht_domain();
 150
 151         wait_all_core0_started();
 152 #if CONFIG_LOGICAL_CPUS==1
 153         // It is said that we should start core1 after all core0 launched
 154         start_other_cores();
 155         wait_all_other_cores_started(bsp_apicid);
 156 #endif
 157
 158         needs_reset |= ht_setup_chains_x();
 159
 160         if (needs_reset) {
 161                 print_info("ht reset -\r\n");
 162                 soft_reset();
 163         }
 164
 165         allow_all_aps_stop(bsp_apicid);
 166
 167         nodes = get_nodes();
 168         //It's the time to set ctrl now;
 169         fill_mem_ctrl(nodes, ctrl, spd_addr);
 170
 171         enable_smbus();
 172
 173         memreset_setup();
 174         sdram_initialize(nodes, ctrl);
 175
 176 #if 0
 177         dump_pci_devices();
 178 #endif
 179
 180         post_cache_as_ram();
 181
 182 }
 183