src/mainboard/intel/jarrell/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/romcc_io.h>
   6 #include <cpu/x86/lapic.h>
   7 #include <stdlib.h>
   8 #include "option_table.h"
   9 #include "pc80/mc146818rtc_early.c"
  10 #include "pc80/serial.c"
  11 #include "arch/i386/lib/console.c"
  12 #include "lib/ramtest.c"
  13 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
  14 #include "northbridge/intel/e7520/raminit.h"
  15 #include "superio/nsc/pc87427/pc87427.h"
  16 #include "cpu/x86/lapic/boot_cpu.c"
  17 #include "cpu/x86/mtrr/earlymtrr.c"
  18 #include "watchdog.c"
  19 #include "reset.c"
  20 #include "power_reset_check.c"
  21 #include "jarrell_fixups.c"
  22 #include "superio/nsc/pc87427/pc87427_early_init.c"
  23 #include "northbridge/intel/e7520/memory_initialized.c"
  24 #include "cpu/x86/bist.h"
  25
  26 #define SIO_GPIO_BASE 0x680
  27 #define SIO_XBUS_BASE 0x4880
  28
  29 #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP2)
  30 #define HIDDEN_SERIAL_DEV  PNP_DEV(0x2e, PC87427_SP1)
  31
  32 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D6F0)
  33 #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
  34
  35 /* Beta values:         0x00090800 */
  36 /* Silver values:       0x000a0900 */
  37 #define RECVENA_CONFIG  0x000a090a
  38 #define RECVENB_CONFIG  0x000a090a
  39 #define DIMM_MAP_LOGICAL 0x0124
  40
  41 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  42 {
  43         /* nothing to do */
  44 }
  45 static inline int spd_read_byte(unsigned device, unsigned address)
  46 {
  47         return smbus_read_byte(device, address);
  48 }
  49
  50 #include "northbridge/intel/e7520/raminit.c"
  51 #include "lib/generic_sdram.c"
  52 #include "debug.c"
  53
  54 static void main(unsigned long bist)
  55 {
  56         /*
  57          *
  58          *
  59          */
  60         static const struct mem_controller mch[] = {
  61                 {
  62                         .node_id = 0,
  63                         .f0 = PCI_DEV(0, 0x00, 0),
  64                         .f1 = PCI_DEV(0, 0x00, 1),
  65                         .f2 = PCI_DEV(0, 0x00, 2),
  66                         .f3 = PCI_DEV(0, 0x00, 3),
  67                         .channel0 = { (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, 0 },
  68                         .channel1 = { (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, 0 },
  69                 }
  70         };
  71
  72         if (bist == 0) {
  73                 /* Skip this if there was a built in self test failure */
  74                 early_mtrr_init();
  75                 if (memory_initialized()) {
  76                         asm volatile ("jmp __cpu_reset");
  77                 }
  78         }
  79         /* Setup the console */
  80         pc87427_disable_dev(CONSOLE_SERIAL_DEV);
  81         pc87427_disable_dev(HIDDEN_SERIAL_DEV);
  82         pc87427_enable_dev(CONSOLE_SERIAL_DEV, CONFIG_TTYS0_BASE);
  83         /* Enable Serial 2 lines instead of GPIO */
  84         outb(0x2c, 0x2e);
  85         outb((inb(0x2f) & (~1<<1)), 0x2f);
  86         uart_init();
  87         console_init();
  88
  89         /* Halt if there was a built in self test failure */
  90         report_bist_failure(bist);
  91
  92         pc87427_enable_dev(PC87427_GPIO_DEV, SIO_GPIO_BASE);
  93
  94         pc87427_enable_dev(PC87427_XBUS_DEV, SIO_XBUS_BASE);
  95         xbus_cfg(PC87427_XBUS_DEV);
  96
  97         /* MOVE ME TO A BETTER LOCATION !!! */
  98         /* config LPC decode for flash memory access */
  99         device_t dev;
 100         dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
 101         if (dev == PCI_DEV_INVALID) {
 102                 die("Missing ich5?");
 103         }
 104         pci_write_config32(dev, 0xe8, 0x00000000);
 105         pci_write_config8(dev, 0xf0, 0x00);
 106
 107 #if 0
 108         print_pci_devices();
 109 #endif
 110         enable_smbus();
 111 #if 0
 112 //      dump_spd_registers(&cpu[0]);
 113         int i;
 114         for(i = 0; i < 1; i++) {
 115                 dump_spd_registers();
 116         }
 117 #endif
 118         disable_watchdogs();
 119         power_down_reset_check();
 120 //      dump_ipmi_registers();
 121         mainboard_set_e7520_leds();
 122         sdram_initialize(ARRAY_SIZE(mch), mch);
 123         ich5_watchdog_on();
 124 #if 0
 125         dump_pci_devices();
 126 #endif
 127 #if 0
 128         dump_pci_device(PCI_DEV(0, 0x00, 0));
 129         dump_bar14(PCI_DEV(0, 0x00, 0));
 130 #endif
 131
 132 #if 0 // temporarily disabled
 133         /* Check the first 1M */
 134 //      ram_check(0x00000000, 0x000100000);
 135 //      ram_check(0x00000000, 0x000a0000);
 136         ram_check(0x00100000, 0x01000000);
 137         /* check the first 1M in the 3rd Gig */
 138         ram_check(0x30100000, 0x31000000);
 139 #if 0
 140         ram_check(0x00000000, 0x02000000);
 141 #endif
 142
 143 #endif
 144 #if 0
 145         while(1) {
 146                 hlt();
 147         }
 148 #endif
 149 }
 150