src/mainboard/digitallogic/adl855pc/romstage.c

   1 #define ASM_CONSOLE_LOGLEVEL 8
   2 #include <stdint.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #if 0
   8 #include <arch/smp/lapic.h>
   9 #endif
  10 #include <arch/hlt.h>
  11 //#include "option_table.h"
  12 #include <stdlib.h>
  13 #include "pc80/mc146818rtc_early.c"
  14 #include "pc80/serial.c"
  15 #include "console/console.c"
  16 #include "lib/ramtest.c"
  17 #include "southbridge/intel/i82801dx/i82801dx.h"
  18 #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
  19 #include "northbridge/intel/i855/raminit.h"
  20
  21 #if 0
  22 #include "cpu/p6/apic_timer.c"
  23 #include "lib/delay.c"
  24 #endif
  25
  26 #include "cpu/x86/lapic/boot_cpu.c"
  27 #include "northbridge/intel/i855/debug.c"
  28 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  29 #include "cpu/x86/mtrr/earlymtrr.c"
  30 #include "cpu/x86/bist.h"
  31
  32 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  33
  34 static void hard_reset(void)
  35 {
  36         outb(0x0e, 0x0cf9);
  37 }
  38
  39 static void memreset_setup(void)
  40 {
  41 }
  42
  43 static void memreset(int controllers, const struct mem_controller *ctrl)
  44 {
  45 }
  46
  47 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  48 {
  49         /* nothing to do */
  50 }
  51
  52 static inline int spd_read_byte(unsigned device, unsigned address)
  53 {
  54         return smbus_read_byte(device, address);
  55 }
  56
  57 #include "northbridge/intel/i855/raminit.c"
  58 #include "northbridge/intel/i855/reset_test.c"
  59 #include "lib/generic_sdram.c"
  60
  61 static void main(unsigned long bist)
  62 {
  63         static const struct mem_controller memctrl[] = {
  64                 {
  65                         .d0 = PCI_DEV(0, 0, 1),
  66                         .channel0 = { (0xa<<3)|0, 0 },
  67                 },
  68         };
  69
  70         if (bist == 0) {
  71                 early_mtrr_init();
  72 #if 0
  73                 enable_lapic();
  74                 init_timer();
  75 #endif
  76         }
  77
  78         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  79         uart_init();
  80         console_init();
  81
  82         /* Halt if there was a built in self test failure */
  83         report_bist_failure(bist);
  84
  85
  86 #if 0
  87         print_pci_devices();
  88 #endif
  89
  90         if(!bios_reset_detected()) {
  91                 enable_smbus();
  92 #if 0
  93         dump_spd_registers(&memctrl[0]);
  94         //              dump_smbus_registers();
  95 #endif
  96
  97                 memreset_setup();
  98
  99                 sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
 100
 101         }
 102 #if 0
 103         else {
 104                         /* clear memory 1meg */
 105         __asm__ volatile(
 106                 "1: \n\t"
 107                 "movl %0, %%fs:(%1)\n\t"
 108                 "addl $4,%1\n\t"
 109                 "subl $4,%2\n\t"
 110                 "jnz 1b\n\t"
 111                 :
 112                 : "a" (0), "D" (0), "c" (1024*1024)
 113                 );
 114
 115         }
 116 #endif
 117
 118 #if 0
 119         dump_pci_devices();
 120 #endif
 121 #if 0
 122         dump_pci_device(PCI_DEV(0, 0, 0));
 123 #endif
 124
 125 /*
 126 #if  0
 127         ram_check(0x00000000, msr.lo+(msr.hi<<32));
 128 #else
 129 #if 0
 130         // Check 16MB of memory @ 0
 131         ram_check(0x00000000, 0x01000000);
 132 #else
 133         // Check 16MB of memory @ 2GB
 134         ram_check(0x80000000, 0x81000000);
 135 #endif
 136 #endif
 137 */
 138 }
 139