src/mainboard/eaglelion/5bcm/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/romcc_io.h>
   6 #include <arch/hlt.h>
   7 #include <stdlib.h>
   8 #include "pc80/serial.c"
   9 #include "arch/i386/lib/console.c"
  10 #include "lib/ramtest.c"
  11 //#include "southbridge/intel/i440bx/i440bx_early_smbus.c"
  12 #include "superio/nsc/pc97317/pc97317_early_serial.c"
  13 //#include "northbridge/intel/i440bx/raminit.h"
  14 #include "cpu/x86/bist.h"
  15 #include "southbridge/amd/cs5530/cs5530_enable_rom.c"
  16
  17 #define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
  18
  19 //#include "lib/delay.c"
  20
  21 #include "northbridge/amd/gx1/raminit.c"
  22
  23 static void main(unsigned long bist)
  24 {
  25         pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  26         uart_init();
  27         console_init();
  28
  29         /* Halt if there was a built in self test failure */
  30         report_bist_failure(bist);
  31
  32         cs5530_enable_rom();
  33
  34         sdram_init();
  35
  36         /* Check all of memory */
  37 #if 0
  38         ram_check(0x00000000, msr.lo);
  39 #endif
  40 #if 0
  41         static const struct {
  42                 unsigned long lo, hi;
  43         } check_addrs[] = {
  44                 /* Check 16MB of memory @ 0*/
  45                 { 0x00000000, 0x01000000 },
  46 #if TOTAL_CPUS > 1
  47                 /* Check 16MB of memory @ 2GB */
  48                 { 0x80000000, 0x81000000 },
  49 #endif
  50         };
  51         int i;
  52         for(i = 0; i < ARRAY_SIZE(check_addrs); i++) {
  53                 ram_check(check_addrs[i].lo, check_addrs[i].hi);
  54         }
  55 #endif
  56 }
  57