Fix issues reported by new lint test.
Change-Id: I077a829cb4a855cbb3b71b6eb5c66b2068be6def
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/646
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
hex
default 0x80000
depends on CPU_AMD_AGESA_FAMILY12
-
+
config HAVE_INIT_TIMER
bool
default y
- depends on CPU_AMD_AGESA_FAMILY12
-
+ depends on CPU_AMD_AGESA_FAMILY12
+
#
# Copyright (c) 2011, Advanced Micro Devices, Inc.
# All rights reserved.
-#
+#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# * Redistributions of source code must retain the above copyright
# * Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
-# * Neither the name of Advanced Micro Devices, Inc. nor the names of
-# its contributors may be used to endorse or promote products derived
+# * Neither the name of Advanced Micro Devices, Inc. nor the names of
+# its contributors may be used to endorse or promote products derived
# from this software without specific prior written permission.
-#
+#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
+#
#*****************************************************************************
-
+
ramstage-y += chip_name.c
driver-y += model_12_init.c
#elif (CONFIG_MMCONF_BUS_NUMBER == 2)
orl $(1 << 2), %eax
#elif (CONFIG_MMCONF_BUS_NUMBER == 4)
- orl $(2 << 2), %eax
+ orl $(2 << 2), %eax
#elif (CONFIG_MMCONF_BUS_NUMBER == 8)
orl $(3 << 2), %eax
#elif (CONFIG_MMCONF_BUS_NUMBER == 16)
movl %eax, %esp
#ifdef CARTEST
-testok:
+testok:
post_code(0x40)
xorl %edx, %edx
xorl %eax, %eax
.code32
- /* This is the GDT for the ROM stage part of coreboot. It
- * is different from the RAM stage GDT which is defined in
+ /* This is the GDT for the ROM stage part of coreboot. It
+ * is different from the RAM stage GDT which is defined in
* c_start.S
*/
{
unsigned long int i = SINGLE_CHAR_TIMEOUT;
while (i-- && !uart8250_can_rx_byte(base_port));
-
+
if (i)
return inb(base_port + UART_RBR);
else
#*****************************************************************************
-#
+#
# This file is part of the coreboot project.
-#
+#
# Copyright (C) 2011 Advanced Micro Devices, Inc.
-#
+#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
-#
+#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
-#
+#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
return CalloutStatus;
}
}
-
+
return CalloutStatus;
}
} else {
/* Otherwise, add freed node to the start of the list
- Update NextNodeOffset and BufferSize to include the
+ Update NextNodeOffset and BufferSize to include the
size of BIOS_BUFFER_NODE
*/
AllocNodePtr->NextNodeOffset = FreedNodeOffset;
TempData8 &= 0x03;
TempData8 |= Data8;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
-
+
Data8 |= BIT2+BIT3;
Data8 &= ~BIT4;
TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
{
case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
- Data8 &= ~(UINT8)BIT6 ;
+ Data8 &= ~(UINT8)BIT6 ;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
- Data8 |= BIT6 ;
+ Data8 |= BIT6 ;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21
Status = AGESA_SUCCESS;
break;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
- Data8 |= BIT6 ;
+ Data8 |= BIT6 ;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25
Status = AGESA_SUCCESS;
break;
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-
+
#ifndef _BIOS_CALLOUT_H_
#define _BIOS_CALLOUT_H_
DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
- }
+ }
};
PCIe_DDI_DESCRIPTOR DdiList [] = {
//
// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
//
- AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) +
- sizeof (PCIe_PORT_DESCRIPTOR) * 5 +
+ AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) +
+ sizeof (PCIe_PORT_DESCRIPTOR) * 5 +
sizeof (PCIe_DDI_DESCRIPTOR)) * 2;
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
if ( Status!= AGESA_SUCCESS) {
// Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
- ASSERT(FALSE);
+ ASSERT(FALSE);
return;
}
-
+
BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR);
AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5;
BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
+
LibAmdMemFill (BrazosPcieComplexListPtr,
0,
sizeof (PCIe_COMPLEX_DESCRIPTOR),
0,
sizeof (PCIe_PORT_DESCRIPTOR) * 5,
&InitEarly->StdHeader);
-
+
LibAmdMemFill (BrazosPcieDdiPtr,
0,
sizeof (PCIe_DDI_DESCRIPTOR) * 2,
((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
- InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
- InitEarly->GnbConfig.PsppPolicy = 0;
+ InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
+ InitEarly->GnbConfig.PsppPolicy = 0;
}
#include "amdlib.h"
//GNB GPP Port4
-#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
+#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port5
-#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable
+#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port6
-#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable
+#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port7
-#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable
+#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port8
-#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable
+#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
OemCustomizeInitEarly (
IN OUT AMD_EARLY_PARAMS *InitEarly
);
-
+
#endif //_PLATFORM_GNB_PCIE_COMPLEX_H
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-
+
/**
* @file
*
#define INSTALL_FT1_SOCKET_SUPPORT TRUE
#define INSTALL_AM3_SOCKET_SUPPORT FALSE
-/*
- * Agesa optional capabilities selection.
+/*
+ * Agesa optional capabilities selection.
* Uncomment and mark FALSE those features you wish to include in the build.
* Comment out or mark TRUE those features you want to REMOVE from the build.
*/
-#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE
+#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE
#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE
#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE
#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE
#define BLDOPT_REMOVE_HT_ASSIST TRUE
#define BLDOPT_REMOVE_ATM_MODE TRUE
//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE
-//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE
+//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE
#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE
//#define BLDOPT_REMOVE_C6_STATE TRUE
#define BLDOPT_REMOVE_GFX_RECOVERY TRUE
#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000
-/*
- * Agesa configuration values selection.
+/*
+ * Agesa configuration values selection.
* Uncomment and specify the value for the configuration options
- * needed by the system.
+ * needed by the system.
*/
#include "AGESA.h"
#include "CommonReturns.h"
#*****************************************************************************
-#
+#
# This file is part of the coreboot project.
-#
+#
# Copyright (C) 2011 Advanced Micro Devices, Inc.
-#
+#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
-#
+#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
-#
+#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-
+
#include "Porting.h"
#include "AGESA.h"
#include "amdlib.h"
UINT64 limit;
address |= 1; // set read bit
-
+
__outbyte (iobase + 0, 0xFF); // clear error status
__outbyte (iobase + 1, 0x1F); // clear error status
__outbyte (iobase + 3, offset); // offset in eeprom
*
* readspd - Read one or more SPD bytes from a DIMM.
* Start with offset zero and read sequentially.
- * Optimization relies on autoincrement to avoid
+ * Optimization relies on autoincrement to avoid
* sending offset for every byte.
* Reads 128 bytes in 7-8 ms at 400 KHz.
*/
error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]);
if (error) return error;
}
-
+
return 0;
}
{
int spdAddress, ioBase;
- if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR;
- if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR;
+ if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR;
+ if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR;
if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR;
-
- spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId];
+
+ spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId];
if (spdAddress == 0) return AGESA_ERROR;
ioBase = 0xB00;
setupFch (ioBase);
* This is the call to AmdInitLate. It is really in the wrong place, conceptually,
* but functionally within the coreboot model, this is the best place to make the
* call. The logically correct place to call AmdInitLate is after PCI scan is done,
- * after the decision about S3 resume is made, and before the system tables are
- * written into RAM. The routine that is responsible for writing the tables is
- * "write_tables", called near the end of "hardwaremain". There is no platform
- * specific entry point between the S3 resume decision point and the call to
- * "write_tables", and the next platform specific entry points are the calls to
- * the ACPI table write functions. The first of ose would seem to be the right
- * place, but other table write functions, e.g. the PIRQ table write function, are
+ * after the decision about S3 resume is made, and before the system tables are
+ * written into RAM. The routine that is responsible for writing the tables is
+ * "write_tables", called near the end of "hardwaremain". There is no platform
+ * specific entry point between the S3 resume decision point and the call to
+ * "write_tables", and the next platform specific entry points are the calls to
+ * the ACPI table write functions. The first of ose would seem to be the right
+ * place, but other table write functions, e.g. the PIRQ table write function, are
* called before the ACPI tables are written. This routine is called at the beginning
* of each of the write functions called prior to the ACPI write functions, so this
* becomes the best place for this call.
*/
- status = agesawrapper_amdinitlate();
+ status = agesawrapper_amdinitlate();
if(status) {
printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
}
-
+
sbdn_sb800 = 0;
for (i = 0; i < 3; i++) {
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
-
+
u32 dword;
u8 byte;
-
+
ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
dword &= 0xFFFFFFF0;
smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
/* on board NIC & Slot PCIE. */
-
+
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
#*****************************************************************************
-#
+#
# This file is part of the coreboot project.
-#
+#
# Copyright (C) 2011 Advanced Micro Devices, Inc.
-#
+#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
-#
+#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
-#
+#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
}
}
}
-
+
Device (PS2K) {
Name (_HID, EisaId ("PNP0303"))
Name (_CRS, ResourceTemplate () {
return CalloutStatus;
}
}
-
+
return CalloutStatus;
}
} else {
/* Otherwise, add freed node to the start of the list
- Update NextNodeOffset and BufferSize to include the
+ Update NextNodeOffset and BufferSize to include the
size of BIOS_BUFFER_NODE
*/
AllocNodePtr->NextNodeOffset = FreedNodeOffset;
TempData8 &= 0x03;
TempData8 |= Data8;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8);
-
+
Data8 |= BIT2+BIT3;
Data8 &= ~BIT4;
TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
{
case AssertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
- Data8 &= ~(UINT8)BIT6 ;
+ Data8 &= ~(UINT8)BIT6 ;
Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21
Status = AGESA_SUCCESS;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21);
- Data8 |= BIT6 ;
+ Data8 |= BIT6 ;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21
Status = AGESA_SUCCESS;
break;
break;
case DeassertSlotReset:
Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
- Data8 |= BIT6 ;
+ Data8 |= BIT6 ;
Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25
Status = AGESA_SUCCESS;
break;
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-
+
#ifndef _BIOS_CALLOUT_H_
#define _BIOS_CALLOUT_H_
DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
- }
+ }
};
PCIe_DDI_DESCRIPTOR DdiList [] = {
//
// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
//
- AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) +
- sizeof (PCIe_PORT_DESCRIPTOR) * 5 +
+ AllocHeapParams.RequestedBufferSize = (sizeof (PCIe_COMPLEX_DESCRIPTOR) +
+ sizeof (PCIe_PORT_DESCRIPTOR) * 5 +
sizeof (PCIe_DDI_DESCRIPTOR)) * 2;
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
if ( Status!= AGESA_SUCCESS) {
// Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
- ASSERT(FALSE);
+ ASSERT(FALSE);
return;
}
-
+
BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
AllocHeapParams.BufferPtr += sizeof (PCIe_COMPLEX_DESCRIPTOR);
AllocHeapParams.BufferPtr += sizeof (PCIe_PORT_DESCRIPTOR) * 5;
BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
-
+
LibAmdMemFill (BrazosPcieComplexListPtr,
0,
sizeof (PCIe_COMPLEX_DESCRIPTOR),
0,
sizeof (PCIe_PORT_DESCRIPTOR) * 5,
&InitEarly->StdHeader);
-
+
LibAmdMemFill (BrazosPcieDdiPtr,
0,
sizeof (PCIe_DDI_DESCRIPTOR) * 2,
((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
- InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
- InitEarly->GnbConfig.PsppPolicy = 0;
+ InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
+ InitEarly->GnbConfig.PsppPolicy = 0;
}
#include "amdlib.h"
//GNB GPP Port4
-#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
+#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port5
-#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable
+#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port6
-#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable
+#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port7
-#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable
+#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
//GNB GPP Port8
-#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable
+#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1
-#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
+#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db)
//3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db)
#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced
OemCustomizeInitEarly (
IN OUT AMD_EARLY_PARAMS *InitEarly
);
-
+
#endif //_PLATFORM_GNB_PCIE_COMPLEX_H
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-
+
/**
* @file
*
#define INSTALL_FT1_SOCKET_SUPPORT TRUE
#define INSTALL_AM3_SOCKET_SUPPORT FALSE
-/*
- * Agesa optional capabilities selection.
+/*
+ * Agesa optional capabilities selection.
* Uncomment and mark FALSE those features you wish to include in the build.
* Comment out or mark TRUE those features you want to REMOVE from the build.
*/
-#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE
+#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE
#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE
#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE
#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE
#define BLDOPT_REMOVE_HT_ASSIST TRUE
#define BLDOPT_REMOVE_ATM_MODE TRUE
//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE
-//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE
+//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE
#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE
//#define BLDOPT_REMOVE_C6_STATE TRUE
#define BLDOPT_REMOVE_GFX_RECOVERY TRUE
#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000
-/*
- * Agesa configuration values selection.
+/*
+ * Agesa configuration values selection.
* Uncomment and specify the value for the configuration options
- * needed by the system.
+ * needed by the system.
*/
#include "AGESA.h"
#include "CommonReturns.h"
#*****************************************************************************
-#
+#
# This file is part of the coreboot project.
-#
+#
# Copyright (C) 2011 Advanced Micro Devices, Inc.
-#
+#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
-#
+#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
-#
+#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-
+
#include "Porting.h"
#include "AGESA.h"
#include "amdlib.h"
UINT64 limit;
address |= 1; // set read bit
-
+
__outbyte (iobase + 0, 0xFF); // clear error status
__outbyte (iobase + 1, 0x1F); // clear error status
__outbyte (iobase + 3, offset); // offset in eeprom
*
* readspd - Read one or more SPD bytes from a DIMM.
* Start with offset zero and read sequentially.
- * Optimization relies on autoincrement to avoid
+ * Optimization relies on autoincrement to avoid
* sending offset for every byte.
* Reads 128 bytes in 7-8 ms at 400 KHz.
*/
error = readSmbusByte (iobase, SmbusSlaveAddress, &buffer [index]);
if (error) return error;
}
-
+
return 0;
}
{
int spdAddress, ioBase;
- if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR;
- if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR;
+ if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR;
+ if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR;
if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR;
-
- spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId];
+
+ spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId];
if (spdAddress == 0) return AGESA_ERROR;
ioBase = 0xB00;
setupFch (ioBase);
* This is the call to AmdInitLate. It is really in the wrong place, conceptually,
* but functionally within the coreboot model, this is the best place to make the
* call. The logically correct place to call AmdInitLate is after PCI scan is done,
- * after the decision about S3 resume is made, and before the system tables are
- * written into RAM. The routine that is responsible for writing the tables is
- * "write_tables", called near the end of "hardwaremain". There is no platform
- * specific entry point between the S3 resume decision point and the call to
- * "write_tables", and the next platform specific entry points are the calls to
- * the ACPI table write functions. The first of ose would seem to be the right
- * place, but other table write functions, e.g. the PIRQ table write function, are
+ * after the decision about S3 resume is made, and before the system tables are
+ * written into RAM. The routine that is responsible for writing the tables is
+ * "write_tables", called near the end of "hardwaremain". There is no platform
+ * specific entry point between the S3 resume decision point and the call to
+ * "write_tables", and the next platform specific entry points are the calls to
+ * the ACPI table write functions. The first of ose would seem to be the right
+ * place, but other table write functions, e.g. the PIRQ table write function, are
* called before the ACPI tables are written. This routine is called at the beginning
* of each of the write functions called prior to the ACPI write functions, so this
* becomes the best place for this call.
*/
- status = agesawrapper_amdinitlate();
+ status = agesawrapper_amdinitlate();
if(status) {
printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
}
-
+
sbdn_sb800 = 0;
for (i = 0; i < 3; i++) {
mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
-
+
u32 dword;
u8 byte;
-
+
ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
dword &= 0xFFFFFFF0;
smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
/* on board NIC & Slot PCIE. */
-
+
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
/* Bus 0, Dev 0 - RS780 Host Controller */
/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-
+
Package(){0x0002FFFF, 0, INTC, 0 },
Package(){0x0002FFFF, 1, INTD, 0 },
Package(){0x0002FFFF, 2, INTA, 0 },
Package(){0x0002FFFF, 3, INTB, 0 },
-
+
/* Bus 0, Funct 8 - Southbridge port (normally hidden) */
/* SB devices */
Package(){0x0009FFFF, 1, 0, 18 },
Package(){0x0009FFFF, 2, 0, 19 },
Package(){0x0009FFFF, 3, 0, 10 },
-
+
/* Bus 0, Dev A - PCIe internal ethernet */
Package(){0x000AFFFF, 0, 0, 18 },
Package(){0x000AFFFF, 1, 0, 19 },
Package(){0x0000FFFF, 2, 0, 16 },
Package(){0x0000FFFF, 3, 0, 17 },
})
-
+
Name(PS9, Package(){
/* PCIe slot - Hooked to PCIe x1 */
Package(){0x0000FFFF, 0, INTD, 0 },
endchoice
-source "src/mainboard/asrock/939a785gmh/Kconfig"\r
+source "src/mainboard/asrock/939a785gmh/Kconfig"
source "src/mainboard/asrock/e350m1/Kconfig"
config MAINBOARD_VENDOR
#*****************************************************************************
-#
+#
# This file is part of the coreboot project.
-#
+#
# Copyright (C) 2011 Advanced Micro Devices, Inc.
-#
+#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
-#
+#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
-#
+#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
TRAP(0xc1)
}
}
-
+
Method (_Q09, 0)
{
Notify(BAT0, 0x80)
{
Notify(\_TZ.THRM, 0x80)
}
-
+
Method (_Q20, 0)
{
Notify(\_SB.ECO, 0x81)
}
Return (0)
}
-
-
+
+
}
}
* MA 02110-1301 USA
*/
-/* This is board specific information: IRQ routing for the
+/* This is board specific information: IRQ routing for the
* i945
*/
* MA 02110-1301 USA
*/
-/* This is board specific information: IRQ routing for the
+/* This is board specific information: IRQ routing for the
* 0:1e.0 PCI bridge of the ICH7
*/
Device (PWRB)
{
Name(_HID, EisaId("PNP0C0C"))
-
+
// Wake
Name(_PRW, Package(){0x1d, 0x04})
}
INFO, 1024
}
-/* The _PIC method is called by the OS to choose between interrupt
+/* The _PIC method is called by the OS to choose between interrupt
* routing via the i8259 interrupt controller or the APIC.
- *
+ *
* _PIC is called with a parameter of 0 for i8259 configuration and
* with a parameter of 1 for Local Apic/IOAPIC configuration.
*/
// Notify PCI Express slots in case a card
// was inserted while a sleep state was active.
-
+
If (LEqual(RP1D, 0)) {
Notify(\_SB.PCI0.RP01, 0)
}
Notify(\_SB.PCI0.RP04, 0)
}
- // Are we coming from S3?
+ // Are we coming from S3?
If (LEqual(Arg0, 3)) {
TRAP(0xeb)
TRAP(0x46)
}
- // Are we coming from S4?
+ // Are we coming from S4?
If (LEqual(Arg0, 4)) {
Notify(SLPB, 0x02)
If (DTSE) {
CreateByteField(RSRC, 0x05, IORH) // Why?
CreateByteField(RSRC,
\_SB.PCI0.LPCB.SIO1.UAR1._CRS._IRA._INT, IRQL)
-
+
Store (READ(0, 0x24, 0xff), Local0)
And (Local0, 0xc0, Local1)
ShiftRight(Local1, 0x06, Local1)
CreateByteField(RSRC, 0x05, IORH)
CreateByteField(RSRC,
\_SB.PCI0.LPCB.SIO1.UAR2._CRS._IRB._INT, IRQL)
-
+
Store (READ(0, 0x25, 0xff), Local0)
And (Local0, 0xc0, Local1)
ShiftRight(Local1, 0x06, Local1)
CreateByteField(RSRC, 0x05, IORH) // Why?
CreateByteField(RSRC,
\_SB.PCI0.LPCB.SIO1.UAR3._CRS._IRA._INT, IRQL)
-
+
Store (READ(0, 0x1b, 0xff), Local0)
And (Local0, 0xc0, Local1)
ShiftRight(Local1, 0x06, Local1)
CreateByteField(RSRC, 0x05, IORH) // Why?
CreateByteField(RSRC,
\_SB.PCI0.LPCB.SIO1.UAR4._CRS._IRA._INT, IRQL)
-
+
Store (READ(0, 0x1c, 0xff), Local0)
And (Local0, 0xc0, Local1)
ShiftRight(Local1, 0x06, Local1)
ThermalZone (THRM)
{
// TODO These could/should be read from the
- // GNVS area, so they can be controlled by
+ // GNVS area, so they can be controlled by
// coreboot
Name(TC1V, 0x00)
Name(TC2V, 0x0a)
#
# This file is part of the coreboot project.
-#
+#
# Copyright (C) 2007-2008 coresystems GmbH
#
# This program is free software; you can redistribute it and/or
##
## This file is part of the coreboot project.
-##
+##
## Copyright (C) 2007-2009 coresystems GmbH
##
## This program is free software; you can redistribute it and/or
end
end
- device pci_domain 0 on
+ device pci_domain 0 on
device pci 00.0 on end # host bridge
# autodetect:
#device pci 01.0 off end # i945 PCIe root port
device pci 1d.7 on end # USB2 EHCI
device pci 1e.0 on
chip southbridge/ti/pcixx12
-
+
end
end # PCI bridge
- #device pci 1e.2 off end # AC'97 Audio
+ #device pci 1e.2 off end # AC'97 Audio
#device pci 1e.3 off end # AC'97 Modem
device pci 1f.0 on # LPC bridge
chip superio/smsc/fdc37n972
// mainboard specific devices
#include "acpi/mainboard.asl"
-
+
// Thermal Zone
#include "acpi/thermal.asl"
Store (ETBA, HPT)
Return (CRS)
}
-
+
}
#endif
}
select QRANK_DIMM_SUPPORT
select SET_FIDVID
select GFXUMA
- select EXT_CONF_SUPPORT
-
+ select EXT_CONF_SUPPORT
+
config MAINBOARD_DIR
string
default siemens/sitemp_g1p1
-
+
config LINT01_CONVERSION
bool
default y
config MAX_PHYSICAL_CPUS
int
default 1
-
+
config SB_HT_CHAIN_ON_BUS0
int
default 1
config IOMMU
bool
default n
-
+
config HW_SCRUBBER
bool
default n
-
+
config ECC_MEMORY
bool
default n
-
+
endif # BOARD_SIEMENS_SITEMP_G1P1
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-
+
/* Supported sleep states: */
Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-
+
/* Routing is in System Bus scope */
Scope(\_SB)
{
Package(){0x0013FFFF, 3, 0, 19 },
/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:AC97 Audio; F6:AC97 Modem */
- Package(){0x0014FFFF, 0, 0, 16 },
+ Package(){0x0014FFFF, 0, 0, 16 },
Package(){0x0014FFFF, 1, 0, 17 },
Package(){0x0014FFFF, 2, 0, 18 },
Package(){0x0014FFFF, 3, 0, 19 },
Package(){0x004FFFF, 0, \_SB.PCI0.LPC0.INTE, 0 },
Package(){0x004FFFF, 1, \_SB.PCI0.LPC0.INTF, 0 },
Package(){0x004FFFF, 2, \_SB.PCI0.LPC0.INTG, 0 },
- Package(){0x004FFFF, 3, \_SB.PCI0.LPC0.INTH, 0 },
+ Package(){0x004FFFF, 3, \_SB.PCI0.LPC0.INTH, 0 },
})
-
+
Name(AP2P, Package(){
/* PCI slots: slot 0 behind Dev14, Fun4. */
Package(){0x0005FFFF, 0, 0, 21 }, // Phoenix does it
Package(){0x0004FFFF, 2, 0, 22 },
Package(){0x0004FFFF, 3, 0, 23 },
})
-
+
}
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
*/
-
+
/* THERMAL */
Scope(\_TZ) {
Name (KELV, 2732)
/* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
}
}
-
+
// Processors used for active cooling
Method (_PSL, 0, Serialized)
{
}
Return (Package() {\_PR.CPU0})
}
-
+
Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
/* DBGO("\\_TZ\\TZ00\\_HOT\n") */
Return (Add (THOT, KELV))
}
} /* end of _TMP */
} /* end of TZ00 */
-}
\ No newline at end of file
+}
end
end
device pci_domain 0 on
- subsystemid 0x110a 0x4076 inherit
+ subsystemid 0x110a 0x4076 inherit
chip northbridge/amd/amdk8
device pci 18.0 on # southbridge
chip southbridge/amd/rs690
device pci 1.0 on # Internal Graphics P2P bridge 0x7912
device pci 5.0 on # Internal Graphics 0x791F
end
- device pci 5.2 on #
+ device pci 5.2 on #
end
end
device pci 2.0 on # PCIE P2P bridge 0x7913 (external GFX-port0)
Name(UOM7, 2)
Name(UOM8, 6)
Name(UOM9, 6)
-
- Name(DSEN, 1) // Display Output Switching Enable
+
+ Name(DSEN, 1) // Display Output Switching Enable
// Power notification
/* PIC IRQ mapping registers, C00h-C01h */
PCBA, 32,
MPEN, 8
}
-
+
Name (IOLM,0xe0000000)
-
-#include "acpi/platform.asl"
+
+#include "acpi/platform.asl"
Scope(\_SB) {
-
+
/* PCIe Configuration Space for 16 busses */
OperationRegion(PCFG, SystemMemory, PCBA, 0x2000000) /* PCIe reserved space for 31 busses */
Field(PCFG, ByteAcc, NoLock, Preserve) {
,14,
P92E, 1, /* Port92 decode enable */
}
-
+
OperationRegion(BAR5, SystemMemory, STB5, 0x1000)
Field(BAR5, AnyAcc, NoLock, Preserve)
{
P3PR, 1,
}
}
-#include "acpi/event.asl"
+#include "acpi/event.asl"
#include "acpi/routing.asl"
#include "acpi/usb.asl"
Scope(\_SB)
{
/* Start \_SB scope */
-
+
#include "acpi/globutil.asl"
Device(PWRB) { /* Start Power button device */
Name(_HID, EISAID("PNP0A03"))
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
-
+
Method(_BBN, 0) { /* Bus number = 0 */
Return(0)
- }
+ }
Method(_STA, 0) {
/* DBGO("\\_SB\\PCI0\\_STA\n") */
Return(0x0B) /* Status is visible */
}
-
+
Device (MEMR)
{
Name (_HID, EisaId ("PNP0C02"))
If(PCIF){ Return(APR0) } /* APIC mode */
Return (PR0) /* PIC Mode */
} /* end _PRT */
-
+
OperationRegion (BAR1, PCI_Config, 0x14, 0x04)
Field (BAR1, ByteAcc, NoLock, Preserve)
{
Z009, 32
}
-
+
/* Describe the Northbridge devices */
Device(AMRT) {
Name(_ADR, 0x00000000)
} /* end AMRT */
-
+
/* The internal GFX bridge */
Device(AGPB) {
Name(_ADR, 0x00010000)
Name(_PRW, Package() {0x18, 4})
Method(_PRT,0) {
If(PCIF){ Return(APS5) } /* APIC mode */
- Return (PS5) /* PIC Mode */
+ Return (PS5) /* PIC Mode */
} /* end _PRT */
} /* end PBR5 */
/* PCI slot 1 */
Device(PIBR) {
Name(_ADR, 0x00140004)
- Name(_PRW, Package() {4, 5}) // Phoenix doeas it so
+ Name(_PRW, Package() {4, 5}) // Phoenix doeas it so
Method(_PRT, 0) {
If(PCIF){ Return(AP2P) } /* APIC Mode */
Return (PCIB) /* PIC Mode */
/* Describe the Southbridge devices */
Device(SATA) {
Name(_ADR, 0x00120000)
-#include "acpi/sata.asl"
+#include "acpi/sata.asl"
} /* end SATA */
Device(UOH1) {
}
} /* end AZHD */
- Device(LPC0)
+ Device(LPC0)
{
Name (_ADR, 0x00140003)
Mutex (PSMX, 0x00)
-
+
/* PIC IRQ mapping registers, C00h-C01h */
OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
Field(PRQM, ByteAcc, NoLock, Preserve) {
PRQI, 0x00000008,
PRQD, 0x00000008, /* Offset: 1h */
}
-
+
IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
PINA, 0x00000008, /* Index 0 */
PINB, 0x00000008, /* Index 1 */
PING, 0x00000008, /* Index B */
PINH, 0x00000008, /* Index C */
}
-
+
Method(CIRQ, 0x00, NotSerialized)
{
Store(0, PINA)
Name(IRQP, ResourceTemplate(){
IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7}
})
-
+
Name(PITF, ResourceTemplate(){
IRQ(Level,ActiveLow,Exclusive){9}
- })
-
+ })
+
Device(INTA) {
Name(_HID, EISAID("PNP0C0F"))
Name(_UID, 1)
} /* Method(_SB.INTA._PRS) */
Method(_CRS ,0) {
- Store (IRQB, Local0) //
+ Store (IRQB, Local0) //
CreateWordField(Local0, 0x1, IRQ0)
ShiftLeft(1, PINA, IRQ0)
Return(Local0)
/* Use lowest available IRQ */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
- Store(Local0, PINB)
+ Store(Local0, PINB)
} /* End Method(_SB.INTB._SRS) */
} /* End Device(INTB) */
/* Use lowest available IRQ */
FindSetRightBit(IRQ0, Local0)
Decrement(Local0)
- Store(Local0, PINC)
+ Store(Local0, PINC)
} /* End Method(_SB.INTC._SRS) */
} /* End Device(INTC) */
Device(INTE) {
Name(_HID, EISAID("PNP0C0F"))
Name(_UID, 5)
-
+
Method(_STA, 0) {
if (PINE) {
Return(0x0B) /* sata is invisible */
Store(0, PINE)
} /* End Method(_SB.INTE._DIS) */
- Method(_PRS ,0) {
+ Method(_PRS ,0) {
Return(IRQB) // Return(IRQP)
}
Store(Local0, PINH)
} /* End Method(_SB.INTH._SRS) */
} /* End Device(INTH) */
-
+
/* Real Time Clock Device */
Device(RTC0) {
Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
Name(_CRS, ResourceTemplate() {
IO(Decode16, 0x00F0, 0x00F0, 1, 0x10)
- IRQ (Edge, ActiveHigh, Exclusive, ) {13}
+ IRQ (Edge, ActiveHigh, Exclusive, ) {13}
})
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
Return(CRS)
}
}
-
+
Device (KBC0)
{
Name (_HID, EisaId ("PNP0303"))
IRQ (Edge, ActiveHigh, Exclusive, ) {1}
})
}
-
+
Device (MSE0)
{
Name (_HID, EisaId ("PNP0F13"))
Name(_ADR, 0x00140005)
Name (_PRW, Package (0x02)
{
- 0x0C,
+ 0x0C,
0x04
})
} /* end Ac97audio */
Name(_ADR, 0x00140006)
Name (_PRW, Package (0x02)
{
- 0x0C,
+ 0x0C,
0x04
})
} /* end Ac97modem */
CreateDWordField(CRES, ^EMM2._MIN, EM2B)
CreateDWordField(CRES, ^EMM2._MAX, EM2E)
CreateDWordField(CRES, ^EMM2._LEN, EM2L)
-
+
Store(TOM1, EM2B)
Subtract(IOLM, 1, EM2E)
Subtract(IOLM, TOM1, EM2L)
SCMD, 8, /* SMBUS shaow cmd */
SEVT, 8, /* SMBUS slave event */
SDAT, 8, /* SMBUS slave data */
- SMK1, 8,
- SLMC, 8,
- RADD, 8,
+ SMK1, 8,
+ SLMC, 8,
+ RADD, 8,
SADD, 8
}
##
chip northbridge/amd/gx2
- device pci_domain 0 on
+ device pci_domain 0 on
device pci 1.0 on end # Geode GX2 Host Bridge
device pci 1.1 on end # Geode GX2 Graphics Processor
chip southbridge/amd/cs5536
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
-
+
driver-y += northbridge.c
-ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ssdt.asl
\ No newline at end of file
+ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ssdt.asl
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
-
+
driver-y += northbridge.c
help
Select this for boards with a Voltage Regulator able to operate
at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.
-
+
source src/northbridge/amd/amdfam10/root_complex/Kconfig
/* we are ignoring the 5530 case for now, and perhaps forever. */
/* 553X NB Init */
-
+
/* Arbiter setup */
msrnum = GLPCI_ARB;
msr = rdmsr(msrnum);
static void GeodeLinkPriority(void)
{
msr_t msr = { 0, 0 };
-
+
struct msrinit *prio = GeodeLinkPriorityTable;
int i;
static uint64_t getShadow(void)
{
msr_t msr = { 0, 0 };
-
+
msr = rdmsr(GLIU0_P2D_SC_0);
return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo;
}
config USBDEBUG_DEFAULT_PORT
int
- default 1
+ default 1
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
rm -rf out
mkdir out
-
+
# walk through all ACPI tables with their addresses
-# example:
+# example:
# RSDT @ 0xcf6794ba
-# we can not just dump the tables by their names because some
+# we can not just dump the tables by their names because some
# machines have double ACPI tables
acpidump | grep "@ 0x" | while read line
INSTALL = /usr/bin/install
PREFIX = /usr/local
CFLAGS = -O2 -g -Wall -W
-LDFLAGS =
+LDFLAGS =
OBJS = ifdtool.o
mkdir -p $(DESTDIR)$(PREFIX)/share/man/man8
$(INSTALL) $(PROGRAM).8 $(DESTDIR)$(PREFIX)/share/man/man8
-.PHONY: all clean distclean dep
+.PHONY: all clean distclean dep
-include .dependencies
SCANBUCKET=`mktemp`
LC_ALL=C export LC_ALL
find src -name .svn -type d -prune -o -name mainboard -type d -prune -o -name examples -type d -prune -o -type f -exec sed -nf `dirname $0`/remccoms3.sed {} + > $SCANBUCKET
-
+
for define in $DEFINES; do
if [ `egrep -c "([^_A-Za-z0-9]$define[^_A-Za-z0-9]|^$define[^_A-Za-z0-9]|[^_A-Za-z0-9]$define\$)" $SCANBUCKET` -gt 0 ]; then
echo "$define is defined in mainboard(s) and used elsewhere"
s,\n\(.[^\"]*\).*,\1,
x
s,.[^\"]*,,
-
+
/^"/b break
/^\\/{
H
s,\n\(.[^\']*\).*,\1,
x
s,.[^\']*,,
-
+
/^'/b break
/^\\/{
H
if test $libc_cv_fno_stack_protector = yes; then
I386_CFLAGS="$I386_CFLAGS -fno-stack-protector"
IA64_CFLAGS="$IA64_CFLAGS -fno-stack-protector"
-
+
fi
AC_SUBST(libc_cv_fno_stack_protector)
projects / coreboot.git / commitdiff