2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007-2009 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 config NORTHBRIDGE_AMD_AMDFAM10
22 select HAVE_DEBUG_RAM_SETUP
23 select HAVE_DEBUG_SMBUS
25 select HYPERTRANSPORT_PLUGIN_SUPPORT
26 select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX
29 if NORTHBRIDGE_AMD_AMDFAM10
30 config AGP_APERTURE_SIZE
46 config HW_MEM_HOLE_SIZEK
50 config HW_MEM_HOLE_SIZE_AUTO_INC
54 config MMCONF_BASE_ADDRESS
58 config MMCONF_BUS_NUMBER
62 config BOOTBLOCK_NORTHBRIDGE_INIT
64 default "northbridge/amd/amdfam10/bootblock.c"
66 config SB_HT_CHAIN_UNITID_OFFSET_ONLY
82 config DIMM_REGISTERED
118 depends on NORTHBRIDGE_AMD_AMDFAM10
120 Select this for boards with a Voltage Regulator able to operate
121 at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.
123 source src/northbridge/amd/amdfam10/root_complex/Kconfig