2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 Advanced Micro Devices, Inc.
5 * Copyright (C) 2010 Siemens AG, Inc.
6 * (Written by Josef Kellermann <joseph.kellermann@heitec.de> for Siemens AG, Inc.)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 DefinitionBlock ("DSDT.aml", "DSDT", 2, "SIEMENS", "SITEMP ", 0x20101005)
24 /* Data to be patched by the BIOS during POST */
25 /* Memory related values */
26 Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
27 Name(HPBA, 0xFED00000) /* Base address of HPET table */
29 /* USB overcurrent mapping pins. */
41 Name(DSEN, 1) // Display Output Switching Enable
44 /* PIC IRQ mapping registers, C00h-C01h */
45 OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
46 Field(PRQM, ByteAcc, NoLock, Preserve) {
48 PRQD, 0x00000008, /* Offset: 1h */
50 IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
51 PINA, 0x00000008, /* Index 0 */
52 PINB, 0x00000008, /* Index 1 */
53 PINC, 0x00000008, /* Index 2 */
54 PIND, 0x00000008, /* Index 3 */
55 SINT, 0x00000008, /* Index 4 */
57 PINE, 0x00000008, /* Index 9 */
58 PINF, 0x00000008, /* Index A */
59 PING, 0x00000008, /* Index B */
60 PINH, 0x00000008, /* Index C */
63 /* PCI Error control register */
64 OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
65 Field(PERC, ByteAcc, NoLock, Preserve) {
72 /* Client Management index/data registers */
73 OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
74 Field(CMT, ByteAcc, NoLock, Preserve) {
76 /* Client Management Data register */
84 /* GPM Port register */
85 OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
86 Field(GPT, ByteAcc, NoLock, Preserve) {
97 /* Flash ROM program enable register */
98 OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
99 Field(FRE, ByteAcc, NoLock, Preserve) {
104 /* PM2 index/data registers */
105 OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
106 Field(PM2R, ByteAcc, NoLock, Preserve) {
111 /* Power Management I/O registers */
112 OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
113 Field(PIOR, ByteAcc, NoLock, Preserve) {
117 IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
118 Offset(0x00), /* MiscControl */
122 Offset(0x01), /* MiscStatus */
126 Offset(0x04), /* SmiWakeUpEventEnable3 */
129 Offset(0x07), /* SmiWakeUpEventStatus3 */
132 Offset(0x10), /* AcpiEnable */
135 Offset(0x1C), /* ProgramIoEnable */
142 Offset(0x1D), /* IOMonitorStatus */
149 Offset(0x20), /* AcpiPmEvtBlk */
151 Offset(0x36), /* GEvtLevelConfig */
155 Offset(0x37), /* GPMLevelConfig0 */
162 Offset(0x38), /* GPMLevelConfig1 */
169 Offset(0x3B), /* PMEStatus1 */
178 Offset(0x55), /* SoftPciRst */
186 /* Offset(0x61), */ /* Options_1 */
190 Offset(0x65), /* UsbPMControl */
193 Offset(0x68), /* MiscEnable68 */
197 Offset(0x92), /* GEVENTIN */
200 Offset(0x96), /* GPM98IN */
203 Offset(0x9A), /* EnhanceControl */
206 Offset(0xA8), /* PIO7654Enable */
211 Offset(0xA9), /* PIO7654Status */
219 * First word is PM1_Status, Second word is PM1_Enable
221 OperationRegion(P1EB, SystemIO, APEB, 0x04)
222 Field(P1EB, ByteAcc, NoLock, Preserve) {
246 OperationRegion (GVAR, SystemMemory, 0xBADEAFFE, 0x100)
247 Field (GVAR, ByteAcc, NoLock, Preserve)
256 Name (IOLM,0xe0000000)
258 #include "acpi/platform.asl"
262 /* PCIe Configuration Space for 16 busses */
263 OperationRegion(PCFG, SystemMemory, PCBA, 0x2000000) /* PCIe reserved space for 31 busses */
264 Field(PCFG, ByteAcc, NoLock, Preserve) {
265 Offset(0x00090024), /* Byte offset to SATA BAR5 register 24h - Bus 0, Device 18, Function 0 */
267 Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
278 Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
281 Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
283 Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
285 Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
287 P92E, 1, /* Port92 decode enable */
290 OperationRegion(BAR5, SystemMemory, STB5, 0x1000)
291 Field(BAR5, AnyAcc, NoLock, Preserve)
294 Offset(0x120), /* Port 0 Task file status */
300 Offset(0x128), /* Port 0 Serial ATA status */
304 Offset(0x12C), /* Port 0 Serial ATA control */
306 Offset(0x130), /* Port 0 Serial ATA error */
311 offset(0x1A0), /* Port 1 Task file status */
317 Offset(0x1A8), /* Port 1 Serial ATA status */
321 Offset(0x1AC), /* Port 1 Serial ATA control */
323 Offset(0x1B0), /* Port 1 Serial ATA error */
328 Offset(0x220), /* Port 2 Task file status */
334 Offset(0x228), /* Port 2 Serial ATA status */
338 Offset(0x22C), /* Port 2 Serial ATA control */
340 Offset(0x230), /* Port 2 Serial ATA error */
345 Offset(0x2A0), /* Port 3 Task file status */
351 Offset(0x2A8), /* Port 3 Serial ATA status */
355 Offset(0x2AC), /* Port 3 Serial ATA control */
357 Offset(0x2B0), /* Port 3 Serial ATA error */
362 #include "acpi/event.asl"
363 #include "acpi/routing.asl"
364 #include "acpi/usb.asl"
369 /* Start \_SB scope */
371 #include "acpi/globutil.asl"
373 Device(PWRB) { /* Start Power button device */
374 Name(_HID, EISAID("PNP0C0C"))
376 Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
377 Name(_STA, 0x0B) /* sata is invisible */
380 /* Note: Only need HID on Primary Bus */
387 Name(_HID, EISAID("PNP0A03"))
388 Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
390 Method(_BBN, 0) { /* Bus number = 0 */
395 /* DBGO("\\_SB\\PCI0\\_STA\n") */
396 Return(0x0B) /* Status is visible */
401 Name (_HID, EisaId ("PNP0C02"))
402 Name (MEM1, ResourceTemplate ()
404 Memory32Fixed (ReadWrite,
405 0x00000000, // Address Base
406 0x00000000, // Address Length
408 Memory32Fixed (ReadWrite,
409 0x00000000, // Address Base
410 0x00000000, // Address Length
413 Method (_CRS, 0, NotSerialized)
415 CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1A._BAS, MB01)
416 CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1A._LEN, ML01)
417 CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1B._BAS, MB02)
418 CreateDWordField (MEM1, \_SB.PCI0.MEMR._Y1B._LEN, ML02)
421 Store (0xFEC00000, MB01)
422 Store (0xFEE00000, MB02)
432 If(PCIF){ Return(APR0) } /* APIC mode */
433 Return (PR0) /* PIC Mode */
436 OperationRegion (BAR1, PCI_Config, 0x14, 0x04)
437 Field (BAR1, ByteAcc, NoLock, Preserve)
442 /* Describe the Northbridge devices */
444 Name(_ADR, 0x00000000)
447 /* The internal GFX bridge */
449 Name(_ADR, 0x00010000)
450 Name(_PRW, Package() {0x18, 4})
451 Method(_PRT,0) { Return (APR1) }
455 Name (_ADR, 0x00050000)
458 /* Windows 2000 and Windows XP call _DOS to enable/disable
459 * Display Output Switching during init and while a switch
462 Store (And(Arg0, 7), DSEN)
464 Method (_STA, 0, NotSerialized)
471 /* The external GFX bridge */
473 Name(_ADR, 0x00020000)
474 Name(_PRW, Package() {0x18, 4})
476 If(PCIF){ Return(APS2) } /* APIC mode */
477 Return (PS2) /* PIC Mode */
481 /* Dev3 is also an external GFX bridge */
484 Name(_ADR, 0x00040000)
485 Name(_PRW, Package() {0x18, 4})
487 If(PCIF){ Return(APS4) } /* APIC mode */
488 Return (PS4) /* PIC Mode */
493 Name(_ADR, 0x00050000)
494 Name(_PRW, Package() {0x18, 4})
496 If(PCIF){ Return(APS5) } /* APIC mode */
497 Return (PS5) /* PIC Mode */
502 Name(_ADR, 0x00060000)
503 Name(_PRW, Package() {0x18, 4})
505 If(PCIF){ Return(APS6) } /* APIC mode */
506 Return (PS6) /* PIC Mode */
510 /* The onboard EtherNet chip */
512 Name(_ADR, 0x00070000)
513 Name(_PRW, Package() {0x18, 4})
515 If(PCIF){ Return(APS7) } /* APIC mode */
516 Return (PS7) /* PIC Mode */
522 Name(_ADR, 0x00140004)
523 Name(_PRW, Package() {4, 5}) // Phoenix doeas it so
525 If(PCIF){ Return(AP2P) } /* APIC Mode */
526 Return (PCIB) /* PIC Mode */
530 /* Describe the Southbridge devices */
532 Name(_ADR, 0x00120000)
533 #include "acpi/sata.asl"
537 Name(_ADR, 0x00130000)
538 Name(_PRW, Package() {0x0B, 3})
542 Name(_ADR, 0x00130001)
543 Name(_PRW, Package() {0x0B, 3})
547 Name(_ADR, 0x00130002)
548 Name(_PRW, Package() {0x0B, 3})
552 Name(_ADR, 0x00130003)
553 Name(_PRW, Package() {0x0B, 3})
557 Name(_ADR, 0x00130004)
558 Name(_PRW, Package() {0x0B, 3})
562 Name(_ADR, 0x00130005)
563 Name(_PRW, Package() {0x0B, 3})
567 Name(_ADR, 0x00140000)
570 /* Primary (and only) IDE channel */
572 Name(_ADR, 0x00140001)
573 #include "acpi/ide.asl"
577 Name(_ADR, 0x00140002)
578 OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
579 Field(AZPD, AnyAcc, NoLock, Preserve) {
603 If(LEqual(LINX,1)){ /* If we are running Linux */
613 Name (_ADR, 0x00140003)
616 /* PIC IRQ mapping registers, C00h-C01h */
617 OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
618 Field(PRQM, ByteAcc, NoLock, Preserve) {
620 PRQD, 0x00000008, /* Offset: 1h */
623 IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
624 PINA, 0x00000008, /* Index 0 */
625 PINB, 0x00000008, /* Index 1 */
626 PINC, 0x00000008, /* Index 2 */
627 PIND, 0x00000008, /* Index 3 */
628 SINT, 0x00000008, /* Index 4 */
630 PINE, 0x00000008, /* Index 9 */
631 PINF, 0x00000008, /* Index A */
632 PING, 0x00000008, /* Index B */
633 PINH, 0x00000008, /* Index C */
636 Method(CIRQ, 0x00, NotSerialized)
649 Name(IRQB, ResourceTemplate(){
650 IRQ(Level,ActiveLow,Shared){10,11}
653 Name(IRQP, ResourceTemplate(){
654 IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7}
657 Name(PITF, ResourceTemplate(){
658 IRQ(Level,ActiveLow,Exclusive){9}
662 Name(_HID, EISAID("PNP0C0F"))
667 Return(0x0B) /* sata is invisible */
669 Return(0x09) /* sata is disabled */
671 } /* End Method(_SB.INTA._STA) */
675 } /* End Method(_SB.INTA._DIS) */
678 Return(IRQB) // Return(IRQP)
679 } /* Method(_SB.INTA._PRS) */
682 Store (IRQB, Local0) //
683 CreateWordField(Local0, 0x1, IRQ0)
684 ShiftLeft(1, PINA, IRQ0)
686 } /* Method(_SB.INTA._CRS) */
688 CreateWordField(ARG0, 1, IRQ0)
689 /* Use lowest available IRQ */
690 FindSetRightBit(IRQ0, Local0)
693 } /* End Method(_SB.INTA._SRS) */
694 } /* End Device(INTA) */
697 Name(_HID, EISAID("PNP0C0F"))
702 Return(0x0B) /* sata is invisible */
704 Return(0x09) /* sata is disabled */
706 } /* End Method(_SB.INTB._STA) */
710 } /* End Method(_SB.INTB._DIS) */
713 Return(IRQB) // Return(IRQP)
714 } /* Method(_SB.INTB._PRS) */
717 Store (IRQB, Local0) // {10,11}
718 CreateWordField(Local0, 0x1, IRQ0)
719 ShiftLeft(1, PINB, IRQ0)
721 } /* Method(_SB.INTB._CRS) */
724 CreateWordField(ARG0, 1, IRQ0)
725 /* Use lowest available IRQ */
726 FindSetRightBit(IRQ0, Local0)
729 } /* End Method(_SB.INTB._SRS) */
730 } /* End Device(INTB) */
733 Name(_HID, EISAID("PNP0C0F"))
738 Return(0x0B) /* sata is invisible */
740 Return(0x09) /* sata is disabled */
742 } /* End Method(_SB.INTC._STA) */
746 } /* End Method(_SB.INTC._DIS) */
749 Return(IRQB) // Return(IRQP)
750 } /* Method(_SB.INTC._PRS) */
753 Store (IRQB, Local0) // {10,11}
754 CreateWordField(Local0, 0x1, IRQ0)
755 ShiftLeft(1, PINC, IRQ0)
757 } /* Method(_SB.INTC._CRS) */
760 CreateWordField(ARG0, 1, IRQ0)
761 /* Use lowest available IRQ */
762 FindSetRightBit(IRQ0, Local0)
765 } /* End Method(_SB.INTC._SRS) */
766 } /* End Device(INTC) */
769 Name(_HID, EISAID("PNP0C0F"))
774 Return(0x0B) /* sata is invisible */
776 Return(0x09) /* sata is disabled */
778 } /* End Method(_SB.INTD._STA) */
782 } /* End Method(_SB.INTD._DIS) */
785 Return(IRQB) // Return(IRQP)
786 } /* Method(_SB.INTD._PRS) */
789 Store (IRQB, Local0) // {10,11}
790 CreateWordField(Local0, 0x1, IRQ0)
791 ShiftLeft(1, PIND, IRQ0)
793 } /* Method(_SB.INTD._CRS) */
796 CreateWordField(ARG0, 1, IRQ0)
797 /* Use lowest available IRQ */
798 FindSetRightBit(IRQ0, Local0)
801 } /* End Method(_SB.INTD._SRS) */
802 } /* End Device(INTD) */
805 Name(_HID, EISAID("PNP0C0F"))
810 Return(0x0B) /* sata is invisible */
812 Return(0x09) /* sata is disabled */
814 } /* End Method(_SB.INTE._STA) */
818 } /* End Method(_SB.INTE._DIS) */
821 Return(IRQB) // Return(IRQP)
825 Store (IRQB, Local0) // {10,11}
826 CreateWordField(Local0, 0x1, IRQ0)
827 ShiftLeft(1, PINE, IRQ0)
829 } /* Method(_SB.INTE._CRS) */
832 CreateWordField(ARG0, 1, IRQ0)
833 /* Use lowest available IRQ */
834 FindSetRightBit(IRQ0, Local0)
837 } /* End Method(_SB.INTE._SRS) */
838 } /* End Device(INTE) */
841 Name(_HID, EISAID("PNP0C0F"))
846 Return(0x0B) /* sata is invisible */
848 Return(0x09) /* sata is disabled */
850 } /* End Method(_SB.INTF._STA) */
854 } /* End Method(_SB.INTF._DIS) */
857 Return(IRQB) // Return(PITF)
858 } /* Method(_SB.INTF._PRS) */
861 Store (IRQB, Local0) // {10,11}
862 CreateWordField(Local0, 0x1, IRQ0)
863 ShiftLeft(1, PINF, IRQ0)
865 } /* Method(_SB.INTF._CRS) */
868 CreateWordField(ARG0, 1, IRQ0)
869 /* Use lowest available IRQ */
870 FindSetRightBit(IRQ0, Local0)
873 } /* End Method(_SB.INTF._SRS) */
874 } /* End Device(INTF) */
877 Name(_HID, EISAID("PNP0C0F"))
882 Return(0x0B) /* sata is invisible */
884 Return(0x09) /* sata is disabled */
886 } /* End Method(_SB.INTG._STA) */
890 } /* End Method(_SB.INTG._DIS) */
893 Return(IRQB) // Return(IRQP)
894 } /* Method(_SB.INTG._CRS) */
897 Store (IRQB, Local0) // {10,11}
898 CreateWordField(Local0, 0x1, IRQ0)
899 ShiftLeft(1, PING, IRQ0)
901 } /* Method(_SB.INTG._CRS) */
904 CreateWordField(ARG0, 1, IRQ0)
905 /* Use lowest available IRQ */
906 FindSetRightBit(IRQ0, Local0)
909 } /* End Method(_SB.INTG._SRS) */
910 } /* End Device(INTG) */
913 Name(_HID, EISAID("PNP0C0F"))
918 Return(0x0B) /* sata is invisible */
920 Return(0x09) /* sata is disabled */
922 } /* End Method(_SB.INTH._STA) */
926 } /* End Method(_SB.INTH._DIS) */
929 Return(IRQB) // Return(IRQP)
930 } /* Method(_SB.INTH._CRS) */
933 Store (IRQB, Local0) // {10,11}
934 CreateWordField(Local0, 0x1, IRQ0)
935 ShiftLeft(1, PINH, IRQ0)
937 } /* Method(_SB.INTH._CRS) */
940 CreateWordField(ARG0, 1, IRQ0)
941 /* Use lowest available IRQ */
942 FindSetRightBit(IRQ0, Local0)
945 } /* End Method(_SB.INTH._SRS) */
946 } /* End Device(INTH) */
949 /* Real Time Clock Device */
951 Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible)*/
952 Name(_CRS, ResourceTemplate() {
953 IRQ (Edge, ActiveHigh, Exclusive, ) {8}
954 IO(Decode16,0x0070, 0x0070, 1, 2)
955 /* IO(Decode16,0x0070, 0x0070, 0, 4) */
957 } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
959 Device(TMR) { /* Timer */
960 Name(_HID,EISAID("PNP0100")) /* System Timer */
961 Name(_CRS, ResourceTemplate() {
962 IRQ (Edge, ActiveHigh, Exclusive, ) {0}
963 IO(Decode16, 0x0040, 0x0040, 1, 4)
964 /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
966 } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
968 Device(SPKR) { /* Speaker */
969 Name(_HID,EISAID("PNP0800")) /* AT style speaker */
970 Name(_CRS, ResourceTemplate() {
971 IO(Decode16, 0x0061, 0x0061, 1, 1)
973 } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
976 Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
977 Name(_CRS, ResourceTemplate() {
978 IRQ (Edge, ActiveHigh, Exclusive, ) {2}
979 IO(Decode16,0x0020, 0x0020, 1, 2)
980 IO(Decode16,0x00A0, 0x00A0, 0, 2)
981 /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
982 /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
984 } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
986 Device(MAD) { /* 8257 DMA */
987 Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
988 Name(_CRS, ResourceTemplate() {
989 DMA(Compatibility,NotBusMaster,Transfer8_16){4}
990 IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
991 IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
992 IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
993 IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
994 IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
995 IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
996 }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
997 } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
1000 Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
1001 Name(_CRS, ResourceTemplate() {
1002 IO(Decode16, 0x00F0, 0x00F0, 1, 0x10)
1003 IRQ (Edge, ActiveHigh, Exclusive, ) {13}
1005 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1008 Name(_HID,EISAID("PNP0103"))
1009 Name(CRS,ResourceTemplate() {
1010 Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
1013 Return(0x0F) /* sata is visible */
1016 CreateDwordField(CRS, ^HPT._BAS, HPBA)
1024 Name (_HID, EisaId ("PNP0303"))
1025 Name (_CRS, ResourceTemplate ()
1028 0x0060, // Range Minimum
1029 0x0060, // Range Maximum
1034 0x0064, // Range Minimum
1035 0x0064, // Range Maximum
1039 IRQ (Edge, ActiveHigh, Exclusive, ) {1}
1045 Name (_HID, EisaId ("PNP0F13"))
1046 Name (_CRS, ResourceTemplate ()
1048 IRQ (Edge, ActiveHigh, Exclusive, ) {12}
1054 Name(_ADR, 0x00140005)
1055 Name (_PRW, Package (0x02)
1060 } /* end Ac97audio */
1063 Name(_ADR, 0x00140006)
1064 Name (_PRW, Package (0x02)
1069 } /* end Ac97modem */
1071 /* ITE IT8712F Support */
1072 OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
1073 Field (IOID, ByteAcc, NoLock, Preserve)
1075 SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */
1078 IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
1081 LDN, 8, /* Logical Device Number */
1083 CID1, 8, /* Chip ID Byte 1, 0x87 */
1084 CID2, 8, /* Chip ID Byte 2, 0x12 */
1086 ACTR, 8, /* Function activate */
1088 APC0, 8, /* APC/PME Event Enable Register */
1089 APC1, 8, /* APC/PME Status Register */
1090 APC2, 8, /* APC/PME Control Register 1 */
1091 APC3, 8, /* Environment Controller Special Configuration Register */
1092 APC4, 8 /* APC/PME Control Register 2 */
1095 /* Enter the IT8712F MB PnP Mode */
1101 Store(0x55, SIOI) /* IT8712F magic number */
1103 /* Exit the IT8712F MB PnP Mode */
1111 * Keyboard PME is routed to SB600 Gevent3. We can wake
1112 * up the system by pressing the key.
1116 /* We only enable KBD PME for S5. */
1117 If (LLess (Arg0, 0x05))
1120 /* DBGO("IT8712F\n") */
1123 Store (One, ACTR) /* Enable EC */
1127 */ /* falling edge. which mode? Not sure. */
1130 Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
1132 Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
1141 Store (Zero, APC0) /* disable keyboard PME */
1143 Store (0xFF, APC1) /* clear keyboard PME status */
1147 /* ############################################################################################### */
1148 Name(CRES, ResourceTemplate() {
1149 IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
1151 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1152 0x0000, /* address granularity */
1153 0x0000, /* range minimum */
1154 0x0CF7, /* range maximum */
1155 0x0000, /* translation */
1159 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1160 0x0000, /* address granularity */
1161 0x0D00, /* range minimum */
1162 0xFFFF, /* range maximum */
1163 0x0000, /* translation */
1167 Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
1168 Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
1169 Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
1171 /* DRAM Memory from 1MB to TopMem */
1172 DWORDMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0, 0, 0, 0x00, 1, ,, EMM2)
1173 WORDIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, 0x00, 0x0D00, 0xffff, 0x00, 0xf300)
1174 }) /* End Name(_SB.PCI0.CRES) */
1178 /* DBGO("\\_SB\\PCI0\\_CRS\n") */
1180 CreateDWordField(CRES, ^EMM1._BAS, EM1B)
1181 CreateDWordField(CRES, ^EMM1._LEN, EM1L)
1183 CreateDWordField(CRES, ^EMM2._MIN, EM2B)
1184 CreateDWordField(CRES, ^EMM2._MAX, EM2E)
1185 CreateDWordField(CRES, ^EMM2._LEN, EM2L)
1188 Subtract(IOLM, 1, EM2E)
1189 Subtract(IOLM, TOM1, EM2L)
1191 If(LGreater(LOMH, 0xC0000)){
1192 Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
1193 Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
1196 Return(CRES) /* note to change the Name buffer */
1198 /* ########################################################################################## */
1199 } /* End Device(PCI0) */
1200 } /* End \_SB scope */
1204 /* DBGO("\\_SI\\_SST\n") */
1205 /* DBGO(" New Indicator state: ") */
1209 } /* End Scope SI */
1212 OperationRegion (SMB0, SystemIO, 0xB00, 0x10) // 0x0C replace by 0x10
1213 Field (SMB0, ByteAcc, NoLock, Preserve) {
1214 HSTS, 8, /* SMBUS status */
1215 SSTS, 8, /* SMBUS slave status */
1216 HCNT, 8, /* SMBUS control */
1217 HCMD, 8, /* SMBUS host cmd */
1218 HADD, 8, /* SMBUS address */
1219 DAT0, 8, /* SMBUS data0 */
1220 DAT1, 8, /* SMBUS data1 */
1221 BLKD, 8, /* SMBUS block data */
1222 SCNT, 8, /* SMBUS slave control */
1223 SCMD, 8, /* SMBUS shaow cmd */
1224 SEVT, 8, /* SMBUS slave event */
1225 SDAT, 8, /* SMBUS slave data */
1232 Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */
1234 Store (0xFA, Local0)
1235 While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) {
1243 Method (SWTC, 1, NotSerialized) {
1244 Store (Arg0, Local0)
1245 Store (0x07, Local2)
1247 While (LEqual (Local1, One)) {
1248 Store (And (HSTS, 0x1E), Local3)
1249 If (LNotEqual (Local3, Zero)) { /* read sucess */
1250 If (LEqual (Local3, 0x02)) {
1251 Store (Zero, Local2)
1254 Store (Zero, Local1)
1257 If (LLess (Local0, 0x0A)) { /* read failure */
1258 Store (0x10, Local2)
1259 Store (Zero, Local1)
1262 Sleep (0x0A) /* 10 ms, try again */
1263 Subtract (Local0, 0x0A, Local0)
1271 Method (SMBR, 3, NotSerialized) {
1272 Store (0x07, Local0)
1273 If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) {
1274 Store (WCLR (), Local0) /* clear SMBUS status register before read data */
1275 If (LEqual (Local0, Zero)) {
1281 Store (Or (ShiftLeft (Arg1, One), One), HADD)
1283 If (LEqual (Arg0, 0x07)) {
1284 Store (0x48, HCNT) /* read byte */
1287 Store (SWTC (0x03E8), Local1) /* 1000 ms */
1288 If (LEqual (Local1, Zero)) {
1289 If (LEqual (Arg0, 0x07)) {
1290 Store (DAT0, Local0)
1294 Store (Local1, Local0)
1300 /* DBGO("the value of SMBusData0 register ") */
1308 #include "acpi/thermal.asl"