src/mainboard/amd/torpedo/dsdt.asl

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 /* DefinitionBlock Statement */
  21 DefinitionBlock (
  22         "DSDT.AML",           /* Output filename */
  23         "DSDT",                 /* Signature */
  24         0x02,           /* DSDT Revision, needs to be 2 for 64bit */
  25         "AMD   ",               /* OEMID */
  26         "TORPEDO ",          /* TABLE ID */
  27         0x00010001      /* OEM Revision */
  28         )
  29 {       /* Start of ASL file */
  30         /* #include "../../../arch/x86/acpi/debug.asl" */       /* Include global debug methods if needed */
  31
  32         /* Data to be patched by the BIOS during POST */
  33         /* FIXME the patching is not done yet! */
  34         /* Memory related values */
  35         Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
  36         Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
  37         Name(PBLN, 0x0) /* Length of BIOS area */
  38
  39         Name(PCBA, 0xE0000000)  /* Base address of PCIe config space */
  40         Name(HPBA, 0xFED00000)  /* Base address of HPET table */
  41
  42         Name(SSFG, 0x0D)                /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
  43
  44         /* Some global data */
  45         Name(OSV, Ones) /* Assume nothing */
  46         Name(GPIC, 0x1) /* Assume PIC */
  47
  48         /*
  49          * Processor Object
  50          *
  51          */
  52         Scope (\_PR) {          /* define processor scope */
  53                 Processor(
  54                         CPU0,           /* name space name */
  55                         0,              /* Unique number for this processor */
  56                         0x810,          /* PBLK system I/O address !hardcoded! */
  57                         0x06            /* PBLKLEN for boot processor */
  58                         ) {
  59                         #include "acpi/cpstate.asl"
  60                 }
  61                 Processor(
  62                         CPU1,           /* name space name */
  63                         1,              /* Unique number for this processor */
  64                         0x0000,         /* PBLK system I/O address !hardcoded! */
  65                         0x00            /* PBLKLEN for boot processor */
  66                         ) {
  67                         #include "acpi/cpstate.asl"
  68                 }
  69                 Processor(
  70                         CPU2,           /* name space name */
  71                         2,              /* Unique number for this processor */
  72                         0x0000,         /* PBLK system I/O address !hardcoded! */
  73                         0x00            /* PBLKLEN for boot processor */
  74                         ) {
  75                         #include "acpi/cpstate.asl"
  76                 }
  77                 Processor(
  78                         CPU3,           /* name space name */
  79                         3,              /* Unique number for this processor */
  80                         0x0000,         /* PBLK system I/O address !hardcoded! */
  81                         0x00            /* PBLKLEN for boot processor */
  82                         ) {
  83                         #include "acpi/cpstate.asl"
  84                 }
  85         } /* End _PR scope */
  86
  87         /* PIC IRQ mapping registers, C00h-C01h. */
  88         OperationRegion(PIRQ, SystemIO, 0x00000C00, 0x00000002)
  89                 Field(PIRQ, ByteAcc, NoLock, Preserve) {
  90                 PIDX, 0x00000008,
  91                 PDAT, 0x00000008,  /* Offset: 1h */
  92         }
  93         IndexField(PIDX, PDAT, ByteAcc, NoLock, Preserve) {
  94                 PIRA, 0x00000008,       /* Index 0 */
  95                 PIRB, 0x00000008,       /* Index 1 */
  96                 PIRC, 0x00000008,       /* Index 2 */
  97                 PIRD, 0x00000008,       /* Index 3 */
  98                 PIRE, 0x00000008,       /* Index 4 */
  99                 PIRF, 0x00000008,       /* Index 5 */
 100                 PIRG, 0x00000008,       /* Index 6 */
 101                 PIRH, 0x00000008,       /* Index 7 */
 102                 Offset(0x10),
 103                 PIRS, 0x00000008,
 104                 Offset(0x13),
 105                 HDAD, 0x00000008,
 106                 , 0x00000008,
 107                 GEC,  0x00000008,
 108                 Offset(0x30),
 109                 USB1, 0x00000008,
 110                 USB2, 0x00000008,
 111                 USB3, 0x00000008,
 112                 USB4, 0x00000008,
 113                 USB5, 0x00000008,
 114                 USB6, 0x00000008,
 115                 USB7, 0x00000008,
 116                 Offset(0x40),
 117                 IDE,  0x00000008,
 118                 SATA, 0x00000008,
 119                 Offset(0x50),
 120                 GPP0, 0x00000008,
 121                 GPP1, 0x00000008,
 122                 GPP2, 0x00000008,
 123                 GPP3, 0x00000008
 124         }
 125
 126         /* PCI Error control register */
 127         OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
 128                 Field(PERC, ByteAcc, NoLock, Preserve) {
 129                 SENS, 0x00000001,
 130                 PENS, 0x00000001,
 131                 SENE, 0x00000001,
 132                 PENE, 0x00000001,
 133         }
 134
 135         /* Client Management index/data registers */
 136         OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
 137                 Field(CMT, ByteAcc, NoLock, Preserve) {
 138                 CMTI,      8,
 139                 /* Client Management Data register */
 140                 G64E,   1,
 141                 G64O,      1,
 142                 G32O,      2,
 143                 ,       2,
 144                 GPSL,     2,
 145         }
 146
 147         /* GPM Port register */
 148         OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
 149                 Field(GPT, ByteAcc, NoLock, Preserve) {
 150                 GPB0,1,
 151                 GPB1,1,
 152                 GPB2,1,
 153                 GPB3,1,
 154                 GPB4,1,
 155                 GPB5,1,
 156                 GPB6,1,
 157                 GPB7,1,
 158         }
 159
 160         /* Flash ROM program enable register */
 161         OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
 162                 Field(FRE, ByteAcc, NoLock, Preserve) {
 163                 ,     0x00000006,
 164                 FLRE, 0x00000001,
 165         }
 166
 167         /* PM2 index/data registers */
 168         OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
 169                 Field(PM2R, ByteAcc, NoLock, Preserve) {
 170                 PM2I, 0x00000008,
 171                 PM2D, 0x00000008,
 172         }
 173
 174         /* Power Management I/O registers, TODO:PMIO is quite different in SB900. */
 175         OperationRegion(PMRG, SystemIO, 0x00000CD6, 0x00000002)
 176                 Field(PMRG, ByteAcc, NoLock, Preserve) {
 177                 PMRI, 0x00000008,
 178                 PMRD, 0x00000008,
 179         }
 180         IndexField (PMRI, PMRD, ByteAcc, NoLock, Preserve) {
 181                 Offset(0x24),
 182                 MMSO,32,
 183                 Offset(0x37),   /* GPMLevelConfig0 */
 184                 , 3,
 185                 PLC0, 1,
 186                 PLC1, 1,
 187                 PLC2, 1,
 188                 PLC3, 1,
 189                 PLC8, 1,
 190                 Offset(0x38),   /* GPMLevelConfig1 */
 191                 , 1,
 192                  PLC4, 1,
 193                  PLC5, 1,
 194                 , 1,
 195                  PLC6, 1,
 196                  PLC7, 1,
 197                 Offset(0x50),
 198                 HPAD,32,
 199                 Offset(0x60),
 200                 P1EB,16,
 201                 Offset(0x65),   /* UsbPMControl */
 202                 , 4,
 203                 URRE, 1,
 204                 Offset(0x96),   /* GPM98IN */
 205                 G8IS, 1,
 206                 G9IS, 1,
 207                 Offset(0x9A),   /* EnhanceControl */
 208                 ,7,
 209                 HPDE, 1,
 210                 Offset(0xC8),
 211                 ,2,
 212                 SPRE,1,
 213                 TPDE,1,
 214                 Offset(0xF0),
 215                 ,3,
 216                 RSTU,1
 217         }
 218
 219         /* PM1 Event Block
 220         * First word is PM1_Status, Second word is PM1_Enable
 221         */
 222         OperationRegion(P1E0, SystemIO, P1EB, 0x04)
 223                 Field(P1E0, ByteAcc, NoLock, Preserve) {
 224                 ,14,
 225                 PEWS,1,
 226                 WSTA,1,
 227                 ,14,
 228                 PEWD,1
 229         }
 230
 231     OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
 232     Field (GRAM, ByteAcc, Lock, Preserve)
 233     {
 234         Offset (0x10),
 235         FLG0,   8
 236     }
 237
 238         Scope(\_SB) {
 239                 /* PCIe Configuration Space for 16 busses */
 240                 OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
 241                         Field(PCFG, ByteAcc, NoLock, Preserve) {
 242                         /* Byte offsets are computed using the following technique:
 243                          * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
 244                          * The 8 comes from 8 functions per device, and 4096 bytes per function config space
 245                         */
 246                         Offset(0x00088024),     /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
 247                         STB5, 32,
 248                         Offset(0x00098042),     /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
 249                         PT0D, 1,
 250                         PT1D, 1,
 251                         PT2D, 1,
 252                         PT3D, 1,
 253                         PT4D, 1,
 254                         PT5D, 1,
 255                         PT6D, 1,
 256                         PT7D, 1,
 257                         PT8D, 1,
 258                         PT9D, 1,
 259                         Offset(0x000A0004),     /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
 260                         SBIE, 1,
 261                         SBME, 1,
 262                         Offset(0x000A0008),     /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
 263                         SBRI, 8,
 264                         Offset(0x000A0014),     /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
 265                         SBB1, 32,
 266                         Offset(0x000A0078),     /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
 267                         ,14,
 268                         P92E, 1,                /* Port92 decode enable */
 269                 }
 270
 271                 OperationRegion(SB5, SystemMemory, STB5, 0x1000)
 272                         Field(SB5, AnyAcc, NoLock, Preserve){
 273                         /* Port 0 */
 274                         Offset(0x120),          /* Port 0 Task file status */
 275                         P0ER, 1,
 276                         , 2,
 277                         P0DQ, 1,
 278                         , 3,
 279                         P0BY, 1,
 280                         Offset(0x128),          /* Port 0 Serial ATA status */
 281                         P0DD, 4,
 282                         , 4,
 283                         P0IS, 4,
 284                         Offset(0x12C),          /* Port 0 Serial ATA control */
 285                         P0DI, 4,
 286                         Offset(0x130),          /* Port 0 Serial ATA error */
 287                         , 16,
 288                         P0PR, 1,
 289
 290                         /* Port 1 */
 291                         offset(0x1A0),          /* Port 1 Task file status */
 292                         P1ER, 1,
 293                         , 2,
 294                         P1DQ, 1,
 295                         , 3,
 296                         P1BY, 1,
 297                         Offset(0x1A8),          /* Port 1 Serial ATA status */
 298                         P1DD, 4,
 299                         , 4,
 300                         P1IS, 4,
 301                         Offset(0x1AC),          /* Port 1 Serial ATA control */
 302                         P1DI, 4,
 303                         Offset(0x1B0),          /* Port 1 Serial ATA error */
 304                         , 16,
 305                         P1PR, 1,
 306
 307                         /* Port 2 */
 308                         Offset(0x220),          /* Port 2 Task file status */
 309                         P2ER, 1,
 310                         , 2,
 311                         P2DQ, 1,
 312                         , 3,
 313                         P2BY, 1,
 314                         Offset(0x228),          /* Port 2 Serial ATA status */
 315                         P2DD, 4,
 316                         , 4,
 317                         P2IS, 4,
 318                         Offset(0x22C),          /* Port 2 Serial ATA control */
 319                         P2DI, 4,
 320                         Offset(0x230),          /* Port 2 Serial ATA error */
 321                         , 16,
 322                         P2PR, 1,
 323
 324                         /* Port 3 */
 325                         Offset(0x2A0),          /* Port 3 Task file status */
 326                         P3ER, 1,
 327                         , 2,
 328                         P3DQ, 1,
 329                         , 3,
 330                         P3BY, 1,
 331                         Offset(0x2A8),          /* Port 3 Serial ATA status */
 332                         P3DD, 4,
 333                         , 4,
 334                         P3IS, 4,
 335                         Offset(0x2AC),          /* Port 3 Serial ATA control */
 336                         P3DI, 4,
 337                         Offset(0x2B0),          /* Port 3 Serial ATA error */
 338                         , 16,
 339                         P3PR, 1,
 340                 }
 341         }
 342
 343
 344         #include "acpi/routing.asl"
 345
 346         Scope(\_SB) {
 347
 348                 /* Debug Port registers, 80h. */
 349                 OperationRegion(DBBG, SystemIO, 0x00000080, 0x00000001)
 350                         Field(DBBG, ByteAcc, NoLock, Preserve) {
 351                         DBG8, 0x00000008,
 352                 }
 353
 354                 Method(_PIC, 1) {
 355                         Store(Arg0, GPIC)
 356                         If (GPIC) {
 357                                 Store(0xAA, \_SB.DBG8)
 358                                 \_SB.DSPI()
 359                         } else {
 360                                 Store(0xAC, \_SB.DBG8)
 361                         }
 362                 }
 363
 364                 Method(DSPI, 0) {
 365                         \_SB.GRUA(0x1F)
 366                         \_SB.GRUB(0x1F)
 367                         \_SB.GRUC(0x1F)
 368                         \_SB.GRUD(0x1F)
 369                         Store(0x1F, PIRE)
 370                         Store(0x1F, PIRF)
 371                         Store(0x1F, PIRG)
 372                         Store(0x1F, PIRH)
 373                 }
 374
 375                 Method(GRUA, 1) {
 376                         Store(Arg0, PIRA)
 377                         Store(Arg0, HDAD)
 378                         Store(Arg0, GEC)
 379                         Store(Arg0, GPP0)
 380                         Store(Arg0, GPP0)
 381                 }
 382
 383                 Method(GRUB, 1) {
 384                         Store(Arg0, PIRB)
 385                         Store(Arg0, USB2)
 386                         Store(Arg0, USB4)
 387                         Store(Arg0, USB6)
 388                         Store(Arg0, GPP1)
 389                         Store(Arg0, IDE)
 390                 }
 391
 392                 Method(GRUC, 1) {
 393                         Store(Arg0, PIRC)
 394                         Store(Arg0, USB1)
 395                         Store(Arg0, USB3)
 396                         Store(Arg0, USB5)
 397                         Store(Arg0, USB7)
 398                         Store(Arg0, GPP2)
 399                 }
 400
 401                 Method(GRUD, 1) {
 402                         Store(Arg0, PIRD)
 403                         Store(Arg0, SATA)
 404                         Store(Arg0, GPP3)
 405                 }
 406
 407                 Name(IRQB, ResourceTemplate() {
 408                         IRQ(Level, ActiveLow, Shared) {
 409                                 15
 410                 }})
 411
 412                 Name(IRQP, ResourceTemplate() {
 413                         IRQ(Level, ActiveLow, Shared) {
 414                                 3, 4, 5, 7, 10, 11, 12, 14, 15
 415                 }})
 416
 417                 Device(INTA) {
 418                         Name(_HID, EISAID("PNP0C0F"))
 419                         Name(_UID, 1)
 420                         Method(_STA, 0) {
 421                                 if (PIRA) {
 422                                         Return(0x0B)
 423                                 } else {
 424                                         Return(0x09)
 425                                 }
 426                         }
 427                         Method(_DIS ,0) {
 428                                 \_SB.GRUA(0x1F)
 429                         }
 430                         Method(_PRS ,0) {
 431                                 Return(IRQP)
 432                         }
 433                         Method(_CRS ,0) {
 434                                 CreateWordField(IRQB, 1, IRQN)
 435                                 ShiftLeft(1, PIRA, IRQN)
 436                                 Return(IRQB)
 437                         }
 438                         Method(_SRS, 1) {
 439                                 CreateWordField(Arg0, 1, IRQM)
 440                                 FindSetRightBit(IRQM, Local0)
 441                                 Decrement(Local0)
 442                                 \_SB.GRUA(Local0)
 443                         }
 444                 }
 445
 446                 Device(INTB) {
 447                         Name(_HID, EISAID("PNP0C0F"))
 448                         Name(_UID, 2)
 449                         Method(_STA, 0) {
 450                                 if (PIRB) {
 451                                         Return(0x0B)
 452                                 } else {
 453                                         Return(0x09)
 454                                 }
 455                         }
 456                         Method(_DIS ,0) {
 457                                 \_SB.GRUB(0x1F)
 458                         }
 459                         Method(_PRS ,0) {
 460                                 Return(IRQP)
 461                         }
 462                         Method(_CRS ,0) {
 463                                 CreateWordField(IRQB, 1, IRQN)
 464                                 ShiftLeft(1, PIRB, IRQN)
 465                                 Return(IRQB)
 466                         }
 467                         Method(_SRS, 1) {
 468                                 CreateWordField(Arg0, 1, IRQM)
 469                                 FindSetRightBit(IRQM, Local0)
 470                                 Decrement(Local0)
 471                                 \_SB.GRUB(Local0)
 472                         }
 473                 }
 474
 475                 Device(INTC) {
 476                         Name(_HID, EISAID("PNP0C0F"))
 477                         Name(_UID, 3)
 478                         Method(_STA, 0) {
 479                                 if (PIRC) {
 480                                         Return(0x0B)
 481                                 } else {
 482                                         Return(0x09)
 483                                 }
 484                         }
 485                         Method(_DIS ,0) {
 486                                 \_SB.GRUC(0x1F)
 487                         }
 488                         Method(_PRS ,0) {
 489                                 Return(IRQP)
 490                         }
 491                         Method(_CRS ,0) {
 492                                 CreateWordField(IRQB, 1, IRQN)
 493                                 ShiftLeft(1, PIRC, IRQN)
 494                                 Return(IRQB)
 495                         }
 496                         Method(_SRS, 1) {
 497                                 CreateWordField(Arg0, 1, IRQM)
 498                                 FindSetRightBit(IRQM, Local0)
 499                                 Decrement(Local0)
 500                                 \_SB.GRUC(Local0)
 501                         }
 502                 }
 503
 504                 Device(INTD) {
 505                         Name(_HID, EISAID("PNP0C0F"))
 506                         Name(_UID, 4)
 507                         Method(_STA, 0) {
 508                                 if (PIRD) {
 509                                         Return(0x0B)
 510                                 } else {
 511                                         Return(0x09)
 512                                 }
 513                         }
 514                         Method(_DIS ,0) {
 515                                 \_SB.GRUD(0x1F)
 516                         }
 517                         Method(_PRS ,0) {
 518                                 Return(IRQP)
 519                         }
 520                         Method(_CRS ,0) {
 521                                 CreateWordField(IRQB, 1, IRQN)
 522                                 ShiftLeft(1, PIRD, IRQN)
 523                                 Return(IRQB)
 524                         }
 525                         Method(_SRS, 1) {
 526                                 CreateWordField(Arg0, 1, IRQM)
 527                                 FindSetRightBit(IRQM, Local0)
 528                                 Decrement(Local0)
 529                                 \_SB.GRUD(Local0)
 530                         }
 531                 }
 532
 533                 Device(INTE) {
 534                         Name(_HID, EISAID("PNP0C0F"))
 535                         Name(_UID, 5)
 536                         Method(_STA, 0) {
 537                                 if (PIRE) {
 538                                         Return(0x0B)
 539                                 } else {
 540                                         Return(0x09)
 541                                 }
 542                         }
 543                         Method(_DIS ,0) {
 544                                 Store(0x1F, PIRE)
 545                         }
 546                         Method(_PRS ,0) {
 547                                 Return(IRQP)
 548                         }
 549                         Method(_CRS ,0) {
 550                                 CreateWordField(IRQB, 1, IRQN)
 551                                 ShiftLeft(1, PIRE, IRQN)
 552                                 Return(IRQB)
 553                         }
 554                         Method(_SRS, 1) {
 555                                 CreateWordField(Arg0, 1, IRQM)
 556                                 FindSetRightBit(IRQM, Local0)
 557                                 Decrement(Local0)
 558                                 Store(Local0, PIRE)
 559                         }
 560                 }
 561
 562                 Device(INTF) {
 563                         Name(_HID, EISAID("PNP0C0F"))
 564                         Name(_UID, 6)
 565                         Method(_STA, 0) {
 566                                 if (PIRF) {
 567                                         Return(0x0B)
 568                                 } else {
 569                                         Return(0x09)
 570                                 }
 571                         }
 572                         Method(_DIS ,0) {
 573                                 Store(0x1F, PIRF)
 574                         }
 575                         Method(_PRS ,0) {
 576                                 Return(IRQP)
 577                         }
 578                         Method(_CRS ,0) {
 579                                 CreateWordField(IRQB, 1, IRQN)
 580                                 ShiftLeft(1, PIRF, IRQN)
 581                                 Return(IRQB)
 582                         }
 583                         Method(_SRS, 1) {
 584                                 CreateWordField(Arg0, 1, IRQM)
 585                                 FindSetRightBit(IRQM, Local0)
 586                                 Decrement(Local0)
 587                                 Store(Local0, PIRF)
 588                         }
 589                 }
 590
 591                 Device(INTG) {
 592                         Name(_HID, EISAID("PNP0C0F"))
 593                         Name(_UID, 7)
 594                         Method(_STA, 0) {
 595                                 if (PIRG) {
 596                                         Return(0x0B)
 597                                 } else {
 598                                         Return(0x09)
 599                                 }
 600                         }
 601                         Method(_DIS ,0) {
 602                                 Store(0x1F, PIRG)
 603                         }
 604                         Method(_PRS ,0) {
 605                                 Return(IRQP)
 606                         }
 607                         Method(_CRS ,0) {
 608                                 CreateWordField(IRQB, 1, IRQN)
 609                                 ShiftLeft(1, PIRG, IRQN)
 610                                 Return(IRQB)
 611                         }
 612                         Method(_SRS, 1) {
 613                                 CreateWordField(Arg0, 1, IRQM)
 614                                 FindSetRightBit(IRQM, Local0)
 615                                 Decrement(Local0)
 616                                 Store(Local0, PIRG)
 617                         }
 618                 }
 619
 620                 Device(INTH) {
 621                         Name(_HID, EISAID("PNP0C0F"))
 622                         Name(_UID, 8)
 623                         Method(_STA, 0) {
 624                                 if (PIRH) {
 625                                         Return(0x0B)
 626                                 } else {
 627                                         Return(0x09)
 628                                 }
 629                         }
 630                         Method(_DIS ,0) {
 631                                 Store(0x1F, PIRH)
 632                         }
 633                         Method(_PRS ,0) {
 634                                 Return(IRQP)
 635                         }
 636                         Method(_CRS ,0) {
 637                                 CreateWordField(IRQB, 1, IRQN)
 638                                 ShiftLeft(1, PIRH, IRQN)
 639                                 Return(IRQB)
 640                         }
 641                         Method(_SRS, 1) {
 642                                 CreateWordField(Arg0, 1, IRQM)
 643                                 FindSetRightBit(IRQM, Local0)
 644                                 Decrement(Local0)
 645                                 Store(Local0, PIRH)
 646                         }
 647                 }
 648         }   /* End Scope(_SB)  */
 649
 650
 651         /* Supported sleep states: */
 652         Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} )        /* (S0) - working state */
 653
 654         If (LAnd(SSFG, 0x01)) {
 655                 Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} )        /* (S1) - sleeping w/CPU context */
 656         }
 657         If (LAnd(SSFG, 0x02)) {
 658                 Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} )        /* (S2) - "light" Suspend to RAM */
 659         }
 660         If (LAnd(SSFG, 0x04)) {
 661                 Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} )        /* (S3) - Suspend to RAM */
 662         }
 663         If (LAnd(SSFG, 0x08)) {
 664                 Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} )        /* (S4) - Suspend to Disk */
 665         }
 666
 667         Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} )        /* (S5) - Soft Off */
 668
 669         Name(\_SB.CSPS ,0)                              /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
 670         Name(CSMS, 0)                   /* Current System State */
 671
 672         /* Wake status package */
 673         Name(WKST,Package(){Zero, Zero})
 674
 675         /*
 676         * \_PTS - Prepare to Sleep method
 677         *
 678         *       Entry:
 679         *               Arg0=The value of the sleeping state S1=1, S2=2, etc
 680         *
 681         * Exit:
 682         *               -none-
 683         *
 684         * The _PTS control method is executed at the beginning of the sleep process
 685         * for S1-S5. The sleeping value is passed to the _PTS control method.   This
 686         * control method may be executed a relatively long time before entering the
 687         * sleep state and the OS may abort      the operation without notification to
 688         * the ACPI driver.  This method cannot modify the configuration or power
 689         * state of any device in the system.
 690         */
 691         Method(\_PTS, 1) {
 692                 /* DBGO("\\_PTS\n") */
 693                 /* DBGO("From S0 to S") */
 694                 /* DBGO(Arg0) */
 695                 /* DBGO("\n") */
 696
 697                 /* Don't allow PCIRST# to reset USB */
 698                 if (LEqual(Arg0,3)){
 699                         Store(0,URRE)
 700                 }
 701
 702                 /* Clear sleep SMI status flag and enable sleep SMI trap. */
 703                 /*Store(One, CSSM)
 704                 Store(One, SSEN)*/
 705
 706                 /* On older chips, clear PciExpWakeDisEn */
 707                 /*if (LLessEqual(\_SB.SBRI, 0x13)) {
 708                 *       Store(0,\_SB.PWDE)
 709                 *}
 710                 */
 711
 712                 /* Clear wake status structure. */
 713                 Store(0, Index(WKST,0))
 714                 Store(0, Index(WKST,1))
 715         } /* End Method(\_PTS) */
 716
 717         /*
 718         *  The following method results in a "not a valid reserved NameSeg"
 719         *  warning so I have commented it out for the duration.  It isn't
 720         *  used, so it could be removed.
 721         *
 722         *
 723         *       \_GTS OEM Going To Sleep method
 724         *
 725         *       Entry:
 726         *               Arg0=The value of the sleeping state S1=1, S2=2
 727         *
 728         *       Exit:
 729         *               -none-
 730         *
 731         *  Method(\_GTS, 1) {
 732         *  DBGO("\\_GTS\n")
 733         *  DBGO("From S0 to S")
 734         *  DBGO(Arg0)
 735         *  DBGO("\n")
 736         *  }
 737         */
 738
 739         /*
 740         *       \_BFS OEM Back From Sleep method
 741         *
 742         *       Entry:
 743         *               Arg0=The value of the sleeping state S1=1, S2=2
 744         *
 745         *       Exit:
 746         *               -none-
 747         */
 748         Method(\_BFS, 1) {
 749                 /* DBGO("\\_BFS\n") */
 750                 /* DBGO("From S") */
 751                 /* DBGO(Arg0) */
 752                 /* DBGO(" to S0\n") */
 753         }
 754
 755         /*
 756         *  \_WAK System Wake method
 757         *
 758         *       Entry:
 759         *               Arg0=The value of the sleeping state S1=1, S2=2
 760         *
 761         *       Exit:
 762         *               Return package of 2 DWords
 763         *               Dword 1 - Status
 764         *                       0x00000000      wake succeeded
 765         *                       0x00000001      Wake was signaled but failed due to lack of power
 766         *                       0x00000002      Wake was signaled but failed due to thermal condition
 767         *               Dword 2 - Power Supply state
 768         *                       if non-zero the effective S-state the power supply entered
 769         */
 770         Method(\_WAK, 1) {
 771                 /* DBGO("\\_WAK\n") */
 772                 /* DBGO("From S") */
 773                 /* DBGO(Arg0) */
 774                 /* DBGO(" to S0\n") */
 775
 776                 /* Re-enable HPET */
 777                 Store(1,HPDE)
 778
 779                 /* Restore PCIRST# so it resets USB */
 780                 if (LEqual(Arg0,3)){
 781                         Store(1,URRE)
 782                 }
 783
 784                 /* Arbitrarily clear PciExpWakeStatus */
 785                 Store(PEWS, PEWS)
 786
 787                 /* if(DeRefOf(Index(WKST,0))) {
 788                 *       Store(0, Index(WKST,1))
 789                 * } else {
 790                 *       Store(Arg0, Index(WKST,1))
 791                 * }
 792                 */
 793                 Return(WKST)
 794         } /* End Method(\_WAK) */
 795
 796         Scope(\_GPE) {  /* Start Scope GPE */
 797         }       /* End Scope GPE */
 798
 799         /* South Bridge */
 800         Scope(\_SB) { /* Start \_SB scope */
 801                 #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */
 802
 803                 /*  _SB.PCI0 */
 804                 /* Note: Only need HID on Primary Bus */
 805                 Device(PCI0) {
 806                         External (TOM1)
 807                         External (TOM2)
 808                         Name(_HID, EISAID("PNP0A03"))
 809                         Name(_ADR, 0x00180000)  /* Dev# = BSP Dev#, Func# = 0 */
 810                         Method(_BBN, 0) { /* Bus number = 0 */
 811                                 Return(0)
 812                         }
 813                         Method(_STA, 0) {
 814                                 /* DBGO("\\_SB\\PCI0\\_STA\n") */
 815                                 Return(0x0B)     /* Status is visible */
 816                         }
 817                         Method(_PRT,0) {
 818                                 If(GPIC){ Return(APR0) }   /* APIC mode */
 819                                 Return (PR0)                  /* PIC Mode */
 820                         } /* end _PRT */
 821
 822                         /* Describe the Northbridge devices */
 823                         Device(AMRT) {
 824                                 Name(_ADR, 0x00000000)
 825                         } /* end AMRT */
 826
 827                         /* The internal GFX bridge */
 828                         Device(AGPB) {
 829                                 Name(_ADR, 0x00010000)
 830                                 Method(_STA,0) {
 831                                         Return(0x0F)
 832                                 }
 833                         }  /* end AGPB */
 834
 835                         /* The external GFX bridge */
 836                         Device(PBR2) {
 837                                 Name(_ADR, 0x00020000)
 838                                 Method(_PRT,0) {
 839                                         If(GPIC){ Return(APS2) }   /* APIC mode */
 840                                         Return (PS2)               /* PIC Mode */
 841                                 } /* end _PRT */
 842                         } /* end PBR2 */
 843
 844                         /* The external GFX bridge */
 845                         Device(PBR3) {
 846                                 Name(_ADR, 0x00030000)
 847                                 Method(_PRT,0) {
 848                                         If(GPIC){ Return(APS3) }   /* APIC mode */
 849                                         Return (PS3)               /* PIC Mode */
 850                                 } /* end _PRT */
 851                         } /* end PBR3 */
 852
 853                         Device(PBR4) {
 854                                 Name(_ADR, 0x00040000)
 855                                 Method(_PRT,0) {
 856                                         If(GPIC){ Return(APS4) }   /* APIC mode */
 857                                         Return (PS4)                  /* PIC Mode */
 858                                 } /* end _PRT */
 859                         } /* end PBR4 */
 860
 861                         Device(PBR5) {
 862                                 Name(_ADR, 0x00050000)
 863                                 Method(_PRT,0) {
 864                                         If(GPIC){ Return(APS5) }   /* APIC mode */
 865                                         Return (PS5)                  /* PIC Mode */
 866                                 } /* end _PRT */
 867                         } /* end PBR5 */
 868
 869                         Device(PBR6) {
 870                                 Name(_ADR, 0x00060000)
 871                                 Method(_PRT,0) {
 872                                         If(GPIC){ Return(APS6) }   /* APIC mode */
 873                                         Return (PS6)                  /* PIC Mode */
 874                                 } /* end _PRT */
 875                         } /* end PBR6 */
 876
 877                         /* The onboard EtherNet chip */
 878                         Device(PBR7) {
 879                                 Name(_ADR, 0x00070000)
 880                                 Method(_PRT,0) {
 881                                         If(GPIC){ Return(APS7) }   /* APIC mode */
 882                                         Return (PS7)                  /* PIC Mode */
 883                                 } /* end _PRT */
 884                         } /* end PBR7 */
 885
 886                         Device(PE20) {
 887                                 Name(_ADR, 0x00150000)
 888                                 Method(_PRT,0) {
 889                                         If(GPIC){ Return(APE0) }   /* APIC mode */
 890                                         Return (PE0)                  /* PIC Mode */
 891                                 } /* end _PRT */
 892                         } /* end PE20 */
 893                         Device(PE21) {
 894                                 Name(_ADR, 0x00150001)
 895                                 Method(_PRT,0) {
 896                                         If(GPIC){ Return(APE1) }   /* APIC mode */
 897                                         Return (PE1)                  /* PIC Mode */
 898                                 } /* end _PRT */
 899                         } /* end PE21 */
 900                         Device(PE22) {
 901                                 Name(_ADR, 0x00150002)
 902                                 Method(_PRT,0) {
 903                                         If(GPIC){ Return(APE2) }   /* APIC mode */
 904                                         Return (APE2)                  /* PIC Mode */
 905                                 } /* end _PRT */
 906                         } /* end PE22 */
 907                         Device(PE23) {
 908                                 Name(_ADR, 0x00150003)
 909                                 Method(_PRT,0) {
 910                                         If(GPIC){ Return(APE3) }   /* APIC mode */
 911                                         Return (PE3)                  /* PIC Mode */
 912                                 } /* end _PRT */
 913                         } /* end PE23 */
 914
 915                         /* Describe the Southbridge devices */
 916                         Device(AZHD) {
 917                                 Name(_ADR, 0x00140002)
 918                                 OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
 919                                         Field(AZPD, AnyAcc, NoLock, Preserve) {
 920                                         offset (0x42),
 921                                         NSDI, 1,
 922                                         NSDO, 1,
 923                                         NSEN, 1,
 924                                 }
 925                         } /* end AZHD */
 926
 927                         Device(GEC) {
 928                                 Name(_ADR, 0x00140006)
 929                         } /* end GEC */
 930
 931                         Device(UOH1) {
 932                                 Name(_ADR, 0x00120000)
 933                                 #include "acpi/usb.asl"
 934                         } /* end UOH1 */
 935
 936                         Device(UOH3) {
 937                                 Name(_ADR, 0x00130000)
 938                                 #include "acpi/usb.asl"
 939                         } /* end UOH3 */
 940
 941                         Device(UOH5) {
 942                                 Name(_ADR, 0x00160000)
 943                                 #include "acpi/usb.asl"
 944                         } /* end UOH5 */
 945
 946                         Device(UEH1) {
 947                                 Name(_ADR, 0x00140005)
 948                                 #include "acpi/usb.asl"
 949                         } /* end UEH1 */
 950
 951                         Device(UOH2) {
 952                                 Name(_ADR, 0x00120002)
 953                                 #include "acpi/usb.asl"
 954                         } /* end UOH2 */
 955
 956                         Device(UOH4) {
 957                                 Name(_ADR, 0x00130002)
 958                                 #include "acpi/usb.asl"
 959                         } /* end UOH4 */
 960
 961                         Device(UOH6) {
 962                                 Name(_ADR, 0x00160002)
 963                                 #include "acpi/usb.asl"
 964                         } /* end UOH5 */
 965
 966                         Device(XHC0) {
 967                                 Name(_ADR, 0x00100000)
 968                                 #include "acpi/usb.asl"
 969                         } /* end XHC0 */
 970
 971                         Device(XHC1) {
 972                                 Name(_ADR, 0x00100001)
 973                                 #include "acpi/usb.asl"
 974                         } /* end XHC1 */
 975
 976                         Device(SBUS) {
 977                                 Name(_ADR, 0x00140000)
 978                         } /* end SBUS */
 979
 980                         Device(LIBR) {
 981                                 Name(_ADR, 0x00140003)
 982                                 /* Real Time Clock Device */
 983                                 Device(RTC0) {
 984                                         Name(_HID, EISAID("PNP0B00"))   /* AT Real Time Clock (not PIIX4 compatible) */
 985                                         Name(_CRS, ResourceTemplate() {
 986                                                 IRQNoFlags(){8}
 987                                                 IO(Decode16,0x0070, 0x0070, 0, 2)
 988                                                 /* IO(Decode16,0x0070, 0x0070, 0, 4) */
 989                                         })
 990                                 } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
 991
 992                                 Device(TMR) {   /* Timer */
 993                                         Name(_HID,EISAID("PNP0100"))    /* System Timer */
 994                                         Name(_CRS, ResourceTemplate() {
 995                                                 IRQNoFlags(){0}
 996                                                 IO(Decode16, 0x0040, 0x0040, 0, 4)
 997                                                 /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
 998                                         })
 999                                 } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
1000
1001                                 Device(SPKR) {  /* Speaker */
1002                                         Name(_HID,EISAID("PNP0800"))    /* AT style speaker */
1003                                         Name(_CRS, ResourceTemplate() {
1004                                                 IO(Decode16, 0x0061, 0x0061, 0, 1)
1005                                         })
1006                                 } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
1007
1008                                 Device(PIC) {
1009                                         Name(_HID,EISAID("PNP0000"))    /* AT Interrupt Controller */
1010                                         Name(_CRS, ResourceTemplate() {
1011                                                 IRQNoFlags(){2}
1012                                                 IO(Decode16,0x0020, 0x0020, 0, 2)
1013                                                 IO(Decode16,0x00A0, 0x00A0, 0, 2)
1014                                                 /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
1015                                                 /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
1016                                         })
1017                                 } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
1018
1019                                 Device(MAD) { /* 8257 DMA */
1020                                         Name(_HID,EISAID("PNP0200"))    /* Hardware Device ID */
1021                                         Name(_CRS, ResourceTemplate() {
1022                                                 DMA(Compatibility,BusMaster,Transfer8){4}
1023                                                 IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
1024                                                 IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
1025                                                 IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
1026                                                 IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
1027                                                 IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
1028                                                 IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
1029                                         }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
1030                                 } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
1031
1032                                 Device(COPR) {
1033                                         Name(_HID,EISAID("PNP0C04"))    /* Math Coprocessor */
1034                                         Name(_CRS, ResourceTemplate() {
1035                                                 IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
1036                                                 IRQNoFlags(){13}
1037                                         })
1038                                 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1039 #if 0
1040                                 Device(HPTM) {
1041                                         Name(_HID,EISAID("PNP0103"))
1042                                         Name(CRS,ResourceTemplate()     {
1043                                                 Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT)     /* 1kb reserved space */
1044                                         })
1045                                         Method(_STA, 0) {
1046                                                 Return(0x0F) /* sata is visible */
1047                                         }
1048                                         Method(_CRS, 0) {
1049                                                 CreateDwordField(CRS, ^HPT._BAS, HPBA)
1050                                                 Store(HPBA, HPBA)
1051                                                 Return(CRS)
1052                                         }
1053                                 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1054 #endif
1055                                 Device (PS2M) {
1056                                         Name (_HID, EisaId ("PNP0F13"))
1057                                         Name (_CRS, ResourceTemplate () {
1058                                                 IRQNoFlags () {12}
1059                                         })
1060                                         Method (_STA, 0, NotSerialized) {
1061                                                 And (FLG0, 0x04, Local0)
1062                                                 If (LEqual (Local0, 0x04)) {
1063                                                         Return (0x0F)
1064                                                 } Else {
1065                                                         Return (0x00)
1066                                                 }
1067                                         }
1068                                 }
1069
1070                                 Device (PS2K) {
1071                                         Name (_HID, EisaId ("PNP0303"))
1072                                         Name (_CRS, ResourceTemplate () {
1073                                                 IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
1074                                                 IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
1075                                                 IRQNoFlags () {1}
1076                                         })
1077                                 }
1078                         } /* end LIBR */
1079
1080                         Device(STCR) {
1081                                 Name(_ADR, 0x00110000)
1082                                 #include "acpi/sata.asl"
1083                         } /* end STCR */
1084
1085                         /* Primary (and only) IDE channel */
1086                         Device(IDEC) {
1087                                 Name(_ADR, 0x00140001)
1088                                 #include "acpi/ide.asl"
1089                         } /* end IDEC */
1090
1091                         Name(CRES, ResourceTemplate() {
1092                                 IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
1093
1094                                 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1095                                         0x0000,                 /* address granularity */
1096                                         0x0000,                 /* range minimum */
1097                                         0x0CF7,                 /* range maximum */
1098                                         0x0000,                 /* translation */
1099                                         0x0CF8                  /* length */
1100                                 )
1101
1102                                 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1103                                         0x0000,                 /* address granularity */
1104                                         0x0D00,                 /* range minimum */
1105                                         0xFFFF,                 /* range maximum */
1106                                         0x0000,                 /* translation */
1107                                         0xF300                  /* length */
1108                                 )
1109
1110                                 /* memory space for PCI BARs below 4GB */
1111                                 Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
1112                         }) /* End Name(_SB.PCI0.CRES) */
1113
1114                         Method(_CRS, 0) {
1115                                 /* DBGO("\\_SB\\PCI0\\_CRS\n") */
1116                                 CreateDWordField(CRES, ^MMIO._BAS, MM1B)
1117                 CreateDWordField(CRES, ^MMIO._LEN, MM1L)
1118                                 /*
1119                                 * Declare memory between TOM1 and 4GB as available
1120                                 * for PCI MMIO.
1121                                 * Use ShiftLeft to avoid 64bit constant (for XP).
1122                                 * This will work even if the OS does 32bit arithmetic, as
1123                                 * 32bit (0x00000000 - TOM1) will wrap and give the same
1124                                 * result as 64bit (0x100000000 - TOM1).
1125                                 */
1126                                 Store(TOM1, MM1B)
1127                                 ShiftLeft(0x10000000, 4, Local0)
1128                                 Subtract(Local0, TOM1, Local0)
1129                                 Store(Local0, MM1L)
1130
1131                                 Return(CRES) /* note to change the Name buffer */
1132                         } /* end of Method(_SB.PCI0._CRS) */
1133                 } /* End Device(PCI0)  */
1134
1135                 Device(PWRB) {  /* Start Power button device */
1136                         Name(_HID, EISAID("PNP0C0C"))
1137                         Name(_UID, 0xAA)
1138                         Name(_STA, 0x0B) /* sata is invisible */
1139                 }
1140         } /* End \_SB scope */
1141 }
1142 /* End of ASL file */