2 * This file is part of the coreboot project.
4 * Copyright (C) 2005-2007 Advanced Micro Devices, Inc.
5 * Copyright (C) 2008 Carl-Daniel Hailfinger
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <cpu/x86/mtrr.h>
22 #include <cpu/amd/mtrr.h>
24 #define CacheSize CONFIG_DCACHE_RAM_SIZE
25 #define CacheBase (0xd0000 - CacheSize)
27 /* Leave some space for global variable to pass to RAM stage. */
28 #define GlobalVarSize CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
30 /* For CAR with Fam10h. */
31 #define CacheSizeAPStack 0x400 /* 1K */
33 #define MSR_MCFG_BASE 0xC0010058
34 #define MSR_FAM10 0xC001102A
36 #define jmp_if_k8(x) comisd %xmm2, %xmm1; jb x
38 #define CPUID_MASK 0x0ff00f00
39 #define CPUID_VAL_FAM10_ROTATED 0x0f000010
44 * xmm2: Fam10h comparison value
48 /* Save the BIST result. */
52 * For normal part %ebx already contain cpu_init_detected
64 /* Figure out the CPU family. */
68 /* Base family is bits 8..11, extended family is bits 20..27. */
69 andl $CPUID_MASK, %eax
70 /* Reorder bits for easier comparison by value. */
73 movl $CPUID_VAL_FAM10_ROTATED, %eax
77 /* Check if cpu_init_detected. */
78 movl $MTRRdefType_MSR, %ecx
80 andl $MTRRdefTypeEn, %eax
81 movl %eax, %ebx /* We store the status. */
83 jmp_if_k8(CAR_FAM10_out_post_errata)
86 * For GH, CAR need to set DRAM Base/Limit registers to direct that
88 * Only BSP needed, for other nodes set during HT/memory init.
89 * So we need to check if it is BSP.
96 /* Enable RT tables on BSP. */
97 movl $0x8000c06c, %eax
105 /* Setup temporary DRAM map: [0,16M) bit 0-23. */
106 movl $0x8000c144, %eax
113 movl $0x8000c140, %eax
123 * Errata 193: Disable clean copybacks to L3 cache to allow cached ROM.
124 * Re-enable it in after RAM is initialized and before CAR is disabled.
126 movl $MSR_FAM10, %ecx
131 /* Erratum 343, RevGuide for Fam10h, Pub#41322 Rev. 3.33 */
132 movl $MSR_FAM10, %ecx
134 bts $35-32, %edx /* Set bit 35 in EDX:EAX (bit 3 in EDX). */
137 #if CONFIG_MMCONF_SUPPORT
138 #if (CONFIG_MMCONF_BASE_ADDRESS > 0xFFFFFFFF)
139 #error "MMCONF_BASE_ADDRESS too big"
140 #elif (CONFIG_MMCONF_BASE_ADDRESS & 0xFFFFF)
141 #error "MMCONF_BASE_ADDRESS not 1MB aligned"
144 movl $((CONFIG_MMCONF_BASE_ADDRESS) | (1 << 0)), %eax
145 #if (CONFIG_MMCONF_BUS_NUMBER == 1)
146 #elif (CONFIG_MMCONF_BUS_NUMBER == 2)
148 #elif (CONFIG_MMCONF_BUS_NUMBER == 4)
150 #elif (CONFIG_MMCONF_BUS_NUMBER == 8)
152 #elif (CONFIG_MMCONF_BUS_NUMBER == 16)
154 #elif (CONFIG_MMCONF_BUS_NUMBER == 32)
156 #elif (CONFIG_MMCONF_BUS_NUMBER == 64)
158 #elif (CONFIG_MMCONF_BUS_NUMBER == 128)
160 #elif (CONFIG_MMCONF_BUS_NUMBER == 256)
163 #error "bad MMCONF_BUS_NUMBER value"
165 movl $(0xc0010058), %ecx
169 CAR_FAM10_out_post_errata:
171 /* Set MtrrFixDramModEn for clear fixed MTRR. */
172 enable_fixed_mtrr_dram_modify:
173 movl $SYSCFG_MSR, %ecx
175 andl $(~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrVarDramEn)), %eax
176 orl $SYSCFG_MSR_MtrrFixDramModEn, %eax
179 /* Clear all MTRRs. */
181 movl $all_mtrr_msrs, %esi
183 clear_fixed_var_mtrr:
186 jz clear_fixed_var_mtrr_out
192 jmp clear_fixed_var_mtrr
193 clear_fixed_var_mtrr_out:
196 * 0x06 is the WB IO type for a given 4k segment.
197 * 0x1e is the MEM IO type for a given 4k segment (K10 and above).
198 * segs is the number of 4k segments in the area of the particular
199 * register we want to use for CAR.
200 * reg is the register where the IO type should be stored.
202 .macro extractmask segs, reg
205 * The xorl here is superfluous because at the point of first execution
206 * of this macro, %eax and %edx are cleared. Later invocations of this
207 * macro will have a monotonically increasing segs parameter.
214 movl $0x1e000000, \reg /* WB MEM type */
216 movl $0x1e1e0000, \reg /* WB MEM type */
218 movl $0x1e1e1e00, \reg /* WB MEM type */
220 movl $0x1e1e1e1e, \reg /* WB MEM type */
225 movl $0x06000000, \reg /* WB IO type */
227 movl $0x06060000, \reg /* WB IO type */
229 movl $0x06060600, \reg /* WB IO type */
231 movl $0x06060606, \reg /* WB IO type */
234 .endif /* if \segs <= 0 */
238 * carsize is the cache size in bytes we want to use for CAR.
239 * windowoffset is the 32k-aligned window into CAR size.
241 .macro simplemask carsize, windowoffset
242 .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4)
243 extractmask gas_bug_workaround, %eax
244 .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000))
245 extractmask gas_bug_workaround, %edx
247 * Without the gas bug workaround, the entire macro would consist
248 * only of the two lines below:
249 * extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax
250 * extractmask (((\carsize - \windowoffset) / 0x1000)), %edx
254 #if CacheSize > 0x10000
255 #error Invalid CAR size, must be at most 64k.
257 #if CacheSize < 0x1000
258 #error Invalid CAR size, must be at least 4k. This is a processor limitation.
260 #if (CacheSize & (0x1000 - 1))
261 #error Invalid CAR size, is not a multiple of 4k. This is a processor limitation.
264 #if CacheSize > 0x8000
265 /* Enable caching for 32K-64K using fixed MTRR. */
266 movl $MTRRfix4K_C0000_MSR, %ecx
267 simplemask CacheSize, 0x8000
271 /* Enable caching for 0-32K using fixed MTRR. */
272 movl $MTRRfix4K_C8000_MSR, %ecx
273 simplemask CacheSize, 0
276 /* Enable memory access for first MBs using top_mem. */
279 movl $(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
282 #if CONFIG_XIP_ROM_SIZE
284 /* Enable write base caching so we can do execute in place (XIP)
287 movl $MTRRphysBase_MSR(1), %ecx
290 * IMPORTANT: The following calculation _must_ be done at runtime. See
291 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
293 movl $copy_and_run, %eax
294 andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
295 orl $MTRR_TYPE_WRBACK, %eax
298 movl $MTRRphysMask_MSR(1), %ecx
299 movl $0xff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for K8 (CONFIG_CPU_ADDR_BITS = 40) */
300 jmp_if_k8(wbcache_post_fam10_setup)
301 movl $0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */
302 wbcache_post_fam10_setup:
303 movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
305 #endif /* CONFIG_XIP_ROM_SIZE */
307 /* Set the default memory type and enable fixed and variable MTRRs. */
308 movl $MTRRdefType_MSR, %ecx
310 movl $(MTRRdefTypeEn | MTRRdefTypeFixEn), %eax
313 /* Enable the MTRRs and IORRs in SYSCFG. */
314 movl $SYSCFG_MSR, %ecx
316 orl $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax
323 andl $(~((1 << 30) | (1 << 29))), %eax
326 jmp_if_k8(fam10_end_part1)
328 /* So we need to check if it is BSP. */
331 bt $8, %eax /* BSP */
337 /* Read the range with lodsl. */
339 movl $CacheBase, %esi
340 movl $(CacheSize >> 2), %ecx
343 /* Clear the range. */
344 movl $CacheBase, %edi
345 movl $(CacheSize >> 2), %ecx
349 /* Set up the stack pointer. */
350 movl $(CacheBase + CacheSize - GlobalVarSize), %eax
358 * Need to set stack pointer for AP.
360 * CacheBase + (CacheSize - GlobalVarSize) / 2
361 * - (NodeID << CoreIDbits + CoreID) * CacheSizeAPStack
362 * So need to get the NodeID and CoreID at first.
363 * If NB_CFG bit 54 is set just use initial APIC ID, otherwise need
367 /* Store our init detected. */
370 /* Get the coreid bits at first. */
371 movl $0x80000008, %eax
377 /* Get the initial APIC ID. */
382 /* Get the nb cfg bit 54. */
383 movl $0xc001001f, %ecx /* NB_CFG_MSR */
385 movl %edi, %ecx /* CoreID bits */
391 /* Calculate stack pointer. */
392 movl $CacheSizeAPStack, %eax
394 movl $(CacheBase + (CacheSize - GlobalVarSize) / 2), %esp
397 /* Retrive init detected. */
408 andl $~(3 << 9), %eax
411 /* Restore the BIST result. */
414 /* We need to set EBP? No need. */
416 pushl %ebx /* Init detected. */
417 pushl %eax /* BIST */
418 call cache_as_ram_main
419 /* We will not go back. */
421 post_code(0xaf) /* Should never see this POST code. */
424 /* fixed MTRR MSRs */
425 .long MTRRfix64K_00000_MSR
426 .long MTRRfix16K_80000_MSR
427 .long MTRRfix16K_A0000_MSR
428 .long MTRRfix4K_C0000_MSR
429 .long MTRRfix4K_C8000_MSR
430 .long MTRRfix4K_D0000_MSR
431 .long MTRRfix4K_D8000_MSR
432 .long MTRRfix4K_E0000_MSR
433 .long MTRRfix4K_E8000_MSR
434 .long MTRRfix4K_F0000_MSR
435 .long MTRRfix4K_F8000_MSR
438 .long MTRRphysBase_MSR(0)
439 .long MTRRphysMask_MSR(0)
440 .long MTRRphysBase_MSR(1)
441 .long MTRRphysMask_MSR(1)
442 .long MTRRphysBase_MSR(2)
443 .long MTRRphysMask_MSR(2)
444 .long MTRRphysBase_MSR(3)
445 .long MTRRphysMask_MSR(3)
446 .long MTRRphysBase_MSR(4)
447 .long MTRRphysMask_MSR(4)
448 .long MTRRphysBase_MSR(5)
449 .long MTRRphysMask_MSR(5)
450 .long MTRRphysBase_MSR(6)
451 .long MTRRphysMask_MSR(6)
452 .long MTRRphysBase_MSR(7)
453 .long MTRRphysMask_MSR(7)
455 /* Variable IORR MTRR MSRs */
456 .long IORRBase_MSR(0)
457 .long IORRMask_MSR(0)
458 .long IORRBase_MSR(1)
459 .long IORRMask_MSR(1)
461 /* Top of memory MTRR MSRs */
465 .long 0x000 /* NULL, end of table */
467 cache_as_ram_setup_out: