2 * This file is part of the coreboot project.
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
24 #include "routing.asl"
28 /* Routing is in System Bus scope */
32 /* Bus 0, Dev 0 - RS780 Host Controller */
33 /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
34 /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
36 Package(){0x0002FFFF, 0, INTC, 0 },
37 Package(){0x0002FFFF, 1, INTD, 0 },
38 Package(){0x0002FFFF, 2, INTA, 0 },
39 Package(){0x0002FFFF, 3, INTB, 0 },
41 /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
44 /* Bus 0, Dev 17 - SATA controller #2 */
45 /* Bus 0, Dev 18 - SATA controller #1 */
46 Package(){0x0011FFFF, 0, INTA, 0 },
48 /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
49 * EHCI, dev 18, 19 func 2 */
50 Package(){0x0012FFFF, 0, INTA, 0 },
51 Package(){0x0012FFFF, 1, INTB, 0 },
52 Package(){0x0012FFFF, 2, INTC, 0 },
53 Package(){0x0012FFFF, 3, INTD, 0 },
55 Package(){0x0013FFFF, 0, INTC, 0 },
56 Package(){0x0013FFFF, 1, INTD, 0 },
57 Package(){0x0013FFFF, 2, INTA, 0 },
58 Package(){0x0013FFFF, 3, INTB, 0 },
60 /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
61 Package(){0x0014FFFF, 0, INTA, 0 },
62 Package(){0x0014FFFF, 1, INTB, 0 },
63 Package(){0x0014FFFF, 2, INTC, 0 },
64 Package(){0x0014FFFF, 3, INTD, 0 },
68 /* NB devices in APIC mode */
69 /* Bus 0, Dev 0 - RS780 Host Controller */
71 /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */
72 /* Package(){0x0001FFFF, 0, 0, 18 }, */
73 /* package(){0x0001FFFF, 1, 0, 19 }, */
75 /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
76 Package(){0x0002FFFF, 0, 0, 18 },
77 Package(){0x0002FFFF, 1, 0, 19 },
78 Package(){0x0002FFFF, 2, 0, 16 },
79 Package(){0x0002FFFF, 3, 0, 17 },
81 /* Bus 0, Dev 9 - PCIe x1 slot */
82 Package(){0x0009FFFF, 0, 0, 17 },
83 Package(){0x0009FFFF, 1, 0, 18 },
84 Package(){0x0009FFFF, 2, 0, 19 },
85 Package(){0x0009FFFF, 3, 0, 10 },
87 /* Bus 0, Dev A - PCIe internal ethernet */
88 Package(){0x000AFFFF, 0, 0, 18 },
89 Package(){0x000AFFFF, 1, 0, 19 },
90 Package(){0x000AFFFF, 2, 0, 16 },
91 Package(){0x000AFFFF, 3, 0, 17 },
92 /* Bus 0, Funct 8 - Southbridge port (normally hidden) */
94 /* SB devices in APIC mode */
95 /* Bus 0, Dev 17 - SATA controller #2 */
96 /* Bus 0, Dev 18 - SATA controller #1 */
97 Package(){0x0011FFFF, 0, 0, 22 },
99 /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5;
100 * EHCI, dev 18, 19 func 2 */
101 Package(){0x0012FFFF, 0, 0, 16 },
102 Package(){0x0012FFFF, 1, 0, 17 },
103 Package(){0x0012FFFF, 2, 0, 18 },
104 Package(){0x0012FFFF, 3, 0, 19 },
106 Package(){0x0013FFFF, 0, 0, 18 },
107 Package(){0x0013FFFF, 1, 0, 19 },
108 Package(){0x0013FFFF, 2, 0, 16 },
109 Package(){0x0013FFFF, 3, 0, 17 },
111 /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
112 Package(){0x0014FFFF, 0, 0, 16 },
113 Package(){0x0014FFFF, 1, 0, 17 },
114 Package(){0x0014FFFF, 2, 0, 18 },
115 Package(){0x0014FFFF, 3, 0, 19 },
119 /* Internal graphics - RS780 VGA, Bus1, Dev5 */
120 Package(){0x0005FFFF, 0, INTC, 0 },
121 Package(){0x0005FFFF, 1, INTD, 0 },
122 Package(){0x0005FFFF, 2, INTA, 0 },
123 Package(){0x0005FFFF, 3, INTB, 0 },
126 Name(APR1, Package(){
127 /* Internal graphics - RS780 VGA, Bus1, Dev5 */
128 Package(){0x0005FFFF, 0, 0, 18 },
129 Package(){0x0005FFFF, 1, 0, 19 },
130 Package(){0x0005FFFF, 2, 0, 16 },
131 Package(){0x0005FFFF, 3, 0, 11 },
135 /* The external GFX - Hooked to PCIe slot 2 */
136 Package(){0x0000FFFF, 0, INTC, 0 },
137 Package(){0x0000FFFF, 1, INTD, 0 },
138 Package(){0x0000FFFF, 2, INTA, 0 },
139 Package(){0x0000FFFF, 3, INTB, 0 },
142 Name(APS2, Package(){
143 /* The external GFX - Hooked to PCIe slot 2 */
144 Package(){0x0000FFFF, 0, 0, 18 },
145 Package(){0x0000FFFF, 1, 0, 19 },
146 Package(){0x0000FFFF, 2, 0, 16 },
147 Package(){0x0000FFFF, 3, 0, 17 },
151 /* PCIe slot - Hooked to PCIe x1 */
152 Package(){0x0000FFFF, 0, INTD, 0 },
153 Package(){0x0000FFFF, 1, INTA, 0 },
154 Package(){0x0000FFFF, 2, INTB, 0 },
155 Package(){0x0000FFFF, 3, INTC, 0 },
158 Name(APS9, Package(){
159 /* PCIe slot - Hooked to PCIe x1 */
160 Package(){0x0000FFFF, 0, 0, 17 },
161 Package(){0x0000FFFF, 1, 0, 18 },
162 Package(){0x0000FFFF, 2, 0, 19 },
163 Package(){0x0000FFFF, 3, 0, 16 },
166 /* PCIe slot - Hooked to ethernet */
167 Package(){0x0000FFFF, 0, INTD, 0 },
168 Package(){0x0000FFFF, 1, INTA, 0 },
169 Package(){0x0000FFFF, 2, INTB, 0 },
170 Package(){0x0000FFFF, 3, INTC, 0 },
173 Name(APSa, Package(){
174 /* PCIe slot - Hooked to PCIe slot 10 */
175 Package(){0x0000FFFF, 0, 0, 18 },
176 Package(){0x0000FFFF, 1, 0, 19 },
177 Package(){0x0000FFFF, 2, 0, 16 },
178 Package(){0x0000FFFF, 3, 0, 17 },
181 Name(PCIB, Package(){
182 /* PCI slots: slot 0, slot 1, behind Dev14, Fun4. */
183 Package(){0x0005FFFF, 0, 0, 0x14 },
184 Package(){0x0005FFFF, 1, 0, 0x15 },
185 Package(){0x0005FFFF, 2, 0, 0x16 },
186 Package(){0x0005FFFF, 3, 0, 0x17 },
187 Package(){0x0006FFFF, 0, 0, 0x15 },
188 Package(){0x0006FFFF, 1, 0, 0x16 },
189 Package(){0x0006FFFF, 2, 0, 0x17 },
190 Package(){0x0006FFFF, 3, 0, 0x14 },