1 /* For starting coreboot in protected mode */
3 #include <arch/rom_segs.h>
4 #include <cpu/x86/post_code.h>
9 /* This is the GDT for the ROM stage part of coreboot. It
10 * is different from the RAM stage GDT which is defined in
18 .word gdt_end - gdt -1 /* compute the table limit */
19 .long gdt /* we know the offset */
22 /* selgdt 0x08, flat code segment */
24 .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */
26 /* selgdt 0x10,flat data segment */
28 .byte 0x00, 0x93, 0xcf, 0x00
34 * When we come here we are in protected mode. We expand
35 * the stack and copies the data segment from ROM to the
38 * After that, we call the chipset bootstrap routine that
39 * does what is left of the chipset initialization.
41 * NOTE aligned to 4 so that we are sure that the prefetch
42 * cache will be reloaded.
45 .globl protected_start
49 ljmp $ROM_CODE_SEG, $__protected_start
52 /* Save the BIST value */
55 post_code(POST_ENTER_PROTECTED_MODE)
57 movw $ROM_DATA_SEG, %ax
64 /* Restore the BIST value to %eax */