Myles Watson [Mon, 13 Sep 2010 14:49:02 +0000 (14:49 +0000)]
Port k8 UMA handling to fam10.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5807
2b7e53f0-3cfb-0310-b3e9-
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Juhana Helovuo [Mon, 13 Sep 2010 14:47:22 +0000 (14:47 +0000)]
Generate multiboot tables from coreboot tables.
Signed-off-by: Juhana Helovuo <juhe@iki.fi>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5806
2b7e53f0-3cfb-0310-b3e9-
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Juhana Helovuo [Mon, 13 Sep 2010 14:43:02 +0000 (14:43 +0000)]
Print an error and correct pci scan limits. Skip sb700 ISA DMA init if needed.
Signed-off-by: Juhana Helovuo <juhe@iki.fi>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5805
2b7e53f0-3cfb-0310-b3e9-
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Myles Watson [Mon, 13 Sep 2010 13:23:20 +0000 (13:23 +0000)]
Fix a typo reported by Sylvain Hitier.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5804
2b7e53f0-3cfb-0310-b3e9-
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Myles Watson [Mon, 13 Sep 2010 13:14:48 +0000 (13:14 +0000)]
Convert i945 boards to use reserved resources instead of directly adding
coreboot table entries in every mainboard.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5803
2b7e53f0-3cfb-0310-b3e9-
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Marc Jones [Fri, 10 Sep 2010 22:13:34 +0000 (22:13 +0000)]
Add F71859 SIO.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5802
2b7e53f0-3cfb-0310-b3e9-
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Jens Rottmann [Fri, 10 Sep 2010 21:51:34 +0000 (21:51 +0000)]
Add support for LiPPERT Hurricane-LX (EPIC board with AMD Geode-LX,
CS5536, ITE IT8712F). Board support is based on the SpaceRunner-LX
(with tiny bits from the RoadRunner-LX) even though the hardware really
was the ancestor of our three other -LX boards and in fact among the
earliest Geode-LX boards on the market. (Might even have been the first
Geode-LX EPIC?)
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5801
2b7e53f0-3cfb-0310-b3e9-
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Myles Watson [Fri, 10 Sep 2010 18:33:24 +0000 (18:33 +0000)]
Move memory type information out of some AMD sockets.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5800
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Thu, 9 Sep 2010 22:12:40 +0000 (22:12 +0000)]
Adapt comment, too. (trivial)
Noticed-by: Uwe Hermann
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5799
2b7e53f0-3cfb-0310-b3e9-
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Scott Duplichan [Thu, 9 Sep 2010 20:37:00 +0000 (20:37 +0000)]
This patch avoids a timeout during PS/2 keyboard
initialization. It can reduce KBC init time by up to 400 ms on
real hardware, and by a minute or so on AMD simnow.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5798
2b7e53f0-3cfb-0310-b3e9-
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Myles Watson [Thu, 9 Sep 2010 16:00:20 +0000 (16:00 +0000)]
Make huge macros inline functions for readability. Remove warnings. Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5797
2b7e53f0-3cfb-0310-b3e9-
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Arne Georg Gleditsch [Thu, 9 Sep 2010 14:54:07 +0000 (14:54 +0000)]
Please find appended. This patch gets rid of the %gs magic altogether,
fixes a few alignment wrinkles and sets up and registers the MMCONF area
for AMD Fam10h CPUs (where selected by mainboard configuration). It
removes a bit of code that proved troublesome in MMCONF setups from
mcp55_early_setup_car.c, as per earlier discussion.
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5796
2b7e53f0-3cfb-0310-b3e9-
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Myles Watson [Thu, 9 Sep 2010 14:51:17 +0000 (14:51 +0000)]
Add support for reserved regions to resources and coreboot tables.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5795
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Thu, 9 Sep 2010 14:44:51 +0000 (14:44 +0000)]
Only try to beep when speaker support is compiled in.
Trivial change.
Reported-by: Aurelien Guillaume <aurelien@iwi.me>
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5794
2b7e53f0-3cfb-0310-b3e9-
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Myles Watson [Thu, 9 Sep 2010 14:42:58 +0000 (14:42 +0000)]
My Jmicron SATA card writes the name of the hard drive to the screen.
This redirects that output to the console and implements a basic
keyboard stub.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5793
2b7e53f0-3cfb-0310-b3e9-
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Arne Georg Gleditsch [Thu, 9 Sep 2010 10:35:52 +0000 (10:35 +0000)]
Also improve boot time on AMD for the DDR3 code path.
Fix a typo, too.
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numscale.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5792
2b7e53f0-3cfb-0310-b3e9-
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Arne Georg Gleditsch [Thu, 9 Sep 2010 09:56:19 +0000 (09:56 +0000)]
Apparently, it's not crucial to clear this at the exact moment we switch
to using ram, so something like the appended is perhaps more
appropriate. Confirmed to work on hw.
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numscale.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5791
2b7e53f0-3cfb-0310-b3e9-
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Kevin O'Connor [Thu, 9 Sep 2010 08:34:02 +0000 (08:34 +0000)]
Add a DRIVERS_PS2_KEYBOARD option which controls the PS2 keyboard
initialization. Not all payloads require it and some keyboards take a
long time to init.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5790
2b7e53f0-3cfb-0310-b3e9-
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Marc Jones [Wed, 8 Sep 2010 21:30:07 +0000 (21:30 +0000)]
Trivial - remove stray characters from a comment block.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5789
2b7e53f0-3cfb-0310-b3e9-
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Kevin O'Connor [Wed, 8 Sep 2010 11:00:25 +0000 (11:00 +0000)]
Code must not access the smbus registers before the RTC power well is
ready (PSON gating). Some boards boot faster than this power well
stabilization, and thus see bad data when accessing the smbus
registers.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5788
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Wed, 8 Sep 2010 10:58:02 +0000 (10:58 +0000)]
Make timer2 the default choice for TSC initialization.
For boards where timer2 is unusable, there's still the IO based
initialization available using the Kconfig option TSC_CALIBRATE_WITH_IO
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Kevin O'Connor <kevin@koconnor.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5787
2b7e53f0-3cfb-0310-b3e9-
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Kevin O'Connor [Wed, 8 Sep 2010 10:53:44 +0000 (10:53 +0000)]
It should not be necessary to read in the rom during CAR setup.
Removing the code preloading reduces the boot time.
Preload code is enabled when doing CARTEST (not exposed
to Kconfig given that it's a pure debugging measure)
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5786
2b7e53f0-3cfb-0310-b3e9-
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Liu Tao [Wed, 8 Sep 2010 10:27:13 +0000 (10:27 +0000)]
Changes to str*cmp functions. Fixes a couple more corner cases.
Signed-off-by: Liu Tao <liutao1980@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5785
2b7e53f0-3cfb-0310-b3e9-
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Myles Watson [Tue, 7 Sep 2010 23:27:59 +0000 (23:27 +0000)]
My Jmicron SATA card depends on the BIOS not clearing AL when setting AH.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5784
2b7e53f0-3cfb-0310-b3e9-
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Myles Watson [Tue, 7 Sep 2010 22:30:15 +0000 (22:30 +0000)]
Make a Kconfig option for debugging output from realmode emulation. Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5783
2b7e53f0-3cfb-0310-b3e9-
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Jens Rottmann [Tue, 7 Sep 2010 17:33:17 +0000 (17:33 +0000)]
Add support for LiPPERT Cool LiteRunner-LX (PC/104 board with AMD
Geode-LX, CS5536, ITE IT8712F), based on very similar SpaceRunner-LX.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5782
2b7e53f0-3cfb-0310-b3e9-
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Rudolf Marek [Tue, 7 Sep 2010 09:18:08 +0000 (09:18 +0000)]
Remove unused ide0_enable and sata0_enable entries from SB7xx
and SB600.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5781
2b7e53f0-3cfb-0310-b3e9-
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Kevin O'Connor [Tue, 7 Sep 2010 07:53:26 +0000 (07:53 +0000)]
2ms is enough time to accurately obtain the clock rate.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5780
2b7e53f0-3cfb-0310-b3e9-
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Aurelien Guillaume [Tue, 7 Sep 2010 07:43:10 +0000 (07:43 +0000)]
Set up an arbitrary amount of system memory on Geode LX, so
coreboot_ram can be unpacked to 1MB. The value is quickly
replaced with the real value later, thus causing no harm.
Move RAMBASE to the default of 1MB for the affected boards
Signed-off-by: Aurelien Guillaume <aurelien@iwi.me>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5779
2b7e53f0-3cfb-0310-b3e9-
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Kevin O'Connor [Mon, 6 Sep 2010 20:20:47 +0000 (20:20 +0000)]
Instead of requiring users to modify qemu to allow writes to
0xc0000-0xfffff, have coreboot qemu support enable the memory range at
startup.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5778
2b7e53f0-3cfb-0310-b3e9-
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Zheng Bao [Sun, 5 Sep 2010 05:52:33 +0000 (05:52 +0000)]
Trivial. Currently the max frequency is preset as 400Mhz. We need to set a
platform specific value. Before that, we can set it manually if the boards
need to run in a higher frequency, which has been tested on Tilapia.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5777
2b7e53f0-3cfb-0310-b3e9-
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Kerry She [Sat, 4 Sep 2010 06:13:02 +0000 (06:13 +0000)]
AMD DDR2 and DDR3 MCT function InitPhyCompensation() compliant with AGESA code.
Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5776
2b7e53f0-3cfb-0310-b3e9-
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Jens Rottmann [Fri, 3 Sep 2010 15:16:36 +0000 (15:16 +0000)]
Update RoadRunner and SpaceRunner config to get in sync with current
standard BIOSes RRLX0013 and SRLX0013. Specifically move SPI and PME
I/Os to 0x1228 and 0x298 and switch SIO watchdog to ext. 48 MHz CLKIN.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5775
2b7e53f0-3cfb-0310-b3e9-
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Jens Rottmann [Fri, 3 Sep 2010 14:54:50 +0000 (14:54 +0000)]
The AMD CS5536's USB controllers are located at device 0F, functions 4
and 5. They're not found if only function 0 is checked. So if a device
exists at all, try all its functions. usb_controller_initialize() will
silently skip all device classes != 0C03.
(changed to continue to use 32bit accesses -pg)
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5774
2b7e53f0-3cfb-0310-b3e9-
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Warren Turkal [Fri, 3 Sep 2010 09:36:37 +0000 (09:36 +0000)]
Add support for dumping ACPI registers for i7
Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5773
2b7e53f0-3cfb-0310-b3e9-
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Warren Turkal [Fri, 3 Sep 2010 09:33:50 +0000 (09:33 +0000)]
Add support for dumping RCBA registers for i7
Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5772
2b7e53f0-3cfb-0310-b3e9-
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Warren Turkal [Fri, 3 Sep 2010 09:32:17 +0000 (09:32 +0000)]
Remove some errant spaces
Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5771
2b7e53f0-3cfb-0310-b3e9-
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Warren Turkal [Fri, 3 Sep 2010 09:31:13 +0000 (09:31 +0000)]
Add DMIBAR support for Intel X58 southbridge
Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5770
2b7e53f0-3cfb-0310-b3e9-
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Warren Turkal [Fri, 3 Sep 2010 08:57:32 +0000 (08:57 +0000)]
Add convenience rules for cscope to Makefile.
Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5769
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Fri, 3 Sep 2010 08:53:06 +0000 (08:53 +0000)]
The current workaround for binutils on mingw (or any non texinfo system) failed.
While we're at it, improve DESTDIR handling
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5768
2b7e53f0-3cfb-0310-b3e9-
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Myles Watson [Thu, 2 Sep 2010 22:02:53 +0000 (22:02 +0000)]
Fix compilation for mtarvon. CAR initialization does early_mtrr_init,
jarell/debug.c isn't ready for gcc, and skip_romstage() doesn't compile.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5767
2b7e53f0-3cfb-0310-b3e9-
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Myles Watson [Thu, 2 Sep 2010 20:30:31 +0000 (20:30 +0000)]
Trivial warning fix for adl855pc.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5766
2b7e53f0-3cfb-0310-b3e9-
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Myles Watson [Thu, 2 Sep 2010 18:36:29 +0000 (18:36 +0000)]
Fix abuild to build all boards. Revision 5754 changed the way vendors and
boards were specified in Kconfig, and abuild depended on that. Since that rev
it has only built qemu.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5765
2b7e53f0-3cfb-0310-b3e9-
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Myles Watson [Thu, 2 Sep 2010 18:29:31 +0000 (18:29 +0000)]
Revert 5762. It silently broke a lot of boards because abuild was broken.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5764
2b7e53f0-3cfb-0310-b3e9-
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Myles Watson [Wed, 1 Sep 2010 21:03:03 +0000 (21:03 +0000)]
Simplify last_dev_p so that it matches comments.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5763
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Wed, 1 Sep 2010 16:27:13 +0000 (16:27 +0000)]
Fix race condition in option_table.h generation by moving the include statement
to those files that actually need it. This significantly reduces the number of
dependencies, so it's no longer extremely ugly to specify them manually (see
the src/pc80/Makefile.inc portion)
Also, drop the AMD DBM690T work around for the issue.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5762
2b7e53f0-3cfb-0310-b3e9-
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Warren Turkal [Wed, 1 Sep 2010 03:40:57 +0000 (03:40 +0000)]
Add support for dumping GPIOS on Intel ICH10R. This information comes from the Intel ICH10 Family Datasheet.
Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5761
2b7e53f0-3cfb-0310-b3e9-
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Jens Rottmann [Tue, 31 Aug 2010 19:19:16 +0000 (19:19 +0000)]
SMC_CONFIG is needed before the device tree is ready and some people
would rather not have mainboard settings like sio_gp1x_config in the
device tree anyway. So found a nice united home for both in Kconfig,
where users can change them without having to mess around in the C code.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5760
2b7e53f0-3cfb-0310-b3e9-
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Jens Rottmann [Tue, 31 Aug 2010 19:02:45 +0000 (19:02 +0000)]
Make ALIX.2D3 support 2D2 as well.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5759
2b7e53f0-3cfb-0310-b3e9-
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Zheng Bao [Tue, 31 Aug 2010 06:10:54 +0000 (06:10 +0000)]
Get Byte65/66 for register manufacture ID code. RegMan1Present will
be used in write levelization training.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5758
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Myles Watson [Mon, 30 Aug 2010 21:52:38 +0000 (21:52 +0000)]
Make yabel work for non-zero bus numbers. The link_num is not the bus number.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5757
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Mon, 30 Aug 2010 17:53:13 +0000 (17:53 +0000)]
We call this cache as ram everywhere, so let's call it the same in Kconfig
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5756
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Mon, 30 Aug 2010 16:52:48 +0000 (16:52 +0000)]
Fix intel mtarvon compilation by switching it over to CAR.
This should be unproblematic, as there are other boards with the same "socket"
that work with CAR already. Tests are highly appreciated though!
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5755
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jens Rottmann [Mon, 30 Aug 2010 16:36:51 +0000 (16:36 +0000)]
Restructured all vendors' Kconfig files to no longer source the boards'
Kconfigs from within the choice/endchoice block. This makes it possible to
define user visible board specific options. Moved all vendor names and PCI
ids to the vendors' Kconfigs. Now all options in each file depend on the same
symbol, so replaced all "depends on"s with a single "if". Sorted boards
(sort -d), cleaned whitespace.
This patch also introduces a dummy option BOARD_SPECIFIC_OPTIONS, which is
always "y" and never used. It it simply needed to have something to attach
the boards' "select" statements to.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5754
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Andreas Schultz [Mon, 30 Aug 2010 16:32:23 +0000 (16:32 +0000)]
This file was missing from r5751.
Signed-off-by: Andreas Schultz <aschultz@tpip.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5753
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Andreas Schultz [Mon, 30 Aug 2010 16:22:22 +0000 (16:22 +0000)]
Support for Lanner EM-8510 Board
Signed-off-by: Andreas Schultz <aschultz@tpip.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
---
src/mainboard/Kconfig | 8 ++
src/mainboard/lanner/Kconfig | 8 ++
src/mainboard/lanner/em8510/Kconfig | 38 +++++++++++
src/mainboard/lanner/em8510/Makefile.inc | 21 ++++++
src/mainboard/lanner/em8510/chip.h | 23 +++++++
src/mainboard/lanner/em8510/cmos.layout | 74 +++++++++++++++++++++
src/mainboard/lanner/em8510/devicetree.cb | 60 +++++++++++++++++
src/mainboard/lanner/em8510/irq_tables.c | 56 ++++++++++++++++
src/mainboard/lanner/em8510/mainboard.c | 27 ++++++++
src/mainboard/lanner/em8510/romstage.c | 103 +++++++++++++++++++++++++++++
10 files changed, 418 insertions(+), 0 deletions(-)
create mode 100644 src/mainboard/lanner/Kconfig
create mode 100644 src/mainboard/lanner/em8510/Kconfig
create mode 100644 src/mainboard/lanner/em8510/Makefile.inc
create mode 100644 src/mainboard/lanner/em8510/chip.h
create mode 100644 src/mainboard/lanner/em8510/cmos.layout
create mode 100644 src/mainboard/lanner/em8510/devicetree.cb
create mode 100644 src/mainboard/lanner/em8510/irq_tables.c
create mode 100644 src/mainboard/lanner/em8510/mainboard.c
create mode 100644 src/mainboard/lanner/em8510/romstage.c
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5752
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Andreas Schultz [Mon, 30 Aug 2010 16:19:04 +0000 (16:19 +0000)]
Rework i855GM/i855GME support
Signed-off-by: Andreas Schultz <aschultz@tpip.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
---
src/northbridge/intel/i855/Kconfig | 30 +
src/northbridge/intel/i855/i855.h | 76 +++
src/northbridge/intel/i855/northbridge.c | 21 +
src/northbridge/intel/i855/raminit.c | 1036 +++++++++++++++++++++++++-----
src/northbridge/intel/i855/raminit.h | 14 +-
5 files changed, 1002 insertions(+), 175 deletions(-)
create mode 100644 src/northbridge/intel/i855/i855.h
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5751
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Andreas Schultz [Mon, 30 Aug 2010 16:16:01 +0000 (16:16 +0000)]
mPGA479M Sockets can take Intel Mobile Celeron.
The 1.2GHz model has CPUID F29. This adds them to the list of CPUs for that socket.
Signed-off-by: Andreas Schultz <aschultz@tpip.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
This patch likely breaks the following two boards since it unconditionally
activates CAR code for this socket:
* digitallogic/adl855pc
* intel/mtarvon
stepan suggests moving those two boards over to CAR, too, so we don't have to
worry.
---
src/cpu/intel/socket_mPGA479M/Kconfig | 1 +
src/cpu/intel/socket_mPGA479M/Makefile.inc | 2 ++
2 files changed, 3 insertions(+), 0 deletions(-)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5750
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Kerry She [Mon, 30 Aug 2010 09:40:41 +0000 (09:40 +0000)]
Multi-DIMMS on AMD ddr2 MCT channel B fixed.
Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5749
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Kerry She [Mon, 30 Aug 2010 07:31:31 +0000 (07:31 +0000)]
Multi-DIMMS on AMD ddr3 MCT channel B works.
Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5748
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Kerry She [Mon, 30 Aug 2010 07:24:13 +0000 (07:24 +0000)]
Trivial syntax correction of AMD mct_ddr3 dir.
Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Kerry She <Kerry.she@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5747
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Sat, 28 Aug 2010 23:23:47 +0000 (23:23 +0000)]
fix compilation of hello.elf example payload.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5746
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jens Rottmann [Fri, 27 Aug 2010 09:36:41 +0000 (09:36 +0000)]
drop three unneeded config variables:
- HAVE_HIGH_TABLES
- HAVE_LOW_TABLES
- FALLBACK_SIZE
Jens Rottmann sent an almost identical patch at the same time, so
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5745
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Myles Watson [Thu, 26 Aug 2010 18:24:04 +0000 (18:24 +0000)]
Remove unused mainboard_config definitions. Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5744
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jens Rottmann [Thu, 26 Aug 2010 12:46:02 +0000 (12:46 +0000)]
CONFIG_DEBUG_RAM_SETUP and CONFIG_DEBUG_SMBUS are only available if the board /
chipset support it. But this involves a long list of 'depends', which you have
to remember updating manually. Converted this into HAVE_... properties, which
will be inherited automatically if someone copies a chipset to create a new
one.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5743
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Thu, 26 Aug 2010 12:43:58 +0000 (12:43 +0000)]
One of my boards needs this mini delay in order to survive ram initialization.
Odd. The others don't.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5742
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Thu, 26 Aug 2010 12:42:43 +0000 (12:42 +0000)]
kontron 986lcd-m: Fix compilation if there is no oprom execution at all...
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5741
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Wed, 25 Aug 2010 18:35:42 +0000 (18:35 +0000)]
Fix i945 based boards
- prevent GCC from inlining do_ram_command - it will break RAM initialization.
- fix the PCIRST# mechanism in those boards that do it, it requires 200ms, not
200us
- move PCIRST# as early as possible (before ich7_enable_lpc)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5740
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Aurelien Guillaume [Tue, 24 Aug 2010 12:58:17 +0000 (12:58 +0000)]
* Adds support for PC Engines Alix.2D(1)3 board to Coreboot.
* DRAM initialization done message is now printed in debug-mode only, rather than everytime.
Signed-off-by: Aurelien Guillaume <aurelien@iwi.me>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5739
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Mon, 23 Aug 2010 18:43:27 +0000 (18:43 +0000)]
mark unused variables in x86emu as unused. gcc has a mechanism for this.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5738
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Wang Qing Pei [Sun, 22 Aug 2010 20:02:27 +0000 (20:02 +0000)]
Fix up some copyrights
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5737
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Sun, 22 Aug 2010 20:00:42 +0000 (20:00 +0000)]
I've checked Revision Guide for AMD Family10h processors (#41322) rev
3.74 June 2010 for errata 351 and it agrees with the comment on
setting ForceFullT0= 000b but I believe the code didn't honor the
comment.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5736
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Sun, 22 Aug 2010 19:59:27 +0000 (19:59 +0000)]
RB_C3 should also apply the workaround for errata 354, according to
Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5735
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Sun, 22 Aug 2010 19:56:47 +0000 (19:56 +0000)]
RB_C3 and HY-D0 should also apply the workaround for errata 344, according to
Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010
My processor wasn't getting the workaround
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5734
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Sun, 22 Aug 2010 19:54:26 +0000 (19:54 +0000)]
documented workaround erratum 414, see
Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010
with patch.erratum414 it stops here (next patches don't make it get further,
but they're needed according to documentation, don't break anything for me and
I still don't have a solution for booting, so I'm keeping them there in case
they fix something.
testx =
5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx =
5a5a5a5a
Disabling cache as ram now
Clearing initial memory region: Done
Loading stage image.
Check CBFS header at
fffffd2e
magic is
4f524243
Found CBFS header at
fffffd2e
Check fallback/romstage
CBFS: follow chain:
fff00000 + 38 + 15b41 + align ->
fff15b80
Check fallback/coreboot_ram
Stage: loading fallback/coreboot_ram @ 0x200000 (
1114112 bytes), entry @
0x20000
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5733
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Sun, 22 Aug 2010 19:51:34 +0000 (19:51 +0000)]
documented workaround erratum 372, see
Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010
with this one it stops here or earlier (as soon as before the patch,
sometimes):
*** Yes, the copy/decompress is taking a while, FIXME!
v_esp=
000cbf48
testx =
5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx =
5a5a5a5a
Disabling cache as ram now
Clearing initial memory region:
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5732
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Sun, 22 Aug 2010 19:49:46 +0000 (19:49 +0000)]
Complete code for errata 343. Revision Guide for AMD Family10h
processors (#41322) rev 3.74 June 2010 says to set the register
to 1 before CAR and to 0 after. We were setting it to 0 after CAR,
but not to 1 before.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5731
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Sun, 22 Aug 2010 19:48:29 +0000 (19:48 +0000)]
Include RB_C3 in erratum 346
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5730
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Xavi Drudis Ferran [Sun, 22 Aug 2010 19:45:57 +0000 (19:45 +0000)]
Add RB_C3 to AMD_FAM10_ALL so that it gets its MSR right for mtrs, ht, etc.
While reviewing impact of this change it seems code for erratum 531 was not in
sync with current docs. I have checked uses of AMD_FAM10_ALL, but I
haven't looked up the docs for all of them, at first sight it seems ok
to include all FAM10 revisions in this mask.
Apply errata 531 only to revisions listed in Revision Guide for AMD Family10h
processors (#41322) rev 3.74 June 2010. Before it was applied also to
DR-B0, DA-C3 or HY-D0 which are not affected according to current docs.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5729
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Anders Juel Jensen [Sun, 22 Aug 2010 19:41:47 +0000 (19:41 +0000)]
Add suport for normal register dumping on ite8510E/TE/G
Signed-off-by: Anders Juel Jensen <andersjjensen@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5728
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Anders Juel Jensen [Sun, 22 Aug 2010 19:40:58 +0000 (19:40 +0000)]
Add another port to find ite8510 on.
Signed-off-by: Anders Juel Jensen <andersjjensen@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5727
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Anders Juel Jensen [Sun, 22 Aug 2010 19:40:11 +0000 (19:40 +0000)]
Add support for non LDN register/device naming.
Signed-off-by: Anders Juel Jensen <andersjjensen@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5726
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Anders Juel Jensen [Sun, 22 Aug 2010 19:39:04 +0000 (19:39 +0000)]
The LDFLAGS = -lz is needed to compile on slackware.
Clubbering CFLAGS is never a good idea.
Signed-off-by: Anders Juel Jensen <andersjjensen@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5725
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Myles Watson [Fri, 20 Aug 2010 20:45:04 +0000 (20:45 +0000)]
Remove a couple of warnings. Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5724
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Oskar Enoksson [Fri, 20 Aug 2010 20:37:27 +0000 (20:37 +0000)]
Add support for the HP DL145 G1, based on the Tyan s2881.
Signed-off-by: Oskar Enoksson <oskeno@foi.se>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5723
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jens Rottmann [Wed, 18 Aug 2010 21:23:27 +0000 (21:23 +0000)]
libpayload: fix garbage on screen with Geode-LX VGA
Clear initial garbage in VGA memory and fix scroll_up, which scrolled 1 scanline
instead of 1 text line by mistake.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5722
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Wang Qing Pei [Wed, 18 Aug 2010 01:55:11 +0000 (01:55 +0000)]
The attached file add pa78vm5 dev3 detection function to avoid the building error.
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5721
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Rudolf Marek [Tue, 17 Aug 2010 21:03:17 +0000 (21:03 +0000)]
Attached patch removes unnecessary IRQ routing info (for ACPI, mptable etc needs to be fixed too). The devicetree.cb changes should reflect now the real board configuration. It has one 16x slot and 1x slot (GPP device 9) and GPP device a is onboard ethernet. The mainboard.c now presents the board name and
I removed the gpio asserts - I think those are not used here.
The pcie 1x slot works, the x1 card I have does not work in 16x slot, but in orig bios I cannot see it any slot, so it is kind of better.
The classic PCI slot works fine too. However it seems SATA has some issues.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5720
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jens Rottmann [Tue, 17 Aug 2010 16:32:42 +0000 (16:32 +0000)]
Correct for size_t would be %zx, but coreboot's printf doesn't support this.
Trying to keep it simple: Two sizes are expected equal so use same %x for both.
Cast to unsigned int to make sure it fits.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5719
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Wang Qing Pei [Tue, 17 Aug 2010 15:19:32 +0000 (15:19 +0000)]
Commit (non-working!) Jetway PA78VM5 mainboard
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5718
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Wang Qing Pei [Tue, 17 Aug 2010 15:05:05 +0000 (15:05 +0000)]
Support for Fintek F71863FG. This might need some work on the copyright
notices. Getting it into the tree so people can get to it.
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5717
2b7e53f0-3cfb-0310-b3e9-
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Marc Bertens [Tue, 17 Aug 2010 11:32:21 +0000 (11:32 +0000)]
image parsing for getpir
when adding for example build/coreboot_ram as parameter
it looks in the file for the PIRQ table prints it to stdout
and shows if the checksum is correct.
getpir works as before without any commandline parameters.
This is very handy for developing a PIRQ table.
Signed-off-by: Marc Bertens <mbertens@xs4all.nl>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5716
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Wang Qing Pei [Tue, 17 Aug 2010 11:22:40 +0000 (11:22 +0000)]
Another AMD 780/700 mainboard: Gigabyte MA78GM-US2H
http://www.gigabyte.cn/products/product-page.aspx?pid=3118#ov
the simple config is
AM2+DDR2+SB700+RS780, the superIO is IT8718F
The patch has been tested with SeaBIOS + SUSE11.2
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5715
2b7e53f0-3cfb-0310-b3e9-
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Wang Qing Pei [Tue, 17 Aug 2010 11:11:09 +0000 (11:11 +0000)]
Tilapila supports both dual slot and single slot. The difference should be
detected by the existence of dev3. Some other RS780 mainboard has
the same function. The patch added the function to make these boards work
smoothly.
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5714
2b7e53f0-3cfb-0310-b3e9-
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Wang Qing Pei [Tue, 17 Aug 2010 11:08:31 +0000 (11:08 +0000)]
Add support for Gigabyte MA785GMT mainboard.
Details of the hardware configuration can be found at
http://www.gigabyte.com/products/product-page.aspx?pid=3478
Brief configuration is:
1. CPU:Support for AM3 processors: AMD PhenomTM II processor/ AMD Athlon™ II processor
2. North Bridge: AMD 785G
3. South Bridge: AMD SB710
4: Super IO : ITE8718F
The mainboard has two bios flashchip. Coreboot ROM should be flashed into the
M_BIOS (which means main bios).
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5713
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Tue, 17 Aug 2010 10:54:36 +0000 (10:54 +0000)]
fix nokia ip530 Kconfig, missed on last check-in
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5712
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Tue, 17 Aug 2010 10:14:50 +0000 (10:14 +0000)]
libpayload: Add function to fix CMOS checksum.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5711
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Tue, 17 Aug 2010 09:52:01 +0000 (09:52 +0000)]
Whatever happened here,... The DEC Tulip is a network card, no bridge of any
kind. Move it to drivers and make the necessary adaptions. Also drop empty
drivers/generic/generic and start cleaning up Makefiles in drivers/
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5710
2b7e53f0-3cfb-0310-b3e9-
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Corey Osgood [Tue, 17 Aug 2010 08:33:44 +0000 (08:33 +0000)]
Add support for the Intel NM10 (a variant of ICH7) and ICH8 southbridges.
Both are tested and appear to be working, however I'm not 100% clear
on if the NM10 has any other PCI IDs.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Paul Menzel <paulepanter@users.sourceforge.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5709
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Stefan Reinauer [Tue, 17 Aug 2010 08:24:01 +0000 (08:24 +0000)]
Add support for Fintek
F81216D/DG/AD
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5708
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1