Fix i945 based boards

- prevent GCC from inlining do_ram_command - it will break RAM initialization.
- fix the PCIRST# mechanism in those boards that do it, it requires 200ms, not
  200us
- move PCIRST# as early as possible (before ich7_enable_lpc)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5740 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index 451f5d9d8a50b9c965c88952284cc5f949064bf6..9f7c14af520f40d3e39e1f1221895589253bf65b 100644 (file)
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -308,9 +308,8 @@ void main(unsigned long bist)
 #if 0
        /* Force PCIRST# */
        pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
-       udelay(200);
+       udelay(200 * 1000);
        pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
-       udelay(200);
 #endif
 
        ich7_enable_lpc();

diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 5faf699129a308452eeaf4f7d6a84784baf54147..902e5c267914d0a82edc4d1fef047f19e6f7d70e 100644 (file)
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -366,14 +366,12 @@ void main(unsigned long bist)
                enable_lapic();
        }
 
-       ich7_enable_lpc();
-
        /* Force PCIRST# */
        pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
-       udelay(200);
+       udelay(200 * 1000);
        pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
-       udelay(200);
 
+       ich7_enable_lpc();
        early_superio_config_w83627thg();
 
        /* Set up the console */

diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index 19b29053e38c0184d1723fe3035d441330c245ce..00c4c9f446c2f1b82d48e51ed32399d125f2254e 100644 (file)
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -279,11 +279,12 @@ void main(unsigned long bist)
                enable_lapic();
        }
 
-       ich7_enable_lpc();
-
        /* Force PCIRST# */
        pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
+       udelay(200 * 1000);
+       pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
 
+       ich7_enable_lpc();
        early_superio_config();
 
        /* Set up the console */

diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index b05a553c5a2daf1f3a23e34748e247813181fb0d..23390cffb62a2f8cc91c7bf190f9d9f578e2f89e 100644 (file)
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -45,7 +45,7 @@
 #define RAM_EMRS_2                     (0x1 << 21)
 #define RAM_EMRS_3                     (0x2 << 21)
 
-static void do_ram_command(u32 command)
+static __attribute__((noinline)) void do_ram_command(u32 command)
 {
        u32 reg32;