Stefan Reinauer [Tue, 25 Jan 2011 19:27:23 +0000 (19:27 +0000)]
Fix abuild
thanks to Kevin who came up with this
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6298
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Zheng Bao [Tue, 25 Jan 2011 06:06:58 +0000 (06:06 +0000)]
Set the SB800 SATA PHY correctly.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6297
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Stefan Reinauer [Mon, 24 Jan 2011 21:27:22 +0000 (21:27 +0000)]
If the tool has 64bit issues, we need to find and fix them. No papering over them.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6296
2b7e53f0-3cfb-0310-b3e9-
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Josef Kellermann [Mon, 24 Jan 2011 21:07:57 +0000 (21:07 +0000)]
This patch fixes an 'write_tables: coreboot table didn't fit (f0221)' issue.
Signed-off-by: Josef Kellermann <Joseph.Kellermann@heitec.de>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6295
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Rudolf Marek [Mon, 24 Jan 2011 21:05:53 +0000 (21:05 +0000)]
Add CFLAGS when compiling resulting executable. It broke 64bit systems, because the rest uses -m32 now.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6294
2b7e53f0-3cfb-0310-b3e9-
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Zheng Bao [Mon, 24 Jan 2011 07:50:07 +0000 (07:50 +0000)]
Change fadt revision back to 3.
The AcpiPmaCntBlk have to be set.
Further research is needed to find out why.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6293
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Kevin O'Connor [Sun, 23 Jan 2011 06:47:09 +0000 (06:47 +0000)]
Clone a tag rather than SeaBIOS stable branch HEAD
Use a tag (rel-0.6.1.3) for SeaBIOS stable checkouts instead of the
stable branch. The tag is a little safer because it prevents an
incorrect commit to the stable branch from being immiediately picked
up by coreboot users.
Note - rel-0.6.1.3 (and 0.6.1-stable) now have the CFLAGS build fix
that was causing build failures for coreboot users.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6292
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Patrick Georgi [Fri, 21 Jan 2011 13:20:10 +0000 (13:20 +0000)]
... And fix the other compile time issues in cmos_layout.bin support
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6291
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Fri, 21 Jan 2011 12:45:37 +0000 (12:45 +0000)]
Make YABEL warnings-are-errors safe
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6290
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Patrick Georgi [Fri, 21 Jan 2011 11:43:06 +0000 (11:43 +0000)]
Typo. s,CMOS_COMPONENT,CBFS_COMPONENT,.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6289
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Zheng Bao [Fri, 21 Jan 2011 08:46:27 +0000 (08:46 +0000)]
Now bimini can boot linux to login.
Note:
1. bimini_fam10/Kconfig: Set GENERATE_MP_TABLE in Kconfig. This will make sure the
smp_write_config_table will run. Then intr_data will be written
into 0xC00/0xC01.
2. bootblock: Use PCI_DEV(0, 0x14, 3) instead of
pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB800_LPC), 0).
The pci_locate_device will cause the system crash.
3. fadt.c: Change fadt revision to 1. 3 will cause the linux hang. Why?
4. early_setup.c: pmio 0x65 has change its meaning.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6288
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Stefan Reinauer [Fri, 21 Jan 2011 07:46:32 +0000 (07:46 +0000)]
push ts5300 rom size to 1MB. In fact the flash part on that
board is 2MB and the entry point is somewhere in the middle. quite weird setup
http://www.embeddedarm.com/products/board-detail.php?product=TS-5300
We should probably wipe the board from the tree. It will not work anyways with
current coreboot and the architecture is kind of obscure.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6287
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Patrick Georgi [Fri, 21 Jan 2011 07:29:40 +0000 (07:29 +0000)]
Add nvramtool -D option that allows taking cmos data from
a plain binary file. Overrides using cmos.default in CBFS
if both -C and -D are given.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6286
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Fri, 21 Jan 2011 07:24:08 +0000 (07:24 +0000)]
Add nvramtool -C option that takes a CBFS file as argument.
When using this option, nvramtool looks for a cmos_layout.bin
and cmos.default in the image and uses these for layout information
and CMOS data.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6285
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Patrick Georgi [Fri, 21 Jan 2011 07:19:59 +0000 (07:19 +0000)]
Add support for working on in-memory CMOS data (eg.
as loaded from a file).
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6284
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Fri, 21 Jan 2011 07:18:20 +0000 (07:18 +0000)]
Abstract CMOS accesses a bit more in preparation of using
files for CMOS data.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6283
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Fri, 21 Jan 2011 07:04:05 +0000 (07:04 +0000)]
There's another place where nvramtool can look for
the CMOS checksum specification.
When using nvramtool on files (instead of CMOS and runtime firmware)
it's the only place.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6282
2b7e53f0-3cfb-0310-b3e9-
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Zheng Bao [Thu, 20 Jan 2011 06:28:25 +0000 (06:28 +0000)]
Remove the code for debugging.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6281
2b7e53f0-3cfb-0310-b3e9-
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Zheng Bao [Thu, 20 Jan 2011 05:59:22 +0000 (05:59 +0000)]
S3 feanture of SB800. Compiliant with SB700.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6280
2b7e53f0-3cfb-0310-b3e9-
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Zheng Bao [Thu, 20 Jan 2011 05:41:11 +0000 (05:41 +0000)]
Move some board specific functions to sb800.h.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6279
2b7e53f0-3cfb-0310-b3e9-
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Zheng Bao [Thu, 20 Jan 2011 05:29:37 +0000 (05:29 +0000)]
Features of Bimini board:
RS785
SB800
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6278
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Zheng Bao [Thu, 20 Jan 2011 04:45:48 +0000 (04:45 +0000)]
This sb800 code is derived from sb700.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6277
2b7e53f0-3cfb-0310-b3e9-
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Zheng Bao [Thu, 20 Jan 2011 02:09:24 +0000 (02:09 +0000)]
For Cx, each ChipSel need to be sent MR command.
After this patch, tilapia can run in higher memory frequency.
To test the high frequency, dont forget to change the freq limit in
mcti_d.c:
static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
{
pDCTstat->PresetmaxFreq = 800;
}
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6276
2b7e53f0-3cfb-0310-b3e9-
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Nils Jacobs [Wed, 19 Jan 2011 07:25:26 +0000 (07:25 +0000)]
Add a GX2 Kconfig option to choose the framebuffer size.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6275
2b7e53f0-3cfb-0310-b3e9-
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Nils Jacobs [Wed, 19 Jan 2011 06:56:33 +0000 (06:56 +0000)]
Add Geode GX2 memmory descriptors.
Add a simple README file.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6274
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Wed, 19 Jan 2011 06:54:42 +0000 (06:54 +0000)]
Revert r5902 to make code more readable again. At least three people like to
have this go away again.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Kevin O'Connor <kevin@koconnor.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6273
2b7e53f0-3cfb-0310-b3e9-
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Kevin O'Connor [Wed, 19 Jan 2011 06:32:35 +0000 (06:32 +0000)]
Now that the VIA code is run above 1Meg (like other boards), it should
cache that range instead of the first 1Meg. This reduces boot time by
about 1 second on epia-cn.
This patch also adds a MTRRphysMaskValid bit definition.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6272
2b7e53f0-3cfb-0310-b3e9-
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Kevin O'Connor [Wed, 19 Jan 2011 06:31:24 +0000 (06:31 +0000)]
The cn700.c code references mainboard_interrupt_handlers() which isn't
defined if VGA_ROM_RUN is off. Define a dummy implementation of that
function for this case.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6271
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Tue, 18 Jan 2011 14:38:59 +0000 (14:38 +0000)]
Fix fwrite tests.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6270
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Tue, 18 Jan 2011 14:28:45 +0000 (14:28 +0000)]
Report if cmos_layout.bin can't be found when it should.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6269
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Tue, 18 Jan 2011 13:56:36 +0000 (13:56 +0000)]
Move option table (cmos.layout's binary representation)
to CBFS and adapt coreboot to use it.
Comments by Stefan and Mathias taken into account (except for
the build time failure if the table is missing when it should
exist and the "memory leak" in build_opt_tbl)
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6268
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Tue, 18 Jan 2011 12:14:08 +0000 (12:14 +0000)]
Remove overengineering, part 1/many
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6267
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Tue, 18 Jan 2011 12:12:47 +0000 (12:12 +0000)]
Eliminate strict aliasing related warnings.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6266
2b7e53f0-3cfb-0310-b3e9-
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Zheng Bao [Tue, 18 Jan 2011 09:36:44 +0000 (09:36 +0000)]
remove the code which is not ready to release.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6265
2b7e53f0-3cfb-0310-b3e9-
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Zheng Bao [Tue, 18 Jan 2011 09:34:31 +0000 (09:34 +0000)]
remove the code which is not ready to release.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6264
2b7e53f0-3cfb-0310-b3e9-
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Zheng Bao [Tue, 18 Jan 2011 09:32:15 +0000 (09:32 +0000)]
remove the code which is not ready to release.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6263
2b7e53f0-3cfb-0310-b3e9-
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Zheng Bao [Tue, 18 Jan 2011 09:31:29 +0000 (09:31 +0000)]
remove the code which is not ready to release.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6262
2b7e53f0-3cfb-0310-b3e9-
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Zheng Bao [Tue, 18 Jan 2011 09:29:19 +0000 (09:29 +0000)]
remove the code which is not ready to release.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6261
2b7e53f0-3cfb-0310-b3e9-
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Peter Stuge [Mon, 17 Jan 2011 05:08:32 +0000 (05:08 +0000)]
cbfstool: When extracting, refer to files in CBFS as file instead of payload
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6260
2b7e53f0-3cfb-0310-b3e9-
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Peter Stuge [Mon, 17 Jan 2011 05:02:09 +0000 (05:02 +0000)]
cbfstool: Trivial move of newline after commands in usage
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6259
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Zheng Bao [Mon, 17 Jan 2011 02:20:33 +0000 (02:20 +0000)]
The code is tested on my board with register DIMMs. More tests need to be
done. Please send the testing report.
Note: The pDCTstat->PresetmaxFreq in mctGet_MaxLoadFreq() should be set
to a higher limit, otherwise the frequnce will be set as 400MHz.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Scott Duplichan <scott@notabs.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6258
2b7e53f0-3cfb-0310-b3e9-
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Rudolf Marek [Sun, 16 Jan 2011 17:15:36 +0000 (17:15 +0000)]
Ooops lets see if this extra comment removal fixes this.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6257
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Rudolf Marek [Sun, 16 Jan 2011 16:23:51 +0000 (16:23 +0000)]
Trivial, cleanup of GPIO comments.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6256
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Fri, 14 Jan 2011 08:36:34 +0000 (08:36 +0000)]
Disable CMOS recovery code for ROMCC boards as the CBFS code used for
that feature is not ROMCC compatible.
Fixes build errors introduced in r6253.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6255
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Fri, 14 Jan 2011 07:41:42 +0000 (07:41 +0000)]
Improved GPIO setup for roda/rk886ex, and some documentation
on what the GPIOs are used for.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6254
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Fri, 14 Jan 2011 07:40:24 +0000 (07:40 +0000)]
Allow coreboot to initialize CMOS if checksum is invalid.
If a file "cmos.default", type "cmos default"(0xaa) is in CBFS,
a wrong checksum leads to coreboot rewriting the first 128 bytes
(except for clock data) with the data in cmos.default, then
reboots the system so every component of coreboot works with the
same set of values.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6253
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Thu, 13 Jan 2011 11:40:38 +0000 (11:40 +0000)]
Default to CRT on Kontron/986lcd-m. "default display" doesn't always
select the right output device.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6252
2b7e53f0-3cfb-0310-b3e9-
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Patrick Georgi [Thu, 13 Jan 2011 11:38:46 +0000 (11:38 +0000)]
Improve compatibility of YABEL with real-world VGABIOSes
Some of them do weird things to the option rom region (mapping
registers there or so) which failed as we handled these memory
region in emulation. As they were copied back to real memory
after the emulation was done, we can just as well use real
memory directly for these regions.
This affects IVT, BDA, and option ROM space.
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6251
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Aurelien Guillaume [Thu, 13 Jan 2011 09:09:21 +0000 (09:09 +0000)]
Add "cbfstool extract" function.
It dumps everything you ask for, but you might not
get what you expect if the file is compressed or
otherwise converted (eg. payloads in SELF format).
(Originally it would only extract "raw" files.
This is a change by me, as filetypes are commonly used
to differentiate raw data files --Patrick)
Signed-off-by: Aurelien Guillaume <aurelien@iwi.me>
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6250
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Wed, 12 Jan 2011 21:09:25 +0000 (21:09 +0000)]
drop unused files
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6249
2b7e53f0-3cfb-0310-b3e9-
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Kerry She [Tue, 11 Jan 2011 02:15:57 +0000 (02:15 +0000)]
change a readable way to fix SB800 CIMX "multi-character constant warning".
by using 'Int32FromChar' macro, instead of the ASCII code.
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6248
2b7e53f0-3cfb-0310-b3e9-
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Marc Bertens [Thu, 6 Jan 2011 23:03:46 +0000 (23:03 +0000)]
Various Nokia IP530 fixes.
- Correct default ROM image size for this board (512KB is correct).
- devicetree.cb: Add AUX I/O config (mainly GPIO settings).
This allows you to control the LEDs in the front panel and JP900/JP901
can be read.
- irq_tables.c: Rework PIRQ table to make more onboard devices work.
Also, avoid IRQ9.
- mainboard.c: Drop unneeded functions, everything is done in devicetree.cb.
Signed-off-by: Marc Bertens <mbertens@xs4all.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6247
2b7e53f0-3cfb-0310-b3e9-
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Zheng Bao [Thu, 6 Jan 2011 02:18:12 +0000 (02:18 +0000)]
Fix some settings fo AMD MCT. It is based on BIOS test suite.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6246
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Wed, 5 Jan 2011 02:40:53 +0000 (02:40 +0000)]
uart_init is only used in romstage.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6245
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Wed, 5 Jan 2011 02:27:53 +0000 (02:27 +0000)]
move single options out of main menu and remove stray "options"
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6244
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Wed, 5 Jan 2011 02:10:50 +0000 (02:10 +0000)]
fix compilation of mconf on some systems.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6243
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Wed, 5 Jan 2011 01:37:48 +0000 (01:37 +0000)]
fix "make clean"
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6242
2b7e53f0-3cfb-0310-b3e9-
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Uwe Hermann [Tue, 4 Jan 2011 19:51:33 +0000 (19:51 +0000)]
MCP55: Cosmetic fixes, switch to u8 et al.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6241
2b7e53f0-3cfb-0310-b3e9-
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Uwe Hermann [Tue, 4 Jan 2011 17:36:55 +0000 (17:36 +0000)]
CK804: Cosmetic fixes, switch to u8 et al.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6240
2b7e53f0-3cfb-0310-b3e9-
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Kerry She [Tue, 4 Jan 2011 06:39:29 +0000 (06:39 +0000)]
Trivial:
add missed CIMx file to romstage. in order to link them into romstage, move all CIMx table to .rodata section.
Run dos2unix on Makefile.inc, which is not upstream CIMx code
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Kerry She <kerry.she@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6239
2b7e53f0-3cfb-0310-b3e9-
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Kerry She [Tue, 4 Jan 2011 06:15:46 +0000 (06:15 +0000)]
Trivial: use the IO_APIC_ADDR constant defined in ioapic.h, and spell check
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Kerry She <kerry.she@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6238
2b7e53f0-3cfb-0310-b3e9-
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Uwe Hermann [Sat, 1 Jan 2011 23:36:03 +0000 (23:36 +0000)]
src/southbridge/amd/cimx_wrapper: Run dos2unix on the files.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6237
2b7e53f0-3cfb-0310-b3e9-
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Uwe Hermann [Sat, 1 Jan 2011 23:30:37 +0000 (23:30 +0000)]
AMD SB800: Drop component prefix from filenames.
We did the same with other chipsets in r6150.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6236
2b7e53f0-3cfb-0310-b3e9-
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Uwe Hermann [Sat, 1 Jan 2011 22:05:57 +0000 (22:05 +0000)]
Add detection support for the ITE IT8721F.
Tested on hardware by me.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6235
2b7e53f0-3cfb-0310-b3e9-
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Uwe Hermann [Sat, 1 Jan 2011 18:58:39 +0000 (18:58 +0000)]
AMD Bimini: Use mptable_init() in mptable.c.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6234
2b7e53f0-3cfb-0310-b3e9-
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Uwe Hermann [Sat, 1 Jan 2011 18:40:02 +0000 (18:40 +0000)]
AMD Bimini: Small fixes, and updates to recent trunk conventions.
- Move CACHE_AS_RAM_ADDRESS_DEBUG #define to Kconfig, where it was renamed
to HAVE_DEBUG_CAR in r5898.
- Move QRANK_DIMM_SUPPORT to Kconfig, see r6028.
- Drop obsolete/unused COMPRESS, see r6145.
- Drop obsolete SET_NB_CFG_54, see r6086.
- Move SET_FIDVID/SET_FIDVID_CORE_RANGE to Kconfig, see r6077.
Actually, the default for SET_FIDVID_CORE_RANGE is 0, so drop it.
- Rename some GENERATE_* options to HAVE_*, see r6027.
- Drop "select CACHE_AS_RAM", this is now set in the socket, see r6151.
- Drop ACPI_SSDTX_NUM, the global default is 0 already.
- Random whitespace and coding style fixes.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6233
2b7e53f0-3cfb-0310-b3e9-
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Uwe Hermann [Sat, 1 Jan 2011 18:10:07 +0000 (18:10 +0000)]
AMD Bimini: Drop duplicate ASL files as we did for other boards.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6232
2b7e53f0-3cfb-0310-b3e9-
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Kerry She [Sat, 1 Jan 2011 18:04:42 +0000 (18:04 +0000)]
Add support for the AMD Bimini eval mainboard.
Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6231
2b7e53f0-3cfb-0310-b3e9-
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Kerry She [Sat, 1 Jan 2011 17:52:34 +0000 (17:52 +0000)]
Add AMD SB800 southbridge support via cimx_wrapper.
Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6230
2b7e53f0-3cfb-0310-b3e9-
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Kerry She [Sat, 1 Jan 2011 17:44:07 +0000 (17:44 +0000)]
Add AMD SB800 southbridge CIMx code.
The main CIMx code is in a src/vendorcode directory and should not be
changed with regard to coding style etc. in order to remain easily syncable
with the "upstream" AMD code.
Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6229
2b7e53f0-3cfb-0310-b3e9-
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Jonathan Kollasch [Fri, 31 Dec 2010 19:20:23 +0000 (19:20 +0000)]
Use $(MAKE) instead of make when cleaning for SeaBIOS.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6228
2b7e53f0-3cfb-0310-b3e9-
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Zheng Bao [Fri, 31 Dec 2010 01:46:12 +0000 (01:46 +0000)]
Add RS785(RS880) support. Just few pci_ids.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6227
2b7e53f0-3cfb-0310-b3e9-
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Zheng Bao [Fri, 31 Dec 2010 01:38:45 +0000 (01:38 +0000)]
Add detection of Nuvoton WPCM450.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6226
2b7e53f0-3cfb-0310-b3e9-
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Nils Jacobs [Thu, 30 Dec 2010 19:23:29 +0000 (19:23 +0000)]
Remove duplicated GX2 processor IIOC mode setting on CS5535 southbridge code
and fix CIS mode comments.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6225
2b7e53f0-3cfb-0310-b3e9-
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Nils Jacobs [Thu, 30 Dec 2010 19:21:08 +0000 (19:21 +0000)]
Use die() to assure the processor can't wake up from an interrupt.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6224
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Thu, 30 Dec 2010 17:39:50 +0000 (17:39 +0000)]
Per default, use SeaBIOS payload instead of no payload.
Add choice to use stable or master version of seabios repository
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6223
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Thu, 30 Dec 2010 16:57:58 +0000 (16:57 +0000)]
superiotool: Don't skip probing on a port if a a chip was detected on another port.
Only skip probing if chip was found on the same port already to avoid
duplicates.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6222
2b7e53f0-3cfb-0310-b3e9-
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Nils Jacobs [Wed, 29 Dec 2010 21:12:10 +0000 (21:12 +0000)]
-Change the remaining GLIU1 port 5 register names from VIP (Video Input Port)
to FG (FooGlue). As the GX2 has no VIP port.
-Change the Memmory setup MSR register names so they correspond better to the
databook. (Part1)
This is less confusing for beginners.
-Add a MSR printing function to northbridge.c like in the Geode LX code.
-Remove the AES register names.(GX2 has no AES registers)
-Delete some unused code.
-Clean up GX2 northbridge code to match Geode LX code.
-Add missing copyright header to northbridge.c.
-Move hardcoded IRQ defining from northbridge.c to irq_tables.c .
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6221
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Wed, 29 Dec 2010 21:02:50 +0000 (21:02 +0000)]
fix i810 boards with ram init debugging disabled.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6220
2b7e53f0-3cfb-0310-b3e9-
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Nils Jacobs [Wed, 29 Dec 2010 20:31:31 +0000 (20:31 +0000)]
-Clean up some comments.
-Remove some white spaces.
-Remove some leading zeros.
-Fix a typo in LX code.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6219
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Mon, 27 Dec 2010 14:31:05 +0000 (14:31 +0000)]
proper printk handling in src/northbridge/intel/i82810/raminit.c
and drop some romcc relics in 440bx code too
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6218
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Mon, 27 Dec 2010 13:30:39 +0000 (13:30 +0000)]
__PRE_RAM__ is defined by the makefile
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6217
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Mon, 27 Dec 2010 13:29:38 +0000 (13:29 +0000)]
dump_spd_registers() is only defined when ram init debugging is on.
Most boards unconditionally call this. Fix it in header file instead of each single romstage.c
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6216
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Mon, 27 Dec 2010 11:34:57 +0000 (11:34 +0000)]
Fix most CONFIG_DEBUG_RAM_SETUP issues.
The intel/xe7501devkit is still broken, I think the (romcc) image is too big to
fit in the bootblock if CONFIG_DEBUG_RAM_SETUP is enabled. It would make sense
to convert all CPU_INTEL_SOCKET_MPGA604 to CAR, but I have no hardware to test.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6215
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Mon, 27 Dec 2010 08:21:23 +0000 (08:21 +0000)]
Intel SCH: make state machine binary selection available in Kconfig for now.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6214
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Sun, 26 Dec 2010 16:49:57 +0000 (16:49 +0000)]
All the values should stay untouched or be set automatically by the resource
allocator. If that does not work out, they should be set in the code. Setting
them in Kconfig is the worst possible thing to do.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6213
2b7e53f0-3cfb-0310-b3e9-
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Uwe Hermann [Sun, 26 Dec 2010 14:12:38 +0000 (14:12 +0000)]
Random fixes for TI pci1x2x / Nokia IP530 / others.
- nokia/ip530/devicetree.cb, southbridge/ti/pci1x2x/pci1x2x.c:
- Fix SMSC
FDC37B787 name (was a typo).
- Disable PS/2 keyboard/mouse LDN, the IP530 doesn't have either.
- Fix typo: s/PCI_DEVICE_ID_TI_1420/PCI_DEVICE_ID_TI_1520/.
- All of these are confirmed by Marc Bertens on IRC.
- Fix a few CHIP_NAME HP board names.
- Random whitespace and coding-style fixes.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6212
2b7e53f0-3cfb-0310-b3e9-
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Nils Jacobs [Sun, 26 Dec 2010 05:24:50 +0000 (05:24 +0000)]
Move Geode GX2 UMA video memory size to Kconfig
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6211
2b7e53f0-3cfb-0310-b3e9-
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Nils Jacobs [Sun, 26 Dec 2010 05:21:18 +0000 (05:21 +0000)]
Remove dead and unused Geode GX2 code
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6210
2b7e53f0-3cfb-0310-b3e9-
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Nils Jacobs [Sun, 26 Dec 2010 05:16:47 +0000 (05:16 +0000)]
Replace Geode GX2 MSR addresses for GLCP on GLIU1 with names
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6209
2b7e53f0-3cfb-0310-b3e9-
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Nils Jacobs [Sun, 26 Dec 2010 05:12:49 +0000 (05:12 +0000)]
Clean up Geode GX2 comments, whitespace and coding style. Trivial.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6208
2b7e53f0-3cfb-0310-b3e9-
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Uwe Hermann [Sat, 25 Dec 2010 22:54:41 +0000 (22:54 +0000)]
Nokia IP530: Add missing "select SDRAMPWR_4DIMM".
This is needed for all Intel 440BX boards with 4 DIMM slots (such as this one).
Thanks Marc Bertens <mbertens@xs4all.nl> for bringing up the issue and
for the success report for this fix on IRC.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6207
2b7e53f0-3cfb-0310-b3e9-
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Keith Hui [Thu, 23 Dec 2010 17:12:03 +0000 (17:12 +0000)]
Fix build with CONFIG_DEBUG_RAM_SETUP on Intel 440BX, use printk().
It's a good thing to use printk() instead of print_*() anyway
on 440BX (and other chipsets which have been converted to CAR).
Build tested and boot-tested on ASUS P2B-LS.
Signed-off-by: Keith Hui <buurin@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6206
2b7e53f0-3cfb-0310-b3e9-
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Uwe Hermann [Mon, 20 Dec 2010 23:40:23 +0000 (23:40 +0000)]
Various Winbond/Nuvoton W83527HG fixes as per datasheet.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6205
2b7e53f0-3cfb-0310-b3e9-
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Stefan Reinauer [Sun, 19 Dec 2010 21:20:14 +0000 (21:20 +0000)]
The same mechanisms are used for normal and fallback images.
Hence drop the FALLBACK_ prefix
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6204
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Uwe Hermann [Sun, 19 Dec 2010 01:08:40 +0000 (01:08 +0000)]
ASUS M2N-E: Enable PCI-E x16 slot.
Simple devicetree.cb fix, tested on hardware using a PCI-E x16 graphics card.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6203
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Rudolf Marek [Sat, 18 Dec 2010 23:30:59 +0000 (23:30 +0000)]
SMM on AMD K8 Part 2/2
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6202
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Stefan Reinauer [Sat, 18 Dec 2010 23:29:37 +0000 (23:29 +0000)]
SMM for AMD K8 Part 1/2
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6201
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Uwe Hermann [Sat, 18 Dec 2010 13:22:37 +0000 (13:22 +0000)]
Fix a few whitespace and coding style issues.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6200
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Patrick Georgi [Sat, 18 Dec 2010 11:55:06 +0000 (11:55 +0000)]
A couple of Poulsbo fixes:
- Don't include cmc.bin to the build. It's required, but we don't ship it
- mptable's API changes a bit. Adapt.
- Fix ACPI for new iasl versions with improved code validation
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6199
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