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(parent: a112523) | patch
The code is tested on my board with register DIMMs. More tests need to be
authorZheng Bao <zheng.bao@amd.com>
Mon, 17 Jan 2011 02:20:33 +0000 (02:20 +0000)
committerZheng Bao <Zheng.Bao@amd.com>
Mon, 17 Jan 2011 02:20:33 +0000 (02:20 +0000)
commita7296e74f1c1bd33f2c19c498443955d674cfacb
tree75a93363813da5aeaad9951a474bda133a7786fetree | snapshot
parenta1125235ecc8c6ff9df1fd293de273111774345acommit | diff
The code is tested on my board with register DIMMs. More tests need to be
done. Please send the testing report.

Note: The pDCTstat->PresetmaxFreq in mctGet_MaxLoadFreq() should be set
to a higher limit, otherwise the frequnce will be set as 400MHz.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Scott Duplichan <scott@notabs.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6258 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
src/northbridge/amd/amdmct/mct_ddr3/mctwl.c diff | blob | history
src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c diff | blob | history
my coreboot WIP stuff (asus m5a99x-evo board)