unsigned long acpi_create_slic(unsigned long current);
#endif
-#include "southbridge/intel/i82801gx/nvs.h" // FIXME: our own copy of nvs would be nice
-static void acpi_create_gnvs(global_nvs_t *gnvs)
+#include "southbridge/intel/i82801gx/nvs.h" // FIXME: our own copy of nvs would be nice
+
+static void acpi_create_gnvs(global_nvs_t * gnvs)
{
memset((void *)gnvs, 0, sizeof(*gnvs));
gnvs->apic = 1;
- gnvs->mpen = 1; /* Enable Multi Processing */
+ gnvs->mpen = 1; /* Enable Multi Processing. */
- /* Enable both COM ports */
+ /* Enable both COM ports. */
gnvs->cmap = 0x01;
gnvs->cmbp = 0x01;
- /* IGD Displays */
+ /* IGD Displays. */
gnvs->ndid = 3;
gnvs->did[0] = 0x80000100;
gnvs->did[1] = 0x80000240;
gnvs->did[4] = 0x00000005;
}
-static void acpi_create_intel_hpet(acpi_hpet_t * hpet)
+static void acpi_create_intel_hpet(acpi_hpet_t *hpet)
{
#define HPET_ADDR 0xfed00000ULL
acpi_header_t *header = &(hpet->header);
acpi_addr_t *addr = &(hpet->addr);
- memset((void *) hpet, 0, sizeof(acpi_hpet_t));
+ memset((void *)hpet, 0, sizeof(acpi_hpet_t));
- /* fill out header fields */
+ /* Fill out header fields. */
memcpy(header->signature, "HPET", 4);
memcpy(header->oem_id, OEM_ID, 6);
memcpy(header->oem_table_id, "COREBOOT", 8);
header->length = sizeof(acpi_hpet_t);
header->revision = 1;
- /* fill out HPET address */
+ /* Fill out HPET address. */
addr->space_id = 0; /* Memory */
addr->bit_width = 64;
addr->bit_offset = 0;
hpet->number = 0x00;
hpet->min_tick = 0x0080;
- header->checksum =
- acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
+ header->checksum = acpi_checksum((void *)hpet, sizeof(acpi_hpet_t));
}
unsigned long acpi_fill_madt(unsigned long current)
/* IOAPIC */
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- 2, IO_APIC_ADDR, 0);
+ 2, IO_APIC_ADDR, 0);
/* INT_SRC_OVR */
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
+ current, 0, 0, 2, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
+ current, 0, 9, 9,
+ MP_IRQ_TRIGGER_LEVEL |
+ MP_IRQ_POLARITY_HIGH);
return current;
}
-unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
+unsigned long acpi_fill_ssdt_generator(unsigned long current,
+ const char *oem_table_id)
{
generate_cpu_entries();
- return (unsigned long) (acpigen_get_current());
+ return (unsigned long)(acpigen_get_current());
}
unsigned long acpi_fill_slit(unsigned long current)
{
- // Not implemented
+ /* Not implemented. */
return current;
}
{
unsigned long current;
int i;
+
acpi_rsdp_t *rsdp;
acpi_rsdt_t *rsdt;
acpi_xsdt_t *xsdt;
ALIGN_CURRENT;
/* clear all table memory */
- memset((void *) start, 0, current - start);
+ memset((void *)start, 0, current - start);
acpi_write_rsdp(rsdp, rsdt, xsdt);
acpi_write_rsdt(rsdt);
ALIGN_CURRENT;
/* Pack GNVS into the ACPI table area */
- for (i=0; i < dsdt->length; i++) {
- if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
- printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
- *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
+ for (i = 0; i < dsdt->length; i++) {
+ if (*(u32 *) (((u32) dsdt) + i) == 0xC0DEBABE) {
+ printk(BIOS_DEBUG, "ACPI: Patching up global NVS in "
+ "DSDT at offset 0x%04x -> 0x%08lx\n",
+ i, current);
+ *(u32 *) (((u32) dsdt) + i) = current; // 0x92 bytes
break;
}
}
/* And fill it */
- acpi_create_gnvs((global_nvs_t *)current);
+ acpi_create_gnvs((global_nvs_t *) current);
current += 0x100;
ALIGN_CURRENT;
dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt,
- dsdt->length);
+ dsdt->length);
#if CONFIG_HAVE_ACPI_SLIC
printk(BIOS_DEBUG, "ACPI: * SLIC\n");
- slic = (acpi_header_t *)current;
+ slic = (acpi_header_t *) current;
current += acpi_create_slic(current);
ALIGN_CURRENT;
acpi_add_table(rsdp, slic);
acpi_add_table(rsdp, fadt);
printk(BIOS_DEBUG, "ACPI: * SSDT\n");
- ssdt = (acpi_header_t *)current;
+ ssdt = (acpi_header_t *) current;
acpi_create_ssdt_generator(ssdt, "COREBOOT");
current += ssdt->length;
acpi_add_table(rsdp, ssdt);
#define DMI_TABLE_SIZE 0x55
static u8 dmi_table[DMI_TABLE_SIZE] = {
- 0x5f, 0x53, 0x4d, 0x5f, 0x2d, 0x1f, 0x02, 0x03, 0x51, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x5f, 0x44, 0x4d, 0x49, 0x5f, 0xeb, 0xa8, 0x03, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00,
- 0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00,
- 0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20,
- 0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32,
+ 0x5f, 0x53, 0x4d, 0x5f, 0x2d, 0x1f, 0x02, 0x03, 0x51, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x5f, 0x44, 0x4d, 0x49, 0x5f, 0xeb, 0xa8, 0x03, 0xa0, 0xff, 0x0f, 0x00,
+ 0x01, 0x00, 0x23, 0x00,
+ 0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde,
+ 0xcb, 0x7f, 0x00, 0x00,
+ 0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74,
+ 0x65, 0x6d, 0x73, 0x20,
+ 0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f,
+ 0x31, 0x33, 0x2f, 0x32,
0x30, 0x30, 0x38, 0x00, 0x00
};
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{
acpi_header_t *header = &(fadt->header);
- u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe;
+ u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
+ 0x40) & 0xfffe;
- memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+ memset((void *)fadt, 0, sizeof(acpi_fadt_t));
memcpy(header->signature, "FACP", 4);
- header->length = sizeof(acpi_fadt_t);
- header->revision = 3;
+ header->length = sizeof(acpi_fadt_t);
+ header->revision = 3;
memcpy(header->oem_id, "CORE ", 6);
memcpy(header->oem_table_id, "COREBOOT", 8);
memcpy(header->asl_compiler_id, "CORE", 4);
header->asl_compiler_revision = 1;
- fadt->firmware_ctrl = (unsigned long) facs;
- fadt->dsdt = (unsigned long) dsdt;
+ fadt->firmware_ctrl = (unsigned long)facs;
+ fadt->dsdt = (unsigned long)dsdt;
fadt->model = 1;
fadt->preferred_pm_profile = PM_MOBILE;
- fadt->sci_int = 0x9;
- fadt->smi_cmd = APM_CNT;
- fadt->acpi_enable = ACPI_ENABLE;
- fadt->acpi_disable = ACPI_DISABLE;
- fadt->s4bios_req = 0x0;
- fadt->pstate_cnt = PST_CONTROL;
+ fadt->sci_int = 0x9;
+ fadt->smi_cmd = APM_CNT;
+ fadt->acpi_enable = ACPI_ENABLE;
+ fadt->acpi_disable = ACPI_DISABLE;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = PST_CONTROL;
fadt->pm1a_evt_blk = pmbase;
fadt->pm1b_evt_blk = 0x0;
fadt->gpe0_blk_len = 8;
fadt->gpe1_blk_len = 0;
fadt->gpe1_base = 0;
- fadt->cst_cnt = CST_CONTROL;
+ fadt->cst_cnt = CST_CONTROL;
fadt->p_lvl2_lat = 1;
fadt->p_lvl3_lat = 85;
fadt->flush_size = 1024;
fadt->century = 0x00;
fadt->iapc_boot_arch = 0x03;
- fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
- ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
- ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
-
- fadt->reset_reg.space_id = 0;
- fadt->reset_reg.bit_width = 0;
- fadt->reset_reg.bit_offset = 0;
- fadt->reset_reg.resv = 0;
- fadt->reset_reg.addrl = 0x0;
- fadt->reset_reg.addrh = 0x0;
-
- fadt->reset_value = 0;
- fadt->x_firmware_ctl_l = (unsigned long)facs;
- fadt->x_firmware_ctl_h = 0;
- fadt->x_dsdt_l = (unsigned long)dsdt;
- fadt->x_dsdt_h = 0;
-
- fadt->x_pm1a_evt_blk.space_id = 1;
- fadt->x_pm1a_evt_blk.bit_width = 32;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
- fadt->x_pm1a_evt_blk.resv = 0;
- fadt->x_pm1a_evt_blk.addrl = pmbase;
- fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- fadt->x_pm1b_evt_blk.space_id = 1;
- fadt->x_pm1b_evt_blk.bit_width = 0;
- fadt->x_pm1b_evt_blk.bit_offset = 0;
- fadt->x_pm1b_evt_blk.resv = 0;
- fadt->x_pm1b_evt_blk.addrl = 0x0;
- fadt->x_pm1b_evt_blk.addrh = 0x0;
-
- fadt->x_pm1a_cnt_blk.space_id = 1;
- fadt->x_pm1a_cnt_blk.bit_width = 16;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
- fadt->x_pm1a_cnt_blk.resv = 0;
- fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
- fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- fadt->x_pm1b_cnt_blk.space_id = 1;
- fadt->x_pm1b_cnt_blk.bit_width = 0;
- fadt->x_pm1b_cnt_blk.bit_offset = 0;
- fadt->x_pm1b_cnt_blk.resv = 0;
- fadt->x_pm1b_cnt_blk.addrl = 0x0;
- fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
- fadt->x_pm2_cnt_blk.space_id = 1;
- fadt->x_pm2_cnt_blk.bit_width = 8;
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.resv = 0;
- fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
- fadt->x_pm2_cnt_blk.addrh = 0x0;
-
- fadt->x_pm_tmr_blk.space_id = 1;
- fadt->x_pm_tmr_blk.bit_width = 32;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.resv = 0;
- fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
- fadt->x_pm_tmr_blk.addrh = 0x0;
-
- fadt->x_gpe0_blk.space_id = 1;
- fadt->x_gpe0_blk.bit_width = 64;
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.resv = 0;
- fadt->x_gpe0_blk.addrl = pmbase + 0x28;
- fadt->x_gpe0_blk.addrh = 0x0;
-
- fadt->x_gpe1_blk.space_id = 1;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.resv = 0;
- fadt->x_gpe1_blk.addrl = 0x0;
- fadt->x_gpe1_blk.addrh = 0x0;
-
- header->checksum =
- acpi_checksum((void *) fadt, header->length);
+ fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+ ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+ ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
+
+ fadt->reset_reg.space_id = 0;
+ fadt->reset_reg.bit_width = 0;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.resv = 0;
+ fadt->reset_reg.addrl = 0x0;
+ fadt->reset_reg.addrh = 0x0;
+
+ fadt->reset_value = 0;
+ fadt->x_firmware_ctl_l = (unsigned long)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (unsigned long)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ fadt->x_pm1a_evt_blk.space_id = 1;
+ fadt->x_pm1a_evt_blk.bit_width = 32;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.resv = 0;
+ fadt->x_pm1a_evt_blk.addrl = pmbase;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = 1;
+ fadt->x_pm1b_evt_blk.bit_width = 0;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.resv = 0;
+ fadt->x_pm1b_evt_blk.addrl = 0x0;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1a_cnt_blk.space_id = 1;
+ fadt->x_pm1a_cnt_blk.bit_width = 16;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.resv = 0;
+ fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = 1;
+ fadt->x_pm1b_cnt_blk.bit_width = 0;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.resv = 0;
+ fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm2_cnt_blk.space_id = 1;
+ fadt->x_pm2_cnt_blk.bit_width = 8;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.resv = 0;
+ fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = 32;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.resv = 0;
+ fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ fadt->x_gpe0_blk.space_id = 1;
+ fadt->x_gpe0_blk.bit_width = 64;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.resv = 0;
+ fadt->x_gpe0_blk.addrl = pmbase + 0x28;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+ fadt->x_gpe1_blk.space_id = 1;
+ fadt->x_gpe1_blk.bit_width = 0;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.resv = 0;
+ fadt->x_gpe1_blk.addrl = 0x0;
+ fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum = acpi_checksum((void *)fadt, header->length);
}
*/
static u32 mainboard_cim_verb_data[] = {
- /* coreboot specific header */
- 0x111d76d5, // Codec Vendor / Device ID: IDT / 92HD81
- 0x00000000, // Subsystem ID
- 0x0000000a, // Number of jacks
+ /* coreboot specific header */
+ 0x111d76d5, // Codec Vendor / Device ID: IDT 92HD81
+ 0x00000000, // Subsystem ID
+ 0x0000000a, // Number of jacks
- //Codec 92HD81 Yangtze 4ch Pin Port A, data = 0x02a11040
+ /* NID 0x0a, Port A (capless headphone) */
0x0A71C40,
0x0A71D10,
0x0A71EA1,
0x0A71F02,
- //;Codec 92HD81 Yangtze 4ch Pin Port B, data = 0x0221101f
+ /* NID 0x0b, Port B (capless headphone) */
0x0B71C1F,
0x0B71D10,
0x0B71E21,
0x0B71F02,
- //;Codec 92HD81 Yangtze 4ch Pin Port C, data = 0x400000f0
+ /*
+ * NID 0x0c, Port C (Line IN/OUT+MIC for YD/UA revisions, and
+ * Line IN+MIC for TA revision)
+ */
0x0C71CF0,
0x0C71D00,
0x0C71E00,
0x0C71F40,
- //;Codec 92HD81 Yangtze 4ch Pin Port D, data = 0x10104110
+ /* NID 0x0d, Port D (BTL output - EAPD control) */
0x0D71C10,
0x0D71D41,
0x0D71E10,
0x0D71F10,
- //;Codec 92HD81 Yangtze 4ch Pin Port E, data = 0x400000f0
+ /* NID 0x0e, Port E (Line IN/OUT) */
0x0E71CF0,
0x0E71D00,
0x0E71E00,
0x0E71F40,
- //;Codec 92HD81 Yangtze 4ch Pin Port F, data = 0x400000f0
+ /* NID 0x0f, Port F (Line IN/OUT, MIC) */
0x0F71CF0,
0x0F71D00,
0x0F71E00,
0x0F71F40,
- //;Codec 92HD81 Yangtze 4ch Pin MonoOut, data = 0x40f000f0
+ /* NID 0x10, MonoOut (output-only) */
0x1071CF0,
0x1071D00,
0x1071EF0,
0x1071F40,
- //;Codec 92HD81 Yangtze 4ch Pin DMic0, data = 0x400000f0
+ /* NID 0x10, DigMic0 (Digital Microphone 0) */
0x1171CF0,
0x1171D00,
0x1171E00,
0x1171F40,
- //;Codec 92HD81 Yangtze 4ch Pin Dig0Pin, data = 0x10402150
+ /* NID 0x1f, Dig0Pin (First Digital Output Pin) */
0x1F71C50,
0x1F71D21,
0x1F71E40,
0x1F71F10,
- //;Codec 92HD81 Yangtze 4ch Pin Dig1Pin, data = 0x400000f0
+ /* NID 0x20, Dig1Pin (Second Digital Output Pin / DMIC Input Pin) */
0x2071CF0,
0x2071D00,
0x2071E00,
0x2071F40,
- //; BTL Gain
- 0x017F417
- // ; Gain = 16.79dB
+ /* BTL Gain */
+ 0x017F417, /* Gain = 16.79dB */
};
extern const u32 *cim_verb_data;
extern u32 cim_verb_data_size;
-
#include <arch/pirq_routing.h>
const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE, /* u32 signature */
- PIRQ_VERSION, /* u16 version */
- 32+16*CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */
- 0x00, /* Interrupt router bus */
- (0x1f << 3) | 0x0, /* Interrupt router dev */
- 0, /* IRQs devoted exclusively to PCI usage */
- 0x8086, /* Vendor */
- 0x8119, /* Device*/
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */
+ 0x00, /* Interrupt router bus */
+ (0x1f << 3) | 0x0, /* Interrupt router dev */
+ 0, /* IRQs devoted exclusively to PCI usage */
+ 0x8086, /* Vendor */
+ 0x8119, /* Device*/
0, /* Miniport */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0xdf, /* Checksum (has to be set to some value that
- * would give 0 after the sum of all bytes
- * for this structure (including checksum).
- */
- {
- /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00, (0x02 << 3) | 0x0, {{0x60, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
- {0x00, (0x1e << 3) | 0x0, {{0x60, 0x5cb8}, {0x61, 0x5cb8}, {0x62, 0x5cb8}, {0x00, 0x0000}}, 0x0, 0x0},
- {0x00, (0x1f << 3) | 0x0, {{0x62, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
- {0x00, (0x1a << 3) | 0x0, {{0x60, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
- {0x00, (0x1d << 3) | 0x0, {{0x64, 0x8200}, {0x65, 0x8200}, {0x66, 0x8200}, {0x67, 0x8200}}, 0x0, 0x0},
- {0x00, (0x1b << 3) | 0x0, {{0x60, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
- {0x00, (0x1c << 3) | 0x0, {{0x60, 0x5cb8}, {0x61, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
- {0x01, (0x00 << 3) | 0x0, {{0x60, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
- {0x02, (0x00 << 3) | 0x0, {{0x61, 0x5cb8}, {0x62, 0x5cb8}, {0x63, 0x5cb8}, {0x60, 0x5cb8}}, 0x2, 0x0},
- {0x00, (0x00 << 3) | 0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
- }
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0xdf, /* Checksum (has to be set to some value that
+ * would give 0 after the sum of all bytes
+ * for this structure (including checksum).
+ */
+ {
+ /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00, (0x02 << 3) | 0x0, {{0x60, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x00, (0x1e << 3) | 0x0, {{0x60, 0x5cb8}, {0x61, 0x5cb8}, {0x62, 0x5cb8}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x00, (0x1f << 3) | 0x0, {{0x62, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x00, (0x1a << 3) | 0x0, {{0x60, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x00, (0x1d << 3) | 0x0, {{0x64, 0x8200}, {0x65, 0x8200}, {0x66, 0x8200}, {0x67, 0x8200}}, 0x0, 0x0},
+ {0x00, (0x1b << 3) | 0x0, {{0x60, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x00, (0x1c << 3) | 0x0, {{0x60, 0x5cb8}, {0x61, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x01, (0x00 << 3) | 0x0, {{0x60, 0x5cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x02, (0x00 << 3) | 0x0, {{0x61, 0x5cb8}, {0x62, 0x5cb8}, {0x63, 0x5cb8}, {0x60, 0x5cb8}}, 0x2, 0x0},
+ {0x00, (0x00 << 3) | 0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ }
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
- return copy_pirq_routing_table(addr);
+ return copy_pirq_routing_table(addr);
}
-
CHIP_NAME("iW Rainbow G6 Mainboard")
.enable_dev = mainboard_enable,
};
-
#include <cpu/x86/smm.h>
#include "southbridge/intel/i82801gx/nvs.h" // FIXME: this should point to its own copy of nvs
-/* The southbridge SMI handler checks whether gnvs has a
- * valid pointer before calling the trap handler
+/*
+ * The southbridge SMI handler checks whether gnvs has a valid pointer before
+ * calling the trap handler.
*/
-//extern global_nvs_t *gnvs;
+// extern global_nvs_t *gnvs;
int mainboard_io_trap_handler(int smif)
{
switch (smif) {
case 0x99:
printk(BIOS_DEBUG, "Sample\n");
- //gnvs->smif = 0;
+ // gnvs->smif = 0;
break;
default:
return 0;
}
- /* On success, the IO Trap Handler returns 0
- * On failure, the IO Trap Handler returns a value != 0
+ /*
+ * On success, the IO Trap Handler returns 0.
+ * On failure, the IO Trap Handler returns a value != 0.
*
* For now, we force the return value to 0 and log all traps to
* see what's going on.
*/
- //gnvs->smif = 0;
+ // gnvs->smif = 0;
return 1;
}
-
-
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
+ * published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdint.h>
#include <string.h>
-
#include <arch/io.h>
#include <arch/romcc_io.h>
#include <device/pci_def.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/cache.h>
#include <arch/cpu.h>
-
#include <console/console.h>
#if 0
#include "ram/ramtest.c"
#include "southbridge/intel/sch/early_smbus.c"
#endif
-//#include "pc80/mc146818rtc_early.c"
-//#include "pc80/serial.c"
-
#define RFID_TEST 0
#if RFID_TEST
static u32 sch_SMbase_read(void)
{
u32 SMBusBase;
- SMBusBase = pci_read_config32(PCI_DEV(0, 0x1f, 0), 0x40); /*SM Bus Address */
+
+ /* SMBus address */
+ SMBusBase = pci_read_config32(PCI_DEV(0, 0x1f, 0), 0x40);
SMBusBase &= 0xFFFF;
- printk(BIOS_DEBUG, "SM Bus Base. =%x\r\n", SMBusBase);
+ printk(BIOS_DEBUG, "SMBus base = %x\r\n", SMBusBase);
return SMBusBase;
}
static void sch_SMbase_init(void)
{
u32 SMBusBase;
+
SMBusBase = sch_SMbase_read();
outb(0x3F, SMBusBase + SMBCLKDIV);
}
static void sch_SMbus_regs(void)
{
u32 SMBusBase;
+
SMBusBase = sch_SMbase_read();
printk(BIOS_DEBUG, "SMBHSTCNT. =%x\r\n", inb(SMBusBase + SMBHSTCNT));
printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n", inb(SMBusBase + SMBHSTSTS));
printk(BIOS_DEBUG, "SMBHSTCMD. =%x\r\n", inb(SMBusBase + SMBHSTCMD));
}
-void smb_clear()
+void smb_clear(void)
{
u32 SMBusBase;
+
SMBusBase = sch_SMbase_read();
outb(0x00, SMBusBase + SMBHSTCNT);
outb(0x07, SMBusBase + SMBHSTSTS);
}
-void data_clear()
+void data_clear(void)
{
u32 SMBusBase;
+
SMBusBase = sch_SMbase_read();
outb(0x00, SMBusBase + SMBHSTDAT0);
outb(0x00, SMBusBase + SMBHSTCMD);
{
int temp, a;
u32 SMBusBase;
+
SMBusBase = sch_SMbase_read();
printk(BIOS_DEBUG, "Transaction 1");
//clear the control and status registers
//check the status register for busy state
//sch_SMbus_regs ();
temp = inb(SMBusBase + SMBHSTSTS);
- //printk(BIOS_DEBUG, "SM Bus Busy.. status =%x\r\n",temp);
+ //printk(BIOS_DEBUG, "SMBus Busy.. status =%x\r\n",temp);
//printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n",inb(SMBusBase+SMBHSTSTS));
do {
temp = inb(SMBusBase + SMBHSTSTS);
- printk(BIOS_DEBUG, "SM Bus Busy.. status =%x\r\n", temp);
+ printk(BIOS_DEBUG, "SMBus Busy.. status =%x\r\n", temp);
//sch_SMbus_regs ();
printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n",
- inb(SMBusBase + SMBHSTSTS));
+ inb(SMBusBase + SMBHSTSTS));
if (temp > 0)
break;
} while (1);
switch (temp) {
case 1:
- printk(BIOS_DEBUG, "SM Bus Success");
+ printk(BIOS_DEBUG, "SMBus Success");
break;
default:
- printk(BIOS_DEBUG, "SM Bus error %d", temp);
+ printk(BIOS_DEBUG, "SMBus error %d", temp);
break;
}
sch_SMbus_regs();
printk(BIOS_DEBUG, "Command in TRansaction 1=%x\r\n\n",
- inb(SMBusBase + SMBHSTCMD));
+ inb(SMBusBase + SMBHSTCMD));
}
void transaction2(unsigned char dev_addr)
{
int temp, a;
u32 SMBusBase;
+
SMBusBase = sch_SMbase_read();
printk(BIOS_DEBUG, "Transaction 2");
//clear the control and status registers
//check the status register for busy state
//sch_SMbus_regs ();
temp = inb(SMBusBase + SMBHSTSTS);
- //printk(BIOS_DEBUG, "SM Bus Busy.. status =%x\r\n",temp);
+ //printk(BIOS_DEBUG, "SMBus Busy.. status =%x\r\n",temp);
//printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n",inb(SMBusBase+SMBHSTSTS));
do {
temp = inb(SMBusBase + SMBHSTSTS);
- printk(BIOS_DEBUG, "SM Bus Busy.. status =%x\r\n", temp);
+ printk(BIOS_DEBUG, "SMBus Busy.. status =%x\r\n", temp);
//sch_SMbus_regs ();
printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n",
- inb(SMBusBase + SMBHSTSTS));
+ inb(SMBusBase + SMBHSTSTS));
if (temp > 0)
break;
} while (1);
switch (temp) {
case 1:
- printk(BIOS_DEBUG, "SM Bus Success");
+ printk(BIOS_DEBUG, "SMBus Success");
break;
default:
- printk(BIOS_DEBUG, "SM Bus error %d", temp);
+ printk(BIOS_DEBUG, "SMBus error %d", temp);
break;
}
sch_SMbus_regs();
printk(BIOS_DEBUG, "Command in TRansaction 2=%x\r\n\n",
- inb(SMBusBase + SMBHSTCMD));
+ inb(SMBusBase + SMBHSTCMD));
}
void transaction3(unsigned char dev_addr)
{
int temp, index, length;
u32 SMBusBase;
+
SMBusBase = sch_SMbase_read();
printk(BIOS_DEBUG, "smb_read_multiple_bytes");
smb_clear();
// sch_SMbus_regs ();
//check the status register for busy state
//temp=inb(SMBusBase+SMBHSTSTS);
- //printk(BIOS_DEBUG, "SM Bus Busy.. status =%x\r\n",temp);
+ //printk(BIOS_DEBUG, "SMBus Busy.. status =%x\r\n",temp);
//sch_SMbus_regs ();
//printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n",inb(SMBusBase+SMBHSTSTS));
do {
temp = inb(SMBusBase + SMBHSTSTS);
printk(BIOS_DEBUG, "SMBHSTSTS. =%x\r\n",
- inb(SMBusBase + SMBHSTSTS));
+ inb(SMBusBase + SMBHSTSTS));
//sch_SMbus_regs ();
if (temp > 0)
break;
switch (temp) {
case 1:
- printk(BIOS_DEBUG, "SM Bus Success\n");
+ printk(BIOS_DEBUG, "SMBus Success\n");
break;
default:
- printk(BIOS_DEBUG, "SM Bus error %d", temp);
+ printk(BIOS_DEBUG, "SMBus error %d", temp);
break;
}
printk(BIOS_DEBUG, "Status .. %x\r\n", inb(SMBusBase + SMBHSTDATB + 1));
for (index = 0; index < length; index++)
printk(BIOS_DEBUG, "Serial Byte[%x]..%x\r\n", index,
- inb(SMBusBase + SMBHSTDATB + index));
+ inb(SMBusBase + SMBHSTDATB + index));
}
int selectcard(void)
{
int i;
+
printk(BIOS_DEBUG, "%s", "\r\nCase 9....... \n\r");
// send the length byte and command code through RFID interface
#include "northbridge/intel/sch/raminit.h"
#include "northbridge/intel/sch/raminit.c"
-
static void sch_enable_lpc(void)
{
/* Initialize the FWH decode/Enable registers according to platform design */
static void sch_shadow_CMC(void)
{
u32 reg32;
+
/* FIXME: proper dest, proper src, and wbinvd, too */
memcpy((void *)CMC_SHADOW, (void *)0xfffd0000, 64 * 1024);
// __asm__ volatile ("wbinvd \n"
reg32 = cpuid_eax(0x80000008);
printk(BIOS_INFO, "Physical Address size: %d.\n", (reg32 & 0xFF));
- printk(BIOS_INFO, "Virtual Address size: %d.\n", ((reg32 & 0xFF00) >> 8));
+ printk(BIOS_INFO, "Virtual Address size: %d.\n",
+ ((reg32 & 0xFF00) >> 8));
sch_port_access_write_ram_cmd(0xB8, 4, 0, 0x3faf0000);
printk(BIOS_DEBUG, "1 ");
sch_port_access_write_ram_cmd(0xBA, 4, 0, reg32);
static void poulsbo_setup_Stage2Regs(void)
{
u32 reg32;
+
printk(BIOS_DEBUG, "Reserved");
reg32 = pci_read_config32(PCI_DEV(0, 0x2, 0), 0x62);
pci_write_config32(PCI_DEV(0, 0x2, 0), 0x62, (reg32 | 0x3));
- /*Slot capabilities */
+ /* Slot capabilities */
pci_write_config32(PCI_DEV(0, 28, 0), 0x54, 0x80500);
pci_write_config32(PCI_DEV(0, 28, 1), 0x54, 0x100500);
/* FIXME: CPU ID identification */
{
int boot_mode = 0;
- if (bist == 0) {
+ if (bist == 0)
enable_lapic();
- }
sch_enable_lpc();
- /* Set up the console */
uart_init();
console_init();
/* Halt if there was a built in self test failure */
// report_bist_failure(bist);
- // outl (0x00,0x1088);
+ // outl (0x00, 0x1088);
- /* Perform some early chipset initialization required
- * before RAM initialization can work
+ /*
+ * Perform some early chipset initialization required
+ * before RAM initialization can work.
*/
sch_early_initialization();
sdram_initialize(boot_mode);
poulsbo_setup_Stage1Regs();
poulsbo_setup_Stage2Regs();
#if 0
- sch_SMbase_init ();
+ sch_SMbase_init();
- /* Perform some initialization that must run before stage2 */
+ /* Perform some initialization that must run before stage2. */
#endif
- /* This should probably go away. Until now it is required
- * and mainboard specific
+ /*
+ * This should probably go away. Until now it is required
+ * and mainboard specific.
*/
/* Chipset Errata! */
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
+ * published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <types.h>
if (!dev)
return current;
- pciexbar_reg=pci_read_config32(dev, 0x48);
+ pciexbar_reg = pci_read_config32(dev, 0x48);
- // MMCFG not supported or not enabled.
+ /* MMCFG not supported or not enabled. */
if (!(pciexbar_reg & (1 << 0)))
return current;
switch ((pciexbar_reg >> 1) & 3) {
- case 0: // 256MB
- pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
+ case 0: /* 256MB */
+ pciexbar = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
+ (1 << 28));
max_buses = 256;
break;
- case 1: // 128M
- pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
+ case 1: /* 128M */
+ pciexbar = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
+ (1 << 28) | (1 << 27));
max_buses = 128;
break;
- case 2: // 64M
- pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
+ case 2: /* 64M */
+ pciexbar = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
+ (1 << 28) | (1 << 27) | (1 << 26));
max_buses = 64;
break;
- default: // RSVD
+ default: /* RSVD */
return current;
}
if (!pciexbar)
return current;
+
#if CONFIG_GENERATE_ACPI_TABLES
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
- pciexbar, 0x0, 0x0, max_buses - 1);
+ pciexbar, 0x0, 0x0, max_buses - 1);
#endif
return current;
}
-
-
*/
#include "sch.h"
-#include "southbridge/intel/sch/sch.h"
+#include <southbridge/intel/sch/sch.h>
#if 0
-static void sch_set_mtrr (void)
+static void sch_set_mtrr(void)
{
msr_t msr;
printk(BIOS_DEBUG, "1");
msr.hi = 0x06060606;
msr.lo = 0x06060606;
- wrmsr (0x250, msr);
+ wrmsr(0x250, msr);
printk(BIOS_DEBUG, "2");
msr.hi = 0x06060606;
msr.lo = 0x06060606;
- wrmsr (0x258, msr);
+ wrmsr(0x258, msr);
printk(BIOS_DEBUG, "3");
msr.hi = 0x0;
msr.lo = 0x0;
- wrmsr (0x259, msr);
+ wrmsr(0x259, msr);
printk(BIOS_DEBUG, "4");
msr.hi = 0x04040404;
msr.lo = 0x04040404;
- wrmsr (0x268, msr);
+ wrmsr(0x268, msr);
printk(BIOS_DEBUG, "5");
msr.hi = 0x04040404;
msr.lo = 0x04040404;
- wrmsr (0x269, msr);
+ wrmsr(0x269, msr);
printk(BIOS_DEBUG, "6");
msr.hi = 0x04040404;
msr.lo = 0x04040404;
- wrmsr (0x26A, msr);
+ wrmsr(0x26A, msr);
printk(BIOS_DEBUG, "7");
msr.hi = 0x04040404;
msr.lo = 0x04040404;
- wrmsr (0x26B, msr);
+ wrmsr(0x26B, msr);
printk(BIOS_DEBUG, "8");
msr.hi = 0x04040404;
msr.lo = 0x04040404;
- wrmsr (0x26C, msr);
+ wrmsr(0x26C, msr);
printk(BIOS_DEBUG, "9");
msr.hi = 0x05050505;
msr.lo = 0x05050505;
- wrmsr (0x26D, msr);
+ wrmsr(0x26D, msr);
printk(BIOS_DEBUG, "10");
msr.hi = 0x05050505;
msr.lo = 0x05050505;
- wrmsr (0x26E, msr);
+ wrmsr(0x26E, msr);
printk(BIOS_DEBUG, "11");
msr.hi = 0x05050505;
msr.lo = 0x05050505;
- wrmsr (0x26f, msr);
+ wrmsr(0x26f, msr);
printk(BIOS_DEBUG, "12");
msr.hi = 0x0;
msr.lo = 0x6;
- wrmsr (0x202, msr);
+ wrmsr(0x202, msr);
printk(BIOS_DEBUG, "13");
msr.hi = 0x0;
msr.lo = 0xC0000800;
- wrmsr (0x203, msr);
+ wrmsr(0x203, msr);
printk(BIOS_DEBUG, "14");
msr.hi = 0x0;
msr.lo = 0x3FAF0000;
- wrmsr (0x204, msr);
+ wrmsr(0x204, msr);
printk(BIOS_DEBUG, "15");
msr.hi = 0x0;
msr.lo = 0xFFFF0800;
- wrmsr (0x205, msr);
+ wrmsr(0x205, msr);
printk(BIOS_DEBUG, "16");
msr.hi = 0x0;
msr.lo = 0x3FB00000;
- wrmsr (0x206, msr);
+ wrmsr(0x206, msr);
printk(BIOS_DEBUG, "16");
msr.hi = 0x0;
msr.lo = 0xFFF00800;
- wrmsr (0x207, msr);
+ wrmsr(0x207, msr);
printk(BIOS_DEBUG, "17");
msr.hi = 0x0;
msr.lo = 0x3FC00000;
- wrmsr (0x208, msr);
+ wrmsr(0x208, msr);
printk(BIOS_DEBUG, "18");
msr.hi = 0x0;
msr.lo = 0xFFC00800;
- wrmsr (0x209, msr);
+ wrmsr(0x209, msr);
printk(BIOS_DEBUG, "19");
msr.hi = 0x0;
msr.lo = 0x0;
- wrmsr (0x20A, msr);
+ wrmsr(0x20A, msr);
printk(BIOS_DEBUG, "20");
msr.hi = 0x0;
msr.lo = 0x0;
- wrmsr (0x20B, msr);
+ wrmsr(0x20B, msr);
printk(BIOS_DEBUG, "21");
msr.hi = 0x0;
msr.lo = 0x0;
- wrmsr (0x20a, msr);
+ wrmsr(0x20a, msr);
printk(BIOS_DEBUG, "22");
msr.hi = 0x0;
msr.lo = 0x0;
- wrmsr (0x20B, msr);
+ wrmsr(0x20B, msr);
printk(BIOS_DEBUG, "23");
msr.hi = 0x0;
msr.lo = 0x0;
- wrmsr (0x20c, msr);
+ wrmsr(0x20c, msr);
msr.hi = 0x0;
msr.lo = 0x0;
- wrmsr (0x20d, msr);
+ wrmsr(0x20d, msr);
msr.hi = 0x0;
msr.lo = 0x0;
- wrmsr (0x20E, msr);
+ wrmsr(0x20E, msr);
msr.hi = 0x0;
msr.lo = 0x0;
- wrmsr (0x20F, msr);
+ wrmsr(0x20F, msr);
msr.hi = 0x0;
msr.lo = 0XC00;
- wrmsr (0x2FF, msr);
+ wrmsr(0x2FF, msr);
printk(BIOS_DEBUG, "end");
}
#endif
static void sch_detect_chipset(void)
{
u16 reg16;
- u8 reg8;
+ u8 reg8;
printk(BIOS_INFO, "\n");
reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), 0x2);
- switch (reg16)
- {
- case 0x8101:
- printk(BIOS_INFO, "UL11L/US15L");
- break;
- case 0x8100:
- printk(BIOS_INFO, "US15W");
- break;
- default:
- printk(BIOS_INFO, "Unknown (%02x)", reg16); /* Others reserved. */
+ switch (reg16) {
+ case 0x8101:
+ printk(BIOS_INFO, "UL11L/US15L");
+ break;
+ case 0x8100:
+ printk(BIOS_INFO, "US15W");
+ break;
+ default:
+ /* Others reserved. */
+ printk(BIOS_INFO, "Unknown (%02x)", reg16);
}
printk(BIOS_INFO, " Chipset\n");
-
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0x8);
- switch (reg8)
- {
- case 3:
- printk(BIOS_INFO, "Qual. Sample ES1, Stepping B1");
- break;
- case 4:
- printk(BIOS_INFO, "Qual. Sample ES2, Stepping C0");
- break;
- case 5:
- printk(BIOS_INFO, "Qual. Sample ES2-Prime, Stepping D0");
- break;
- case 6:
- printk(BIOS_INFO, "Qual. Sample QS, Stepping D1");
- break;
-
- default:
- printk(BIOS_INFO, "Unknown (%02x)", reg8); /* Others reserved. */
+ switch (reg8) {
+ case 3:
+ printk(BIOS_INFO, "Qual. Sample ES1, Stepping B1");
+ break;
+ case 4:
+ printk(BIOS_INFO, "Qual. Sample ES2, Stepping C0");
+ break;
+ case 5:
+ printk(BIOS_INFO, "Qual. Sample ES2-Prime, Stepping D0");
+ break;
+ case 6:
+ printk(BIOS_INFO, "Qual. Sample QS, Stepping D1");
+ break;
+ default:
+ /* Others reserved. */
+ printk(BIOS_INFO, "Unknown (%02x)", reg8);
}
-
}
static void sch_setup_non_standard_bars(void)
{
printk(BIOS_DEBUG, "Setting up ACPI PM1 block ");
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x48, (0x80000000 |DEFAULT_PMBASE)); /*Address 1000 size 16B*/
+ /* Address 0x1000 size 16B */
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x48,
+ (0x80000000 | DEFAULT_PMBASE));
+
printk(BIOS_DEBUG, "Setting up ACPI P block ");
- sch_port_access_write(4,0x70,4,0x80001010);/*Address 1010 size 16B*/
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x40, 0x80001040); /*SM Bus Address 1040 size 64B*/
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x44, 0x80001080); /*GPIO Address 1080 size 64B*/
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x4C, 0x800010C0); /*GPE0 Address 10C0 size 64B*/
- sch_port_access_write(2,4,4,0x3F703F76); /* FIXME: SMM Control */
- pci_write_config32(PCI_DEV(0, 0x02, 0), 0x5C, 0x3F800000); /*Base of Stolen memory Address 1080 size 64B*/
-
- sch_port_access_write(0,0,4, DEFAULT_PCIEXBAR | 1); // pre-b1
- sch_port_access_write(2,9,4, DEFAULT_PCIEXBAR | 1); // b1+
-
- /*RCBA*/
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xF0, (DEFAULT_RCBABASE| 1 ));
- printk(BIOS_DEBUG, " done.\n");
+ /* Address 0x1010 size 16B */
+ sch_port_access_write(4, 0x70, 4, 0x80001010);
+
+ /* SMBus address 0x1040 size 64B */
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x40, 0x80001040);
+
+ /* GPIO address 0x1080 size 64B */
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x44, 0x80001080);
+ /* GPE0 address 0x10C0 size 64B */
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x4C, 0x800010C0);
+
+ sch_port_access_write(2, 4, 4, 0x3F703F76); /* FIXME: SMM Control */
+
+ /* Base of Stolen Memory Address 0x1080 size 64B */
+ pci_write_config32(PCI_DEV(0, 0x02, 0), 0x5C, 0x3F800000);
+
+ sch_port_access_write(0, 0, 4, DEFAULT_PCIEXBAR | 1); /* pre-b1 */
+ sch_port_access_write(2, 9, 4, DEFAULT_PCIEXBAR | 1); /* b1+ */
+
+ /* RCBA */
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xF0, (DEFAULT_RCBABASE | 1));
+
+ printk(BIOS_DEBUG, " done.\n");
}
static void sch_early_initialization(void)
{
- /* Print some chipset specific information */
+ /* Print some chipset specific information. */
sch_detect_chipset();
- /* Setup all non standard BARs */
+ /* Setup all non standard BARs. */
sch_setup_non_standard_bars();
}
{
u32 reg32;
- /* IGD needs to be Bus Master */
+ /* IGD needs to be bus master. */
reg32 = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
- pci_read_config32(dev, PCI_VENDOR_ID));
+ pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations gma_pci_ops = {
- .set_subsystem = gma_set_subsystem,
+ .set_subsystem = gma_set_subsystem,
};
static struct device_operations gma_func0_ops = {
.ops_pci = &gma_pci_ops,
};
-
static const struct pci_driver sch_gma_func0_driver __pci_driver = {
.ops = &gma_func0_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x8108,
};
-
if (!dev)
return 0;
- // FIXME: determine at runtime
+ /* FIXME: Determine at runtime. */
#ifdef POULSBO_PRE_B1
- pciexbar_reg = sch_port_access_read(0,0,4);
+ pciexbar_reg = sch_port_access_read(0, 0, 4);
#else
- pciexbar_reg = sch_port_access_read(2,9,4);
+ pciexbar_reg = sch_port_access_read(2, 9, 4);
#endif
if (!(pciexbar_reg & (1 << 0)))
return 0;
switch ((pciexbar_reg >> 1) & 3) {
- case 0: // 256MB
- *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
+ case 0: /* 256MB */
+ *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
+ (1 << 28));
*len = 256 * 1024 * 1024;
return 1;
- case 1: // 128M
- *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
+ case 1: /* 128M */
+ *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
+ (1 << 28) | (1 << 27));
*len = 128 * 1024 * 1024;
return 1;
- case 2: // 64M
- *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
+ case 2: /* 64M */
+ *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
+ (1 << 28) | (1 << 27) | (1 << 26));
*len = 64 * 1024 * 1024;
return 1;
}
}
/* IDG memory */
-uint64_t uma_memory_base=0, uma_memory_size=0;
+u64 uma_memory_base = 0, uma_memory_size = 0;
static void add_fixed_resources(struct device *dev, int index)
{
if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
printk(BIOS_DEBUG, "Adding PCIe config bar\n");
- resource = new_resource(dev, index+1);
+ resource = new_resource(dev, index + 1);
resource->base = (resource_t) pcie_config_base;
resource->size = (resource_t) pcie_config_size;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
}
printk(BIOS_DEBUG, "Adding CMC shadow area\n");
- resource = new_resource(dev, index+1);
+ resource = new_resource(dev, index + 1);
resource->base = (resource_t) CMC_SHADOW;
resource->size = (resource_t) (64 * 1024);
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
-
#if CONFIG_WRITE_HIGH_TABLES==1
#include <cbmem.h>
#endif
static void pci_domain_set_resources(device_t dev)
{
- uint32_t pci_tolm;
- uint8_t reg8;
- uint16_t reg16;
+ u32 pci_tolm;
+ u8 reg8;
+ u16 reg16;
unsigned long long tomk, tolud;
- /* Can we find out how much memory we can use at most
- * this way?
- */
+
+ /* Can we find out how much memory we can use at most this way? */
pci_tolm = find_pci_tolm(dev->link_list);
printk(BIOS_DEBUG, "pci_tolm: 0x%x\n", pci_tolm);
printk(BIOS_SPEW, "Base of stolen memory: 0x%08x\n",
- pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c));
+ pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c));
tolud = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9c);
- printk(BIOS_SPEW, "Top of Low Used DRAM: 0x%08llx\n", tolud << 24);
+ printk(BIOS_SPEW, "Top of Low Used DRAM: 0x%08llx\n", tolud << 24);
- tomk = tolud << 14;
+ tomk = tolud << 14;
- /* Note: subtract IGD device and TSEG */
+ /* Note: subtract IGD device and TSEG. */
reg8 = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9e);
- if (reg8 & 1)
- {
+ if (reg8 & 1) {
int tseg_size = 0;
printk(BIOS_DEBUG, "TSEG decoded, subtracting ");
reg8 >>= 1;
reg8 &= 3;
switch (reg8) {
case 0:
- tseg_size = 1024;
- break; /* TSEG = 1M */
+ tseg_size = 1024; /* TSEG = 1M */
+ break;
case 1:
- tseg_size = 2048;
- break; /* TSEG = 2M */
+ tseg_size = 2048; /* TSEG = 2M */
+ break;
case 2:
- tseg_size = 8192;
- break; /* TSEG = 8M */
+ tseg_size = 8192; /* TSEG = 8M */
+ break;
}
printk(BIOS_DEBUG, "%dM\n", tseg_size >> 10);
}
reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC);
- if (!(reg16 & 2))
- {
+ if (!(reg16 & 2)) {
int uma_size = 0;
printk(BIOS_DEBUG, "IGD decoded, subtracting ");
reg16 >>= 4;
reg16 &= 7;
- switch (reg16)
- {
- case 1:
- uma_size = 1024;
- break;
- case 2:
- uma_size = 4096;
- break;
- case 3:
- uma_size = 8192;
- break;
+ switch (reg16) {
+ case 1:
+ uma_size = 1024;
+ break;
+ case 2:
+ uma_size = 4096;
+ break;
+ case 3:
+ uma_size = 8192;
+ break;
}
printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10);
tomk -= uma_size;
- /* For reserving UMA memory in the memory map */
+ /* For reserving UMA memory in the memory map. */
uma_memory_base = tomk * 1024ULL;
uma_memory_size = uma_size * 1024ULL;
}
- /* The following needs to be 2 lines, otherwise the second
- * number is always 0
+ /*
+ * The following needs to be 2 lines, otherwise the second
+ * number is always 0.
*/
- printk(BIOS_INFO, "Available memory: %dK", (uint32_t)tomk);
- printk(BIOS_INFO, " (%dM)\n", (uint32_t)(tomk >> 10));
+ printk(BIOS_INFO, "Available memory: %dK", (u32) tomk);
+ printk(BIOS_INFO, " (%dM)\n", (u32) (tomk >> 10));
- /* Report the memory regions */
+ /* Report the memory regions. */
ram_resource(dev, 3, 0, 640);
ram_resource(dev, 4, 768, (tomk - 768));
- if (tomk > 4 * 1024 * 1024) {
+ if (tomk > 4 * 1024 * 1024)
ram_resource(dev, 5, 4096 * 1024, tomk - 4 * 1024 * 1024);
- }
add_fixed_resources(dev, 6);
assign_resources(dev->link_list);
#if CONFIG_WRITE_HIGH_TABLES==1
- /* Leave some space for ACPI, PIRQ and MP tables */
+ /* Leave some space for ACPI, PIRQ and MP tables. */
high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
high_tables_size = HIGH_MEMORY_SIZE;
#endif
}
- /* TODO We could determine how many PCIe busses we need in
- * the bar. For now that number is hardcoded to a max of 64.
- * See e7525/northbridge.c for an example.
- */
+/*
+ * TODO: We could determine how many PCIe busses we need in the bar. For now
+ * that number is hardcoded to a max of 64.
+ * See e7525/northbridge.c for an example.
+ */
static struct device_operations pci_domain_ops = {
- .read_resources = pci_domain_read_resources,
- .set_resources = pci_domain_set_resources,
- .enable_resources = NULL,
- .init = NULL,
- .scan_bus = pci_domain_scan_bus,
+ .read_resources = pci_domain_read_resources,
+ .set_resources = pci_domain_set_resources,
+ .enable_resources = NULL,
+ .init = NULL,
+ .scan_bus = pci_domain_scan_bus,
#if CONFIG_MMCONF_SUPPORT_DEFAULT
- .ops_pci_bus = &pci_ops_mmconf,
+ .ops_pci_bus = &pci_ops_mmconf,
#else
- .ops_pci_bus = &pci_cf8_conf1,
+ .ops_pci_bus = &pci_cf8_conf1,
#endif
};
pci_dev_read_resources(dev);
- /* So, this is one of the big mysteries in the coreboot resource
+ /*
+ * So, this is one of the big mysteries in the coreboot resource
* allocator. This resource should make sure that the address space
* of the PCIe memory mapped config space bar. But it does not.
*/
- /* We use 0xcf as an unused index for our PCIe bar so that we find it again */
+ /*
+ * We use 0xcf as an unused index for our PCIe bar so that we find
+ * it again.
+ */
resource = new_resource(dev, 0xcf);
- resource->flags =
- IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
- IORESOURCE_ASSIGNED;
- get_pcie_bar((u32*)&resource->base, (u32*)&resource->size);
- printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n",
- (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size));
+ resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
+ IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+ get_pcie_bar((u32 *)&resource->base, (u32 *)&resource->size);
+ printk(BIOS_DEBUG,
+ "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n",
+ (unsigned long)(resource->base),
+ (unsigned long)(resource->base + resource->size));
}
static void mc_set_resources(device_t dev)
{
struct resource *resource;
- /* Report the PCIe BAR */
+ /* Report the PCIe BAR. */
resource = find_resource(dev, 0xcf);
- if (resource) {
+ if (resource)
report_resource_stored(dev, resource, "<mmconfig>");
- }
- /* And call the normal set_resources */
+ /* And call the normal set_resources. */
pci_dev_set_resources(dev);
}
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
- pci_read_config32(dev, PCI_VENDOR_ID));
+ pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
switch (pci_read_config32(dev, SKPAD)) {
case 0xcafebabe:
printk(BIOS_DEBUG, "Normal boot.\n");
- acpi_slp_type=0;
+ acpi_slp_type = 0;
break;
case 0xcafed00d:
printk(BIOS_DEBUG, "S3 Resume.\n");
- acpi_slp_type=3;
+ acpi_slp_type = 3;
break;
default:
printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n");
- acpi_slp_type=0;
+ acpi_slp_type = 0;
break;
}
}
#endif
static struct pci_operations intel_pci_ops = {
- .set_subsystem = intel_set_subsystem,
+ .set_subsystem = intel_set_subsystem,
};
static struct device_operations mc_ops = {
- .read_resources = mc_read_resources,
- .set_resources = mc_set_resources,
- .enable_resources = pci_dev_enable_resources,
+ .read_resources = mc_read_resources,
+ .set_resources = mc_set_resources,
+ .enable_resources = pci_dev_enable_resources,
#if CONFIG_HAVE_ACPI_RESUME
- .init = northbridge_init,
+ .init = northbridge_init,
#endif
- .scan_bus = 0,
- .ops_pci = &intel_pci_ops,
+ .scan_bus = 0,
+ .ops_pci = &intel_pci_ops,
};
static const struct pci_driver mc_driver __pci_driver = {
- .ops = &mc_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x8100,
+ .ops = &mc_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = 0x8100,
};
static void cpu_bus_init(device_t dev)
}
static struct device_operations cpu_bus_ops = {
- .read_resources = cpu_bus_noop,
- .set_resources = cpu_bus_noop,
- .enable_resources = cpu_bus_noop,
- .init = cpu_bus_init,
- .scan_bus = 0,
+ .read_resources = cpu_bus_noop,
+ .set_resources = cpu_bus_noop,
+ .enable_resources = cpu_bus_noop,
+ .init = cpu_bus_init,
+ .scan_bus = 0,
};
static void enable_dev(device_t dev)
{
- /* Set the operations if it is a special bus type */
+ /* Set the operations if it is a special bus type. */
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
dev->ops = &pci_domain_ops;
} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
*/
typedef struct {
- u16 osys;
- u8 smif;
- u8 prm0;
- u8 prm1;
- u8 scif;
- u8 prm2;
- u8 prm3;
- u8 lckf;
- u8 prm4;
- u8 prm5;
- u32 p80d;
- u8 lids;
- u8 pwrs;
- u8 dbgs;
- u8 linxs;
- u8 rsvd;
- u8 actt;
- u8 psvt;
- u8 tc1v;
- u8 tc2v;
- u8 tspv;
- u8 crtt;
- u8 dtse;
- u8 dts1;
- u8 dts2;
- u8 rsvd2;
- u8 bnum;
- u8 b0sc, b1sc, b2sc;
- u8 b0ss, b1ss, b2ss;
- u8 rsvd3[3];
- u8 apic;
- u8 mpen;
- u8 bten;
- u8 ppcm;
- u8 pcp0;
- u8 pcp1;
- u8 rsvd4[4];
- u8 natp;
- u8 cmap;
- u8 cmbp;
- u8 lptp;
- u8 fdcp;
- u8 rfdv;
- u8 hotk;
- u8 rtcf;
- u8 util;
- u8 acin;
- u8 igds;
- u8 tlst;
- u8 cadl;
- u8 padl;
- u16 cste;
- u16 pste;
- u16 nste;
- u16 sste;
- u8 ndid;
- u32 did1;
- u32 did2;
- u32 did3;
- u32 did4;
- u32 did5;
- u8 rsvd5[0xb];
- u8 brtl;
- u8 odds;
- u8 alse;
- u8 alaf;
- u8 llow;
- u8 lhih;
- u8 rsvd6;
- u8 emae;
- u16 emap;
- u16 emal;
- u8 rsvd7;
- u8 mefe;
- u8 igps;
- u8 rsvd8[2];
- u8 tpmp;
- u8 tpme;
- u8 rsvd9[8];
- u8 gtf0[7];
- u8 gtf2[7];
- u8 idem;
- u8 idet;
- u8 dock;
+ u16 osys;
+ u8 smif;
+ u8 prm0;
+ u8 prm1;
+ u8 scif;
+ u8 prm2;
+ u8 prm3;
+ u8 lckf;
+ u8 prm4;
+ u8 prm5;
+ u32 p80d;
+ u8 lids;
+ u8 pwrs;
+ u8 dbgs;
+ u8 linxs;
+ u8 rsvd;
+ u8 actt;
+ u8 psvt;
+ u8 tc1v;
+ u8 tc2v;
+ u8 tspv;
+ u8 crtt;
+ u8 dtse;
+ u8 dts1;
+ u8 dts2;
+ u8 rsvd2;
+ u8 bnum;
+ u8 b0sc, b1sc, b2sc;
+ u8 b0ss, b1ss, b2ss;
+ u8 rsvd3[3];
+ u8 apic;
+ u8 mpen;
+ u8 bten;
+ u8 ppcm;
+ u8 pcp0;
+ u8 pcp1;
+ u8 rsvd4[4];
+ u8 natp;
+ u8 cmap;
+ u8 cmbp;
+ u8 lptp;
+ u8 fdcp;
+ u8 rfdv;
+ u8 hotk;
+ u8 rtcf;
+ u8 util;
+ u8 acin;
+ u8 igds;
+ u8 tlst;
+ u8 cadl;
+ u8 padl;
+ u16 cste;
+ u16 pste;
+ u16 nste;
+ u16 sste;
+ u8 ndid;
+ u32 did1;
+ u32 did2;
+ u32 did3;
+ u32 did4;
+ u32 did5;
+ u8 rsvd5[0xb];
+ u8 brtl;
+ u8 odds;
+ u8 alse;
+ u8 alaf;
+ u8 llow;
+ u8 lhih;
+ u8 rsvd6;
+ u8 emae;
+ u16 emap;
+ u16 emal;
+ u8 rsvd7;
+ u8 mefe;
+ u8 igps;
+ u8 rsvd8[2];
+ u8 tpmp;
+ u8 tpme;
+ u8 rsvd9[8];
+ u8 gtf0[7];
+ u8 gtf2[7];
+ u8 idem;
+ u8 idet;
+ u8 dock;
} global_nvs_t;
-
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
+ * published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* | Data |
* | |
* ----------------------------------------------------------------------------
- *
*/
+
#define MSG_OPCODE_READ 0xD0000000
#define MSG_OPCODE_WRITE 0xE0000000
#define MCR 0xD0
#define MDR 0xD4
-int sch_port_access_read(int port,int reg, int bytes)
+int sch_port_access_read(int port, int reg, int bytes)
{
- pci_write_config32(PCI_DEV(0, 0, 0), MCR, (MSG_OPCODE_READ |(port <<16) | (reg << 8) ));
+ pci_write_config32(PCI_DEV(0, 0, 0), MCR,
+ (MSG_OPCODE_READ | (port << 16) | (reg << 8)));
return pci_read_config32(PCI_DEV(0, 0, 0), MDR);
}
-void sch_port_access_write(int port,int reg,int bytes,long data)
+void sch_port_access_write(int port, int reg, int bytes, long data)
{
- pci_write_config32(PCI_DEV(0, 0, 0), MDR,data);
- pci_write_config32(PCI_DEV(0, 0, 0), MCR, (MSG_OPCODE_WRITE |(port <<16) | (reg << 8) ));
+ pci_write_config32(PCI_DEV(0, 0, 0), MDR, data);
+ pci_write_config32(PCI_DEV(0, 0, 0), MCR,
+ (MSG_OPCODE_WRITE | (port << 16) | (reg << 8)));
pci_read_config32(PCI_DEV(0, 0, 0), MDR);
}
-void sch_port_access_write_ram_cmd(int cmd,int port,int reg,int data)
+void sch_port_access_write_ram_cmd(int cmd, int port, int reg, int data)
{
-
- pci_write_config32(PCI_DEV(0, 0, 0), MDR,data);
- pci_write_config32(PCI_DEV(0, 0, 0), MCR, ((cmd << 24) |(port <<16) | (reg << 8)));
+ pci_write_config32(PCI_DEV(0, 0, 0), MDR, data);
+ pci_write_config32(PCI_DEV(0, 0, 0), MCR,
+ ((cmd << 24) | (port << 16) | (reg << 8)));
pci_read_config32(PCI_DEV(0, 0, 0), MDR);
}
-
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
+ * published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
#include <spd.h>
#include "raminit.h"
#include "sch.h"
+
#define DEBUG_RAM_SETUP
#define SOFTSTRSP(base, off) *((volatile u8 *)((base) + (off)))
static void detect_fsb(struct sys_info *sysinfo)
{
u32 reg32;
+
reg32 = sch_port_access_read(5, 3, 4);
- if (reg32 & BIT(3)) {
+ if (reg32 & BIT(3))
sysinfo->fsb_frequency = 533;
- } else {
+ else
sysinfo->fsb_frequency = 400;
- }
}
static u32 detect_softstrap_base(void)
{
u32 reg32, base_addr;
+
reg32 = sch_port_access_read(4, 0x71, 2);
reg32 &= 0x700;
reg32 = reg32 >> 7;
sysinfo->ranks = reg8;
if (reg8 == 0) {
sysinfo->ram_param_source = RAM_PARAM_SOURCE_SPD;
- /* FIXME: implement SPD reading */
- die("no support for reading DIMM config from SPD yet!");
+ /* FIXME: Implement SPD reading. */
+ die("No support for reading DIMM config from SPD yet!");
return;
} else {
sysinfo->ram_param_source = RAM_PARAM_SOURCE_SOFTSTRAP;
- /*Timings from soft strap */
+ /* Timings from soft strap */
reg8 = SOFTSTRSP(sbase, 0x87f0);
temp = reg8 & 0x30;
temp = temp >> 4;
temp = reg8 & 0x03;
sysinfo->trp = temp;
- /*Geometry from Softstrap */
+ /* Geometry from Softstrap */
reg8 = SOFTSTRSP(sbase, 0x87f1);
temp = reg8 & 0x06;
temp = reg8 & 0x01;
sysinfo->data_width = temp;
- /*Refresh rate default 7.8us */
+ /* Refresh rate default 7.8us */
sysinfo->refresh = 3;
}
}
{
u32 reg32;
- /* Program DRP DRAM Rank Population and Interface Register
- * as per data in sysinfo SCH port 1 register 0 .. 0XFF
+ /*
+ * Program DRP DRAM Rank Population and Interface Register as per data
+ * in sysinfo SCH port 1 register 0..0xFF.
*/
- reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DRP, 4);
- reg32 &= ~(DRP_FIELDS); /* Clear all DRP fields we'll change */
+ reg32 =
+ sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DRP, 4);
+ reg32 &= ~(DRP_FIELDS); /* Clear all DRP fields we'll change. */
/* Rank0 Device Width, Density, Enable */
- reg32 |= (sysinfo->data_width) | ((sysinfo->device_density) << 1) | (1 << 3);
+ reg32 |= sysinfo->data_width | (sysinfo->device_density << 1) | (1 << 3);
/* Rank1 Device Width, Density, Enable */
- reg32 |= (sysinfo->data_width << 4) | ((sysinfo->device_density) << 5) | (1 << 7);
- sch_port_access_write(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DRP, 4, reg32);
+ reg32 |= (sysinfo->data_width << 4)
+ | ((sysinfo->device_density) << 5) | (1 << 7);
+ sch_port_access_write(SCH_MSG_DUNIT_PORT,
+ SCH_MSG_DUNIT_REG_DRP, 4, reg32);
/*
- Program DTR DRAM Timing Register as per data in sysinfo SCH port 1 register 1
- tRD_dly = 2 (15:13 = 010b)
- 0X3F
- */
- reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DTR, 4);
- reg32 &= ~(DTR_FIELDS); /* Clear all DTR fields we'll change */
+ * Program DTR DRAM Timing Register as per data in sysinfo SCH port 1
+ * register 1.
+ *
+ * tRD_dly = 2 (15:13 = 010b)
+ * 0X3F
+ */
+ reg32 =
+ sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DTR, 4);
+ reg32 &= ~(DTR_FIELDS); /* Clear all DTR fields we'll change. */
reg32 = (sysinfo->trp);
reg32 |= (sysinfo->trcd) << 2;
reg32 |= (sysinfo->cl) << 4;
reg32 |= 0X4000; /* tRD_dly = 2 (15:13 = 010b) */
- sch_port_access_write(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DTR, 4, reg32);
-
+ sch_port_access_write(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DTR, 4,
+ reg32);
- /* DCO DRAM Controller Operation Register as per data in sysinfo SCH port 1 register 2 0XF */
- reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DCO, 4);
- reg32 &= ~(DCO_FIELDS); /*Clear all DTR fields we'll change */
+ /*
+ * DCO DRAM Controller Operation Register as per data in sysinfo
+ * SCH port 1 register 2 0xF.
+ */
+ reg32 =
+ sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DCO, 4);
+ reg32 &= ~(DCO_FIELDS); /* Clear all DTR fields we'll change. */
- if (sysinfo->fsb_frequency == 533) {
+ if (sysinfo->fsb_frequency == 533)
reg32 |= 1;
- } else {
+ else
reg32 &= ~(BIT(0));
- }
- reg32 = 0x006911c; // FIXME ?
+ reg32 = 0x006911c; // FIXME ?
- sch_port_access_write(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DCO, 4, reg32);
+ sch_port_access_write(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DCO, 4,
+ reg32);
}
static void program_dll_config(struct sys_info *sysinfo)
sch_port_access_write(SCH_MSG_DUNIT_PORT, 0x22, 4, 0x58585858);
}
sch_port_access_write(SCH_MSG_DUNIT_PORT, 0x23, 4, 0x2222);
- if (sysinfo->fsb_frequency == 533) {
+ if (sysinfo->fsb_frequency == 533)
sch_port_access_write(SCH_MSG_DUNIT_PORT, 0x20, 4, 0x993B);
- } else {
+ else
sch_port_access_write(SCH_MSG_DUNIT_PORT, 0x20, 4, 0xCC3B);
- }
}
static void do_jedec_init(struct sys_info *sysinfo)
{
u32 reg32, rank, cmd, temp, num_ranks;
+
/* Performs JEDEC memory initializattion for all memory rows */
/* Set CKE0/1 low */
- reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DRP, 4);
+ reg32 =
+ sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DRP, 4);
reg32 |= DRP_CKE_DIS;
- sch_port_access_write(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DRP, 4, reg32);
- reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DRP, 4);
+ sch_port_access_write(SCH_MSG_DUNIT_PORT,
+ SCH_MSG_DUNIT_REG_DRP, 4, reg32);
+ reg32 =
+ sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DRP, 4);
rank = 0;
num_ranks = sysinfo->ranks;
- do {
+ do {
/* Start clocks */
- reg32 =
- sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DRP, 4);
- reg32 &= ~(DRP_SCK_DIS); /* Enable all SCK/SCKB by def. */
+ reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT,
+ SCH_MSG_DUNIT_REG_DRP, 4);
+ reg32 &= ~(DRP_SCK_DIS); /* Enable all SCK/SCKB by def. */
sch_port_access_write(1, SCH_MSG_DUNIT_REG_DRP, 4, reg32);
- /* Program miscellaneous SCH registers on rank 0 initialization */
- reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DRP, 4);
- if (rank == 0) {
+ /* Program misc. SCH registers on rank 0 initialization. */
+ reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT,
+ SCH_MSG_DUNIT_REG_DRP, 4);
+ if (rank == 0)
program_dll_config(sysinfo);
- }
printk(BIOS_DEBUG, "Setting up RAM \n");
+
/*
- Wait 200us
- reg32 = inb(ACPI_BASE + 8); PM1 Timer
- reg32 &=0xFFFFFF;
- reg32 +=0x2EE;
- do
- {
- reg32 = inb(ACPI_BASE + 8);PM1 Timer
- reg32 &= 0xFFFFFF;
- }while (reg32 < 0x2EE); */
- /* Apply NOP */
+ * Wait 200us
+ * reg32 = inb(ACPI_BASE + 8); PM1 Timer
+ * reg32 &=0xFFFFFF;
+ * reg32 +=0x2EE;
+ * do {
+ * reg32 = inb(ACPI_BASE + 8);PM1 Timer
+ * reg32 &= 0xFFFFFF;
+ * } while (reg32 < 0x2EE);
+ */
+
+ /* Apply NOP. */
cmd = rank;
cmd |= SCH_DRAMINIT_CMD_NOP;
- sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, SCH_MSG_DUNIT_PORT, 0, cmd);
- /* Set CKE=high */
- reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DRP, 4);
- reg32 &= 0xFFFF9FFF; /* Clear both the CKE static disables */
- sch_port_access_write(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DRP, 4, reg32);
- /* Wait 400ns (not needed when executing from flash)
- Precharge all
+ sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT,
+ SCH_MSG_DUNIT_PORT, 0, cmd);
+ /* Set CKE=high. */
+ reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT,
+ SCH_MSG_DUNIT_REG_DRP, 4);
+ reg32 &= 0xFFFF9FFF; /* Clear both the CKE static disables. */
+ sch_port_access_write(SCH_MSG_DUNIT_PORT,
+ SCH_MSG_DUNIT_REG_DRP, 4, reg32);
+ /*
+ * Wait 400ns (not needed when executing from flash).
+ * Precharge all.
*/
- reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DRP, 4);
+ reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT,
+ SCH_MSG_DUNIT_REG_DRP, 4);
cmd = rank;
cmd |= SCH_DRAMINIT_CMD_PALL;
- sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, SCH_MSG_DUNIT_PORT, 0, cmd);
+ sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT,
+ SCH_MSG_DUNIT_PORT, 0, cmd);
- /*EMRS(2); High temp self refresh=disabled, partial array self refresh=full */
+ /*
+ * EMRS(2); High temp self refresh=disabled,
+ * partial array self refresh=full.
+ */
cmd = rank;
cmd |= SCH_DRAMINIT_CMD_EMRS2;
- sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, SCH_MSG_DUNIT_PORT, 0, cmd);
- /*EMRS(3) (no command) */
+ sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT,
+ SCH_MSG_DUNIT_PORT, 0, cmd);
+
+ /* EMRS(3) (no command). */
cmd = rank;
cmd |= SCH_DRAMINIT_CMD_EMRS3;
- sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, SCH_MSG_DUNIT_PORT, 0, cmd);
- /*EMRS(1); Enable DLL (Leave all bits in the command at 0) */
+ sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT,
+ SCH_MSG_DUNIT_PORT, 0, cmd);
+
+ /* EMRS(1); Enable DLL (Leave all bits in the command at 0). */
cmd = rank;
cmd |= SCH_DRAMINIT_CMD_EMRS1;
- sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, SCH_MSG_DUNIT_PORT, 0, cmd);
- /*MRS; Reset DLL (Set memory address bit 8) */
+ sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT,
+ SCH_MSG_DUNIT_PORT, 0, cmd);
+
+ /* MRS; Reset DLL (Set memory address bit 8). */
cmd = rank;
cmd |= SCH_DRAMINIT_CMD_MRS;
cmd |= (SCH_JEDEC_DLLRESET << SCH_DRAMINIT_ADDR_OFFSET);
- sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, SCH_MSG_DUNIT_PORT, 0, cmd);
- /*Precharge all */
+ sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT,
+ SCH_MSG_DUNIT_PORT, 0, cmd);
+
+ /* Precharge all. */
cmd = rank;
cmd |= SCH_DRAMINIT_CMD_PALL;
- sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, SCH_MSG_DUNIT_PORT, 0, cmd);
- /*Issue 2 auto-refresh commands */
+ sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT,
+ SCH_MSG_DUNIT_PORT, 0, cmd);
+
+ /* Issue 2 auto-refresh commands. */
cmd = rank;
cmd |= SCH_DRAMINIT_CMD_AREF;
- sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, SCH_MSG_DUNIT_PORT, 0, cmd);
- sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, SCH_MSG_DUNIT_PORT, 0, cmd);
- /*MRS command including tCL, tWR, burst length (always 4) */
+ sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT,
+ SCH_MSG_DUNIT_PORT, 0, cmd);
+ sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT,
+ SCH_MSG_DUNIT_PORT, 0, cmd);
+
+ /* MRS command including tCL, tWR, burst length (always 4). */
cmd = rank;
- cmd |= (SCH_DRAMINIT_CMD_MRS + JEDEC_STATIC_PARAM); /*Static param */
+ cmd |= (SCH_DRAMINIT_CMD_MRS + JEDEC_STATIC_PARAM); /* Static param */
temp = sysinfo->cl;
- temp += TCL_LOW; /*Adjust for the TCL base */
- temp = temp << ((SCH_JEDEC_CL_OFFSET + SCH_DRAMINIT_ADDR_OFFSET)); /*Ready the CAS latency */
+ temp += TCL_LOW; /* Adjust for the TCL base. */
+ temp = temp << ((SCH_JEDEC_CL_OFFSET
+ + SCH_DRAMINIT_ADDR_OFFSET)); /* Ready the CAS latency */
cmd |= temp;
- sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, SCH_MSG_DUNIT_PORT, 0, cmd);
- /* Wait 200 clocks (max of 1us, so no need to delay)
- Issue EMRS(1):OCD default
+ sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT,
+ SCH_MSG_DUNIT_PORT, 0, cmd);
+
+ /*
+ * Wait 200 clocks (max of 1us, so no need to delay).
+ * Issue EMRS(1):OCD default.
*/
cmd = rank;
cmd |= SCH_DRAMINIT_CMD_EMRS1;
cmd |= (SCH_JEDEC_OCD_DEFAULT << SCH_DRAMINIT_ADDR_OFFSET);
- sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, SCH_MSG_DUNIT_PORT, 0, cmd);
- /*Issue EMRS(1): OCD cal. mode exit. */
+ sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT,
+ SCH_MSG_DUNIT_PORT, 0, cmd);
+
+ /* Issue EMRS(1): OCD cal. mode exit. */
cmd = rank;
cmd |= SCH_DRAMINIT_CMD_EMRS1;
cmd |= (SCH_JEDEC_DQS_DIS << SCH_DRAMINIT_ADDR_OFFSET);
- sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT, SCH_MSG_DUNIT_PORT, 0, cmd);
+ sch_port_access_write_ram_cmd(SCH_OPCODE_DRAMINIT,
+ SCH_MSG_DUNIT_PORT, 0, cmd);
rank += SCH_DRAMINIT_RANK_MASK;
num_ranks--;
} while (num_ranks);
}
/**
- * @param boot_mode: 0 = normal, 1 = resume
+ * @param boot_mode 0 = normal, 1 = resume
*/
-
void sdram_initialize(int boot_mode)
{
struct sys_info sysinfo;
memset(&sysinfo, 0, sizeof(sysinfo));
-
detect_fsb(&sysinfo);
detect_softstraps(&sysinfo);
program_sch_dram_data(&sysinfo);
/* cold boot */
- if (boot_mode == BOOT_MODE_NORMAL) {
+ if (boot_mode == BOOT_MODE_NORMAL)
do_jedec_init(&sysinfo);
- } else {
+ else
program_dll_config(&sysinfo);
- }
- /* raminit complete */
- reg32 = sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DCO, 4);
+ /* RAM init complete. */
+ reg32 =
+ sch_port_access_read(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DCO, 4);
reg32 |= DCO_IC;
reg32 |= ((sysinfo.refresh) << 2);
reg32 = 0x006919c;
- sch_port_access_write(SCH_MSG_DUNIT_PORT, SCH_MSG_DUNIT_REG_DCO, 4, reg32);
+ sch_port_access_write(SCH_MSG_DUNIT_PORT,
+ SCH_MSG_DUNIT_REG_DCO, 4, reg32);
- /* setting up TOM */
+ /* Setting up TOM. */
reg32 = 0x10000000;
reg32 = reg32 >> sysinfo.data_width;
reg32 = reg32 << sysinfo.device_density;
reg32 = 0x40000000;
sch_port_access_write(2, 8, 4, reg32);
- /* resume mode */
- if (boot_mode == BOOT_MODE_RESUME) {
+ /* Resume mode. */
+ if (boot_mode == BOOT_MODE_RESUME)
sch_port_access_write_ram_cmd(SCH_OPCODE_WAKEFULLON,
SCH_MSG_DUNIT_PORT, 0, 0);
- }
sch_port_access_write(2, 0, 4, 0x98);
sch_port_access_write(2, 3, 4, 0x7);
sch_port_access_write(3, 2, 4, 0x408);
sch_port_access_write(4, 0x71, 4, 0x600);
}
-
#ifndef __SCH_PULSBO_H__
#define __SCH_PULSBO_H__ 1
-int sch_port_access_read(int port,int reg, int bytes);
-void sch_port_access_write(int port,int reg,int bytes,long data);
-void sch_port_access_write_ram_cmd(int cmd,int port,int reg,int data);
+int sch_port_access_read(int port, int reg, int bytes);
+void sch_port_access_write(int port, int reg, int bytes, long data);
+void sch_port_access_write_ram_cmd(int cmd, int port, int reg, int data);
/* Southbridge IO BARs */
/* TODO Make sure these don't get changed by stage2 */
if (set_bits(base + 0x08, 1, 1) == -1)
goto no_codec;
- /* Read in Codec location (BAR + 0xe)[2..0]*/
+ /* Read in Codec location (BAR + 0xe)[2..0] */
reg32 = read32(base + 0xe);
reg32 &= 0x0f;
if (!reg32)
return 0;
}
-const u32 * cim_verb_data = NULL;
+const u32 *cim_verb_data = NULL;
u32 cim_verb_data_size = 0;
static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb)
printk(BIOS_DEBUG, "sch_audio: dev=%s\n", dev_path(dev));
printk(BIOS_DEBUG, "sch_audio: Reading viddid=%x\n", viddid);
- int idx=0;
+ int idx = 0;
while (idx < (cim_verb_data_size / sizeof(u32))) {
- u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32
- verb_size++; // we ship an additional gain value
+ u32 verb_size = 4 * cim_verb_data[idx + 2]; // in u32
+ verb_size++; // we ship an additional gain value
if (cim_verb_data[idx] != viddid) {
- idx += verb_size + 3; // skip verb + header
+ idx += verb_size + 3; // skip verb + header
continue;
}
- *verb = &cim_verb_data[idx+3];
+ *verb = &cim_verb_data[idx + 3];
return verb_size;
}
int timeout = 50;
- while(timeout--) {
- u32 reg32 = read32(base + HDA_ICII_REG);
+ while (timeout--) {
+ u32 reg32 = read32(base + HDA_ICII_REG);
if (!(reg32 & HDA_ICII_BUSY))
return 0;
udelay(1);
int timeout = 25;
write32(base + 0x68, 1);
- while(timeout--)
- {
+ while (timeout--) {
udelay(1);
}
timeout = 50;
- while(timeout--)
- {
- u32 reg32 = read32(base + 0x68);
- if ((reg32 & ((1 << 1) | (1 << 0))) ==(1 << 1))
- {
+ while (timeout--) {
+ u32 reg32 = read32(base + 0x68);
+ if ((reg32 & ((1 << 1) | (1 << 0))) == (1 << 1)) {
write32(base + 0x68, 2);
- return 0;
+ return 0;
}
- udelay(1);
- }
-
+ udelay(1);
+ }
return 1;
}
if (wait_for_valid(base) == -1)
return;
-
reg32 = read32(base + 0x0);
printk(BIOS_DEBUG, "sch_audio: GCAP: %08x\n", reg32);
static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
{
int i;
+
for (i = 2; i >= 0; i--) {
if (codec_mask & (1 << i))
codec_init(dev, base, i);
u32 codec_mask;
u32 reg32;
-
-
res = find_resource(dev, 0x10);
if (!res)
return;
// NOTE this will break as soon as the sch_audio get's a bar above
// 4G. Is there anything we can do about it?
- base = (u32)res->base;
- printk(BIOS_DEBUG, "sch_audio: base = %08x\n", (u32)base);
+ base = (u32) res->base;
+ printk(BIOS_DEBUG, "sch_audio: base = %08x\n", (u32) base);
codec_mask = codec_detect(base);
if (codec_mask) {
- printk(BIOS_DEBUG, "sch_audio: codec_mask = %02x\n", codec_mask);
+ printk(BIOS_DEBUG, "sch_audio: codec_mask = %02x\n",
+ codec_mask);
codecs_init(dev, base, codec_mask);
- }
- else
- {
- /* No audio codecs found disable HD audio controller*/
+ } else {
+ /* No audio codecs found disable HD audio controller */
pci_write_config32(dev, 0x10, 0);
pci_write_config32(dev, PCI_COMMAND, 0);
reg32 = pci_read_config32(dev, 0xFC);
}
}
-static void sch_audio_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void sch_audio_set_subsystem(device_t dev, unsigned vendor,
+ unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
- pci_read_config32(dev, PCI_VENDOR_ID));
+ pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
}
}
static struct pci_operations sch_audio_pci_ops = {
- .set_subsystem = sch_audio_set_subsystem,
+ .set_subsystem = sch_audio_set_subsystem,
};
static struct device_operations sch_audio_ops = {
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x811B,
};
-
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
-
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
+ * published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
#include <device/pci_ids.h>
/* PCI Configuration Space (D31:F1): IDE */
-#define INTR_LN 0x3c
-#define IDE_TIM_PRI 0x80 /* IDE timings, primary */
+#define INTR_LN 0x3c
+#define IDE_TIM_PRI 0x80 /* IDE timings, primary */
+
+extern int sch_port_access_read(int port, int reg, int bytes);
-extern int sch_port_access_read(int port,int reg, int bytes);
static void ide_init(struct device *dev)
{
- u32 ideTimingConfig;
- u32 reg32;
+ u32 ideTimingConfig, reg32;
+
printk(BIOS_DEBUG, "sch_ide: initializing... ");
reg32 = pci_read_config32(dev, PCI_COMMAND);
- pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_IO | PCI_COMMAND_MASTER);
-
- /* Program the clock */
+ pci_write_config32(dev, PCI_COMMAND,
+ reg32 | PCI_COMMAND_IO | PCI_COMMAND_MASTER);
- if (sch_port_access_read(5,3,4) & (1<<3))
- {
- /*533MHz
- Read PCI MC register*/
+ /* Program the clock. */
+ if (sch_port_access_read(5, 3, 4) & (1 << 3)) {
+ /* 533MHz, Read PCI MC register */
reg32 = pci_read_config32(dev, 0x60);
- pci_write_config32(dev,0x60,reg32 | 1);
- }
- else
- {
- /*400MHz*/
+ pci_write_config32(dev, 0x60, reg32 | 1);
+ } else {
+ /* 400MHz */
reg32 = pci_read_config32(dev, 0x60);
- reg32 &=~(1);
- pci_write_config32(dev,0x60,reg32);
+ reg32 &= ~1;
+ pci_write_config32(dev, 0x60, reg32);
}
-
- /* Enable primary IDE interface.
- 80=04 81=00 82=02 83=80
- */
+ /* Enable primary IDE interface. 80=04 81=00 82=02 83=80 */
ideTimingConfig = 0x80020000;
printk(BIOS_DEBUG, "IDE0 ");
pci_write_config32(dev, IDE_TIM_PRI, ideTimingConfig);
- /* Set Interrupt Line */
+ /* Set Interrupt Line. */
/* Interrupt Pin is set by D31IP.PIP */
printk(BIOS_DEBUG, "\n");
}
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
- pci_read_config32(dev, PCI_VENDOR_ID));
+ pci_read_config32(dev, PCI_VENDOR_ID));
} else {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations ide_pci_ops = {
- .set_subsystem = ide_set_subsystem,
+ .set_subsystem = ide_set_subsystem,
};
static struct device_operations ide_ops = {
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
+ * published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
#include <device/pci.h>
#include <device/pci_ids.h>
#include <arch/io.h>
-
#include "chip.h"
-
-/*SCH LPC defines*/
-#define SCH_ACPI_CTL 0x58
-#define SCH_SIRQ_CTL 0x68
-#define PIRQA_ROUT 0x60
-#define PIRQB_ROUT 0x61
-#define PIRQC_ROUT 0x62
-#define PIRQD_ROUT 0x63
-#define PIRQE_ROUT 0x64
-#define PIRQF_ROUT 0x65
-#define PIRQG_ROUT 0x66
-#define PIRQH_ROUT 0x67
+/* SCH LPC defines */
+#define SCH_ACPI_CTL 0x58
+#define SCH_SIRQ_CTL 0x68
+#define PIRQA_ROUT 0x60
+#define PIRQB_ROUT 0x61
+#define PIRQC_ROUT 0x62
+#define PIRQD_ROUT 0x63
+#define PIRQE_ROUT 0x64
+#define PIRQF_ROUT 0x65
+#define PIRQG_ROUT 0x66
+#define PIRQH_ROUT 0x67
typedef struct southbridge_intel_sch_config config_t;
#define PIRQF 0x0A
#define PIRQG 0x0B
#define PIRQH 0x0C
+
static void sch_pirq_init(device_t dev)
{
device_t irq_dev;
+
/* Get the chip configuration */
config_t *config = dev->chip_info;
* I am not so sure anymore he was right.
*/
- for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next)
- {
- u8 int_pin=0, int_line=0;
+ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+ u8 int_pin = 0, int_line = 0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
continue;
int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
- switch (int_pin)
- {
- case 1: /* INTA# */ int_line = config->pirqa_routing; break;
- case 2: /* INTB# */ int_line = config->pirqb_routing; break;
- case 3: /* INTC# */ int_line = config->pirqc_routing; break;
- case 4: /* INTD# */ int_line = config->pirqd_routing; break;
+ switch (int_pin) {
+ case 1: /* INTA# */
+ int_line = config->pirqa_routing;
+ break;
+ case 2: /* INTB# */
+ int_line = config->pirqb_routing;
+ break;
+ case 3: /* INTC# */
+ int_line = config->pirqc_routing;
+ break;
+ case 4: /* INTD# */
+ int_line = config->pirqd_routing;
+ break;
}
if (!int_line)
pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
}
}
+
static void sch_fixups(struct device *dev)
{
- u32 rcba_base;
- /* This needs to happen after PCI enumeration
- RCBA32(0x1d40) |= 1;*/
+ u32 rcba_base;
+
+ /* This needs to happen after PCI enumeration. */
+ /* RCBA32(0x1d40) |= 1; */
rcba_base = pci_read_config32(dev, 0xF0);
- /*Remove the enable bit*/
+
+ /* Remove the enable bit. */
rcba_base = rcba_base >> 1;
rcba_base = rcba_base << 1;
*((volatile u32 *)(rcba_base +0x104)) &= 0xFF00FFFF;
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
+ * published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
printk(BIOS_DEBUG, "done.\n");
}
-static void sch_mmc_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void sch_mmc_set_subsystem(device_t dev, unsigned vendor,
+ unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
-
}
static struct pci_operations lops_pci = {
- .set_subsystem = &sch_mmc_set_subsystem,
+ .set_subsystem = &sch_mmc_set_subsystem,
};
static struct device_operations sch_mmc_ops = {
.device = 0x811E,
};
-
// reg16 &= ~(1 << 1); /* disable SERR */
//reg16 |= (1 << 2); /* ISA enable */
//pci_write_config16(dev, 0x3e, reg16);
- /*Slot implimented*/
+ /* Slot implemented. */
reg16 = pci_read_config16(dev, 0x42);
reg16 |= (1 << 8);
pci_write_config16(dev, 0x42, reg16);
reg16 = pci_read_config16(dev, 0x48);
reg16 |= 0xf;
pci_write_config16(dev, 0x48, reg16);
-
}
static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
/* NOTE: This is not the default position! */
if (!vendor || !device) {
- pci_write_config32(dev, 0x94,
- pci_read_config32(dev, 0));
+ pci_write_config32(dev, 0x94, pci_read_config32(dev, 0));
} else {
pci_write_config32(dev, 0x94,
((device & 0xffff) << 16) | (vendor & 0xffff));
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x8112,
};
-
void soft_reset(void)
{
- outb(0x04, 0xcf9);
+ outb(0x04, 0xcf9);
}
void hard_reset(void)
{
- outb(0x02, 0xcf9);
- outb(0x06, 0xcf9);
+ outb(0x02, 0xcf9);
+ outb(0x06, 0xcf9);
}
-
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
+ * published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
.ops_pci = &smbus_pci_ops,
};
+// FIXME
/* 82801GB/GR/GDH/GBM/GHM/GU (ICH7/ICH7R/ICH7DH/ICH7-M/ICH7-M DH/ICH7-U) */
static const struct pci_driver i82801gx_smbus __pci_driver = {
.ops = &smbus_ops,
return loops ? 0 : -1;
}
-static int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned address)
+static int do_smbus_read_byte(unsigned smbus_base, unsigned device,
+ unsigned address)
{
unsigned char global_status_register;
unsigned char byte;
outb(0, smbus_base + SMBHSTDAT0);
/* Start the command */
- outb((inb(smbus_base + SMBHSTCTL) | 0x40),
- smbus_base + SMBHSTCTL);
+ outb((inb(smbus_base + SMBHSTCTL) | 0x40), smbus_base + SMBHSTCTL);
/* Poll for transaction completion */
if (smbus_wait_until_done(smbus_base) < 0) {
}
return byte;
}
-
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
+ * published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-
#include <device/device.h>
#include <device/pci.h>
#include <console/console.h>
printk(BIOS_DEBUG, "\n");
}
-
/**
* @brief read and clear GPE0_STS
* @return GPE0_STS register
return reg32;
}
-
static void dump_tco_status(u32 tco_sts)
{
printk(BIOS_DEBUG, "TCO_STS: ");
printk(BIOS_DEBUG, "\n");
}
-
-
/**
* @brief Set the EOS bit
*/
struct chip_operations southbridge_intel_sch_ops = {
CHIP_NAME("Intel SCH Southbridge")
};
-
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
+ * published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
{
u32 reg32;
- /* USB Specification says the device must be Bus Master */
+ /* USB Specification says the device must be Bus Master. */
printk(BIOS_DEBUG, "UHCI: Setting up controller.. ");
reg32 = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
- /*Disable clock gating*/
+ /* Disable clock gating. */
reg32 = pci_read_config32(dev, 0xFC);
reg32 |= (1 << 2);
pci_write_config32(dev, 0xFC, reg32);
}
static struct pci_operations usb_pci_ops = {
- .set_subsystem = usb_set_subsystem,
+ .set_subsystem = usb_set_subsystem,
};
static struct device_operations usb_ops = {
.ops_pci = &usb_pci_ops,
};
-/* */
static const struct pci_driver sch_usb0 __pci_driver = {
.ops = &usb_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x8114,
};
+
static const struct pci_driver sch_usb1 __pci_driver = {
.ops = &usb_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x8115,
};
+
static const struct pci_driver sch_usb2 __pci_driver = {
.ops = &usb_ops,
.vendor = PCI_VENDOR_ID_INTEL,
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
+ * published by the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
}
static struct pci_operations lops_pci = {
- .set_subsystem = &usb_client_set_subsystem,
+ .set_subsystem = &usb_client_set_subsystem,
};
static struct device_operations usb_client_ops = {
.ops_pci = &lops_pci,
};
-/* */
static const struct pci_driver sch_usb_client __pci_driver = {
.ops = &usb_client_ops,
.vendor = PCI_VENDOR_ID_INTEL,
printk(BIOS_DEBUG, "done.\n");
}
-static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void usb_ehci_set_subsystem(device_t dev, unsigned vendor,
+ unsigned device)
{
u8 access_cntl;
}
static struct pci_operations lops_pci = {
- .set_subsystem = &usb_ehci_set_subsystem,
+ .set_subsystem = &usb_ehci_set_subsystem,
};
static struct device_operations usb_ehci_ops = {
.ops_pci = &lops_pci,
};
-/* */
static const struct pci_driver sch_usb_ehci __pci_driver = {
.ops = &usb_ehci_ops,
.vendor = PCI_VENDOR_ID_INTEL,
projects / coreboot.git / commitdiff