*\r
*\r
*/\r
-CODECENTRY AzaliaCodecAlc882Table[] =\r
+const static CODECENTRY AzaliaCodecAlc882Table[] =\r
{\r
{0x14, 0x01014010},\r
{0x15, 0x01011012},\r
*\r
*\r
*/\r
-CODECENTRY AzaliaCodecAlc262Table[] =\r
+const static CODECENTRY AzaliaCodecAlc262Table[] =\r
{\r
{0x14, 0x01014010},\r
{0x15, 0x411111F0},\r
*\r
*\r
*/\r
-CODECENTRY AzaliaCodecAlc269Table[] =\r
+const static CODECENTRY AzaliaCodecAlc269Table[] =\r
{\r
{0x12, 0x99A30960},\r
{0x14, 0x99130110},\r
*\r
*\r
*/\r
-CODECENTRY AzaliaCodecAlc861Table[] =\r
+const static CODECENTRY AzaliaCodecAlc861Table[] =\r
{\r
{0x01, 0x8086C601},\r
{0x0B, 0x01014110},\r
*\r
*\r
*/\r
-CODECENTRY AzaliaCodecAlc889Table[] =\r
+const static CODECENTRY AzaliaCodecAlc889Table[] =\r
{\r
{0x11, 0x411111F0},\r
{0x14, 0x01014010},\r
*\r
*\r
*/\r
-CODECENTRY AzaliaCodecAd1984Table[] =\r
+const static CODECENTRY AzaliaCodecAd1984Table[] =\r
{\r
{0x11, 0x0221401F},\r
{0x12, 0x90170110},\r
*\r
*\r
*/\r
-CODECENTRY FrontPanelAzaliaCodecTableList[] =\r
+const static CODECENTRY FrontPanelAzaliaCodecTableList[] =\r
{\r
{0x19, 0x02A19040},\r
{0x1b, 0x02214020},\r
*\r
*\r
*/\r
-CODECTBLLIST azaliaCodecTableList[] =\r
+const static CODECTBLLIST azaliaCodecTableList[] =\r
{\r
- {0x010ec0880, &AzaliaCodecAlc882Table[0]},\r
- {0x010ec0882, &AzaliaCodecAlc882Table[0]},\r
- {0x010ec0883, &AzaliaCodecAlc882Table[0]},\r
- {0x010ec0885, &AzaliaCodecAlc882Table[0]},\r
- {0x010ec0889, &AzaliaCodecAlc889Table[0]},\r
- {0x010ec0262, &AzaliaCodecAlc262Table[0]},\r
- {0x010ec0269, &AzaliaCodecAlc269Table[0]},\r
- {0x010ec0861, &AzaliaCodecAlc861Table[0]},\r
- {0x011d41984, &AzaliaCodecAd1984Table[0]},\r
+ {0x010ec0880, (CODECENTRY*)&AzaliaCodecAlc882Table[0]},\r
+ {0x010ec0882, (CODECENTRY*)&AzaliaCodecAlc882Table[0]},\r
+ {0x010ec0883, (CODECENTRY*)&AzaliaCodecAlc882Table[0]},\r
+ {0x010ec0885, (CODECENTRY*)&AzaliaCodecAlc882Table[0]},\r
+ {0x010ec0889, (CODECENTRY*)&AzaliaCodecAlc889Table[0]},\r
+ {0x010ec0262, (CODECENTRY*)&AzaliaCodecAlc262Table[0]},\r
+ {0x010ec0269, (CODECENTRY*)&AzaliaCodecAlc269Table[0]},\r
+ {0x010ec0861, (CODECENTRY*)&AzaliaCodecAlc861Table[0]},\r
+ {0x011d41984, (CODECENTRY*)&AzaliaCodecAd1984Table[0]},\r
{ (UINT32) 0x0FFFFFFFF, (CODECENTRY*) (UINTN)0x0FFFFFFFF}\r
};\r
\r
*\r
*\r
*/\r
-UINT8 FunctionNumber[] =\r
+const static UINT8 FunctionNumber[] =\r
{\r
Fun_81,\r
Fun_83,\r
*\r
*\r
*/\r
-UINT8 MaxZone[] =\r
+const static UINT8 MaxZone[] =\r
{\r
4,\r
4,\r
*\r
*\r
*/\r
-UINT8 MaxRegister[] =\r
+const static UINT8 MaxRegister[] =\r
{\r
MSG_REG9,\r
MSG_REGB,\r
-#\r
-# This file is part of the coreboot project.\r
-#\r
-# Copyright (C) 2010 Advanced Micro Devices, Inc.\r
-#\r
-# This program is free software; you can redistribute it and/or modify\r
-# it under the terms of the GNU General Public License as published by\r
-# the Free Software Foundation; version 2 of the License.\r
-#\r
-# This program is distributed in the hope that it will be useful,\r
-# but WITHOUT ANY WARRANTY; without even the implied warranty of\r
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
-# GNU General Public License for more details.\r
-#\r
-# You should have received a copy of the GNU General Public License\r
-# along with this program; if not, write to the Free Software\r
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
-#\r
-\r
-# CIMX Root directory\r
-CIMX_ROOT = src/vendorcode/amd/cimx\r
-\r
-CIMX_INC = -I$(src)/mainboard/$(MAINBOARDDIR)\r
-CIMX_INC += -I$(src)/southbridge/amd/cimx_wrapper/sb800\r
-CIMX_INC += -I$(CIMX_ROOT)/sb800\r
-#TODO merge withagesa lib functions\r
-CIMX_INC += -I$(CIMX_ROOT)/lib\r
-\r
-# CIMX LIB files\r
-romstage-y += MEMLIB.c\r
-romstage-y += PCILIB.c\r
-romstage-y += IOLIB.c\r
-romstage-y += PMIOLIB.c\r
-romstage-y += AMDLIB.c\r
-romstage-y += SBPELIB.c\r
-romstage-y += AMDSBLIB.c\r
-romstage-y += SBPOR.c\r
-romstage-y += ECLIB.c\r
-romstage-y += EC.c\r
-ramstage-y += DISPATCHER.c\r
-\r
-ramstage-y += ACPILIB.c\r
-ramstage-y += AZALIA.c\r
-ramstage-y += DISPATCHER.c\r
-ramstage-y += ECfanc.c\r
-ramstage-y += ECfanLIB.c\r
-ramstage-y += GEC.c\r
-ramstage-y += Gpp.c\r
-ramstage-y += PMIO2LIB.c\r
-ramstage-y += SATA.c\r
-ramstage-y += SBCMN.c\r
-ramstage-y += SBMAIN.c\r
-ramstage-y += SBPOR.c\r
-ramstage-y += MEMLIB.c\r
-ramstage-y += PCILIB.c\r
-ramstage-y += IOLIB.c\r
-ramstage-y += PMIOLIB.c\r
-ramstage-y += AMDLIB.c\r
-ramstage-y += SBPELIB.c\r
-ramstage-y += AMDSBLIB.c\r
-ramstage-y += ECLIB.c\r
-ramstage-y += EC.c\r
-ramstage-y += SMM.c\r
-ramstage-y += USB.c\r
-#ramstage-y += LEGACY.c\r
-#ramstage-y += SbModInf.c\r
-\r
-CIMX_CFLAGS =\r
-export CIMX_ROOT\r
-export CIMX_INC\r
-export CIMX_CFLAGS\r
-CC := $(CC) $(CIMX_INC)\r
-\r
-#######################################################################\r
-\r
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2010 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+# CIMX Root directory
+CIMX_ROOT = src/vendorcode/amd/cimx
+
+CIMX_INC = -I$(src)/mainboard/$(MAINBOARDDIR)
+CIMX_INC += -I$(src)/southbridge/amd/cimx_wrapper/sb800
+CIMX_INC += -I$(CIMX_ROOT)/sb800
+#TODO merge with agesa lib functions
+CIMX_INC += -I$(CIMX_ROOT)/lib
+
+romstage-y += ACPILIB.c
+romstage-y += AZALIA.c
+romstage-y += DISPATCHER.c
+romstage-y += ECfanc.c
+romstage-y += ECfanLIB.c
+romstage-y += GEC.c
+romstage-y += Gpp.c
+romstage-y += PMIO2LIB.c
+romstage-y += SATA.c
+romstage-y += SBCMN.c
+romstage-y += SBMAIN.c
+romstage-y += SBPOR.c
+romstage-y += MEMLIB.c
+romstage-y += PCILIB.c
+romstage-y += IOLIB.c
+romstage-y += PMIOLIB.c
+romstage-y += AMDLIB.c
+romstage-y += SBPELIB.c
+romstage-y += AMDSBLIB.c
+romstage-y += ECLIB.c
+romstage-y += EC.c
+romstage-y += SMM.c
+romstage-y += USB.c
+
+ramstage-y += ACPILIB.c
+ramstage-y += AZALIA.c
+ramstage-y += DISPATCHER.c
+ramstage-y += ECfanc.c
+ramstage-y += ECfanLIB.c
+ramstage-y += GEC.c
+ramstage-y += Gpp.c
+ramstage-y += PMIO2LIB.c
+ramstage-y += SATA.c
+ramstage-y += SBCMN.c
+ramstage-y += SBMAIN.c
+ramstage-y += SBPOR.c
+ramstage-y += MEMLIB.c
+ramstage-y += PCILIB.c
+ramstage-y += IOLIB.c
+ramstage-y += PMIOLIB.c
+ramstage-y += AMDLIB.c
+ramstage-y += SBPELIB.c
+ramstage-y += AMDSBLIB.c
+ramstage-y += ECLIB.c
+ramstage-y += EC.c
+ramstage-y += SMM.c
+ramstage-y += USB.c
+#ramstage-y += LEGACY.c
+#ramstage-y += SbModInf.c
+
+CIMX_CFLAGS =
+export CIMX_ROOT
+export CIMX_INC
+export CIMX_CFLAGS
+CC := $(CC) $(CIMX_INC)
+
+#######################################################################
+
*\r
*\r
*/\r
-UINT32 sataIfCodeTable[] =\r
+const static UINT32 sataIfCodeTable[] =\r
{\r
0x01018F40, //sata class ID of IDE\r
0x01040040, //sata class ID of RAID\r
*\r
*\r
*/\r
-UINT16 sataDeviceIDTable[] =\r
+const static UINT16 sataDeviceIDTable[] =\r
{\r
0x4390, //sata device ID of IDE\r
0x4392, //sata device ID of RAID\r
*\r
*\r
*/\r
-SATAPHYSETTING sataPhyTable[] =\r
+const static SATAPHYSETTING sataPhyTable[] =\r
{\r
{0x3006, 0x0056A607},\r
{0x2006, 0x00061400},\r
* sbEarlyPostByteInitTable - PCI device registers initial during early POST.\r
*\r
*/\r
-REG8MASK sbEarlyPostByteInitTable[] =\r
+const static REG8MASK sbEarlyPostByteInitTable[] =\r
{\r
// SMBUS Device (Bus 0, Dev 20, Func 0)\r
{0x00, SMBUS_BUS_DEV_FUN, 0},\r
* sbPmioEPostInitTable - Southbridge ACPI MMIO initial during POST.\r
*\r
*/\r
-AcpiRegWrite sbPmioEPostInitTable[] =\r
+const static AcpiRegWrite sbPmioEPostInitTable[] =\r
{\r
// HPET workaround\r
{PMIO_BASE >> 8, SB_PMIOA_REG54 + 3, 0xFC, BIT0 + BIT1},\r
* abTblEntry800 - AB-Link Configuration Table for SB800\r
*\r
*/\r
-ABTBLENTRY abTblEntry800[] =\r
+const static ABTBLENTRY abTblEntry800[] =\r
{\r
// RPR Enable downstream posted transactions to pass non-posted transactions.\r
{ABCFG, SB_ABCFG_REG10090, BIT8 + BIT16, BIT8 + BIT16},\r
* SbPcieOrderRule - AB-Link Configuration Table for ablink Post Pass Np Downstream/Upstream Feature\r
*\r
*/\r
-ABTBLENTRY SbPcieOrderRule[] =\r
+const static ABTBLENTRY SbPcieOrderRule[] =\r
{\r
// abPostPassNpDownStreamTbl\r
{ABCFG, SB_ABCFG_REG10060, BIT31, BIT31},\r