Random fixes for TI pci1x2x / Nokia IP530 / others.

 - nokia/ip530/devicetree.cb, southbridge/ti/pci1x2x/pci1x2x.c:
   - Fix SMSC FDC37B787 name (was a typo).
   - Disable PS/2 keyboard/mouse LDN, the IP530 doesn't have either.
   - Fix typo: s/PCI_DEVICE_ID_TI_1420/PCI_DEVICE_ID_TI_1520/.
   - All of these are confirmed by Marc Bertens on IRC.

 - Fix a few CHIP_NAME HP board names.

 - Random whitespace and coding-style fixes.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6212 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/drivers/dec/21143/21143.c b/src/drivers/dec/21143/21143.c
index 62567c80385e523fd696adaeb1a44ed5c7dd1e14..7ca6f12078ee71ed1bb2afc0cb683e9ac2f76ca5 100644 (file)
--- a/src/drivers/dec/21143/21143.c
+++ b/src/drivers/dec/21143/21143.c
@@ -38,33 +38,40 @@
 /* CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION try 0x02800107 or 0x02800007 if unsure */
 
 /**
- * This driver take the values from Kconfig and load them in the registers
+ * This driver takes the values from Kconfig and loads them in the registers.
  */
-static void dec_21143_enable( device_t dev )
+static void dec_21143_enable(device_t dev)
 {
-       printk( BIOS_DEBUG, "Init of DECchip 21143 Kconfig style\n");
-       // Command and Status Configuration Register (Offset 0x04)
-       pci_write_config32( dev, 0x04, CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION );
-       printk( BIOS_DEBUG, "0x04 = %08x (07 01 80 02)\n", pci_read_config32(dev, 0x04) );
-       // Cache Line Size Register (Offset 0x0C)
-       pci_write_config8( dev, 0x0C, CONFIG_DEC21143_CACHE_LINE_SIZE );
-       printk( BIOS_DEBUG, "0x0c = %08x (00 80 00 00)\n", pci_read_config32(dev, 0x0C) );
-       // Expansion ROM Base Address Register (Offset 0x30)
-       pci_write_config32( dev, 0x30, CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS );
-       printk( BIOS_DEBUG, "0x30 = %08x (0x00000000)\n", pci_read_config32(dev, 0x30) );
-       return;
+       printk(BIOS_DEBUG, "Initializing DECchip 21143\n");
+
+       /* Command and status configuration (offset 0x04) */
+       pci_write_config32(dev, 0x04,
+                          CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION);
+       printk(BIOS_DEBUG, "0x04 = %08x (07 01 80 02)\n",
+              pci_read_config32(dev, 0x04));
+
+       /* Cache line size (offset 0x0C) */
+       pci_write_config8(dev, 0x0C, CONFIG_DEC21143_CACHE_LINE_SIZE);
+       printk(BIOS_DEBUG, "0x0c = %08x (00 80 00 00)\n",
+              pci_read_config32(dev, 0x0C));
+
+       /* Expansion ROM base address (offset 0x30) */
+       pci_write_config32(dev, 0x30,
+                          CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS);
+       printk(BIOS_DEBUG, "0x30 = %08x (0x00000000)\n",
+              pci_read_config32(dev, 0x30));
 }
 
-static struct device_operations dec_21143_ops  = {
-        .read_resources   = pci_dev_read_resources,
-        .set_resources    = pci_dev_set_resources,
-        .enable_resources = pci_dev_enable_resources,
-        .init             = dec_21143_enable,
-        .scan_bus         = 0,
+static struct device_operations dec_21143_ops = {
+       .read_resources   = pci_dev_read_resources,
+       .set_resources    = pci_dev_set_resources,
+       .enable_resources = pci_dev_enable_resources,
+       .init             = dec_21143_enable,
+       .scan_bus         = 0,
 };
 
 static const struct pci_driver dec_21143_driver __pci_driver = {
-        .ops    = &dec_21143_ops,
-        .vendor = PCI_VENDOR_ID_DEC,
-        .device = PCI_DEVICE_ID_DEC_21142,
+       .ops    = &dec_21143_ops,
+       .vendor = PCI_VENDOR_ID_DEC,
+       .device = PCI_DEVICE_ID_DEC_21142,
 };

diff --git a/src/mainboard/hp/dl145_g1/mainboard.c b/src/mainboard/hp/dl145_g1/mainboard.c
index 922afe8fd76f51b78e20a8e171f9a3205f013133..d68e720c1b2672ba10d562db9edc64b41f61e38f 100644 (file)
--- a/src/mainboard/hp/dl145_g1/mainboard.c
+++ b/src/mainboard/hp/dl145_g1/mainboard.c
@@ -25,5 +25,5 @@
 #include "chip.h"
 
 struct chip_operations mainboard_ops = {
-       CHIP_NAME("HP DL145G1 Mainboard")
+       CHIP_NAME("HP ProLiant DL145 G1 Mainboard")
 };

diff --git a/src/mainboard/hp/dl145_g3/mainboard.c b/src/mainboard/hp/dl145_g3/mainboard.c
index 14af36eedf4b9488d7a266a3cfc406a8364f8728..7799c16efe9e482904a77be777f6eed03c383a28 100644 (file)
--- a/src/mainboard/hp/dl145_g3/mainboard.c
+++ b/src/mainboard/hp/dl145_g3/mainboard.c
@@ -30,5 +30,5 @@
 #include "chip.h"
 
 struct chip_operations mainboard_ops = {
-       CHIP_NAME("HP DL145 G3 Mainboard")
+       CHIP_NAME("HP ProLiant DL145 G3 Mainboard")
 };

diff --git a/src/mainboard/hp/dl165_g6_fam10/mainboard.c b/src/mainboard/hp/dl165_g6_fam10/mainboard.c
index 1a4cf1c0b6e22bf03b3b09fbaffefaf0e534b95e..d84ba478d5c53bf997157999cb745c76de77a061 100644 (file)
--- a/src/mainboard/hp/dl165_g6_fam10/mainboard.c
+++ b/src/mainboard/hp/dl165_g6_fam10/mainboard.c
@@ -30,5 +30,5 @@
 #include "chip.h"
 
 struct chip_operations mainboard_ops = {
-       CHIP_NAME("HP DL165 G6 Mainboard (Family 10)")
+       CHIP_NAME("HP ProLiant DL165 G6 Mainboard (Fam10h)")
 };

diff --git a/src/mainboard/nokia/ip530/devicetree.cb b/src/mainboard/nokia/ip530/devicetree.cb
index cc3fd37e11a562c2a1e7dc3f91429a2dfd814a1d..673e0cb10d5b7e121be6258c6126ed281090cd10 100644 (file)
--- a/src/mainboard/nokia/ip530/devicetree.cb
+++ b/src/mainboard/nokia/ip530/devicetree.cb
@@ -19,9 +19,9 @@
 ##
 
 chip northbridge/intel/i440bx          # Northbridge
-  device lapic_cluster 0 on            # APIC cluster
-    chip cpu/intel/socket_PGA370       # CPU
-      device lapic 0 on end            # APIC
+  device lapic_cluster 0 on            # (L)APIC cluster
+    chip cpu/intel/socket_PGA370       # CPU socket
+      device lapic 0 on end            # Local APIC of the CPU
     end
   end
   device pci_domain 0 on               # PCI domain
@@ -29,7 +29,7 @@ chip northbridge/intel/i440bx         # Northbridge
     device pci 1.0 on end              # PCI/AGP bridge
     chip southbridge/intel/i82371eb    # Southbridge
       device pci 7.0 on                        # ISA bridge
-        chip superio/smsc/smscsuperio  # Super I/O (SMSC FDC37C878)
+        chip superio/smsc/smscsuperio  # Super I/O (SMSC FDC37B787)
           device pnp 3f0.0 off end     # Floppy (No connector)
           device pnp 3f0.3 off end     # Parallel port (No connector)
           device pnp 3f0.4 on          # COM1
@@ -40,10 +40,10 @@ chip northbridge/intel/i440bx               # Northbridge
             io 0x60 = 0x2f8
             irq 0x70 = 3
           end
-          device pnp 3f0.7 on end      # PS/2 keyboard / mouse
           device pnp 3f0.6 on end      # RTC
+          device pnp 3f0.7 off end     # PS/2 keyboard / mouse (No connector)
           device pnp 3f0.8 on end      # AUX I/O
-          device pnp 3f0.A off end     # ACPI (No support yet)
+          device pnp 3f0.a off end     # ACPI (No support yet)
         end
       end
       device pci 7.1 on end            # IDE

diff --git a/src/southbridge/ti/pci1x2x/pci1x2x.c b/src/southbridge/ti/pci1x2x/pci1x2x.c
index 01aeb6d69fcc09eb9ce96d8f5713fa779c343429..63a0646e88f97fe917161c3a93c647baaef87a74 100644 (file)
--- a/src/southbridge/ti/pci1x2x/pci1x2x.c
+++ b/src/southbridge/ti/pci1x2x/pci1x2x.c
@@ -24,41 +24,43 @@
 #include <device/pci_ops.h>
 #include <console/console.h>
 
-#if (  !defined( CONFIG_TI_PCMCIA_CARDBUS_CMDR ) || \
-       !defined( CONFIG_TI_PCMCIA_CARDBUS_CLSR ) || \
-       !defined( CONFIG_TI_PCMCIA_CARDBUS_CLTR ) || \
-       !defined( CONFIG_TI_PCMCIA_CARDBUS_BCR ) || \
-       !defined( CONFIG_TI_PCMCIA_CARDBUS_SCR ) || \
-       !defined( CONFIG_TI_PCMCIA_CARDBUS_MRR ) )
+#if (!defined(CONFIG_TI_PCMCIA_CARDBUS_CMDR) || \
+     !defined(CONFIG_TI_PCMCIA_CARDBUS_CLSR) || \
+     !defined(CONFIG_TI_PCMCIA_CARDBUS_CLTR) || \
+     !defined(CONFIG_TI_PCMCIA_CARDBUS_BCR) || \
+     !defined(CONFIG_TI_PCMCIA_CARDBUS_SCR) || \
+     !defined(CONFIG_TI_PCMCIA_CARDBUS_MRR))
 #error "you must supply these values in your mainboard-specific Kconfig file"
 #endif
 
 static void ti_pci1x2y_init(struct device *dev)
 {
        printk(BIOS_INFO, "Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller\n");
-       // Command register (offset 04)
-       pci_write_config16( dev, 0x04, CONFIG_TI_PCMCIA_CARDBUS_CMDR );
-       // Cache Line Size Register (offset 0x0C)
-       pci_write_config8( dev, 0x0C, CONFIG_TI_PCMCIA_CARDBUS_CLSR );
-       // CardBus latency timer register (offset 1B)
-       pci_write_config8( dev, 0x1B, CONFIG_TI_PCMCIA_CARDBUS_CLTR );
-       // Bridge control register (offset 3E)
-       pci_write_config16( dev, 0x3E, CONFIG_TI_PCMCIA_CARDBUS_BCR );
-       /** Enable change sub-vendor id
-        * Clear the bit 5 to enable to write to the sub-vendor/device ids at 40 and 42 */
-       pci_write_config32( dev, 0x80, 0x10 );
-       pci_write_config32( dev, 0x40, PCI_VENDOR_ID_NOKIA );
-       // Now write the correct value for SCR
-       // System Control Register (offset 0x80)
-       pci_write_config32( dev, 0x80, CONFIG_TI_PCMCIA_CARDBUS_SCR );
-       // Multifunction routing register
-       pci_write_config32( dev, 0x8C, CONFIG_TI_PCMCIA_CARDBUS_MRR );
-       // Set Device Control Register (0x92) accordingly
-       pci_write_config8( dev, 0x92, pci_read_config8( dev, 0x92 ) | 0x02 );
-       return;
+
+       /* Command (offset 04) */
+       pci_write_config16(dev, 0x04, CONFIG_TI_PCMCIA_CARDBUS_CMDR);
+       /* Cache Line Size (offset 0x0C) */
+       pci_write_config8(dev, 0x0C, CONFIG_TI_PCMCIA_CARDBUS_CLSR);
+       /* CardBus latency timer (offset 0x1B) */
+       pci_write_config8(dev, 0x1B, CONFIG_TI_PCMCIA_CARDBUS_CLTR);
+       /* Bridge control (offset 0x3E) */
+       pci_write_config16(dev, 0x3E, CONFIG_TI_PCMCIA_CARDBUS_BCR);
+       /*
+        * Enable change sub-vendor ID. Clear the bit 5 to enable to write
+        * to the sub-vendor/device ids at 40 and 42.
+        */
+       pci_write_config32(dev, 0x80, 0x10);
+       pci_write_config32(dev, 0x40, PCI_VENDOR_ID_NOKIA);
+       /* Now write the correct value for SCR. */
+       /* System control (offset 0x80) */
+       pci_write_config32(dev, 0x80, CONFIG_TI_PCMCIA_CARDBUS_SCR);
+       /* Multifunction routing */
+       pci_write_config32(dev, 0x8C, CONFIG_TI_PCMCIA_CARDBUS_MRR);
+       /* Set the device control register (0x92) accordingly. */
+       pci_write_config8(dev, 0x92, pci_read_config8(dev, 0x92) | 0x02);
 }
 
-static struct device_operations ti_pci1x2y_ops  = {
+static struct device_operations ti_pci1x2y_ops = {
        .read_resources   = NULL, //pci_dev_read_resources,
        .set_resources    = pci_dev_set_resources,
        .enable_resources = pci_dev_enable_resources,
@@ -67,19 +69,19 @@ static struct device_operations ti_pci1x2y_ops  = {
 };
 
 static const struct pci_driver ti_pci1225_driver __pci_driver = {
-        .ops    = &ti_pci1x2y_ops,
-        .vendor = PCI_VENDOR_ID_TI,
-        .device = PCI_DEVICE_ID_TI_1225,
+       .ops    = &ti_pci1x2y_ops,
+       .vendor = PCI_VENDOR_ID_TI,
+       .device = PCI_DEVICE_ID_TI_1225,
 };
 
 static const struct pci_driver ti_pci1420_driver __pci_driver = {
-        .ops    = &ti_pci1x2y_ops,
-        .vendor = PCI_VENDOR_ID_TI,
-        .device = PCI_DEVICE_ID_TI_1420,
+       .ops    = &ti_pci1x2y_ops,
+       .vendor = PCI_VENDOR_ID_TI,
+       .device = PCI_DEVICE_ID_TI_1420,
 };
 
 static const struct pci_driver ti_pci1520_driver __pci_driver = {
-        .ops    = &ti_pci1x2y_ops,
-        .vendor = PCI_VENDOR_ID_TI,
-        .device = PCI_DEVICE_ID_TI_1420,
+       .ops    = &ti_pci1x2y_ops,
+       .vendor = PCI_VENDOR_ID_TI,
+       .device = PCI_DEVICE_ID_TI_1520,
 };