Use die() to assure the processor can't wake up from an interrupt.

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6224 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/northbridge/amd/gx2/pll_reset.c b/src/northbridge/amd/gx2/pll_reset.c
index 1f3c65dcbe32579c8ac4bd18f44e1bcde4218162..7b8694b6904638b70c6a404b13259034fe73e471 100644 (file)
--- a/src/northbridge/amd/gx2/pll_reset.c
+++ b/src/northbridge/amd/gx2/pll_reset.c
@@ -78,9 +78,8 @@ static void pll_reset(void)
        } else if (CONFIG_GX2_PROCESSOR_MHZ == 300) {
                DEFAULT_FBDIV = 18;
        } else {
-               printk(BIOS_ERR, "Unsupported GX2_PROCESSOR_MHZ setting!\n");
                post_code(POST_PLL_CPU_VER_FAIL);
-               __asm__ __volatile__("hlt\n");
+               die("Unsupported GX2_PROCESSOR_MHZ setting!\n");
        }
 
        /* clear the Bypass bit */
@@ -186,7 +185,7 @@ static void pll_reset(void)
 
                /* You should never get here..... The chip has reset. */
                post_code(POST_PLL_RESET_FAIL);
-               while (1);
+               die("CONFIGURING PLL FAILURE\n");
 
        } /* we haven't configured the PLL; do it now */
 

diff --git a/src/northbridge/amd/lx/pll_reset.c b/src/northbridge/amd/lx/pll_reset.c
index 1f8e499825607b06d7a31969110a5ba7c72dba92..3077b61c9caa5bccbf19816a8b3648a54da983c9 100644 (file)
--- a/src/northbridge/amd/lx/pll_reset.c
+++ b/src/northbridge/amd/lx/pll_reset.c
@@ -59,9 +59,8 @@ static void pll_reset(char manualconf)
                wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
 
                /* You should never get here..... The chip has reset. */
-               printk(BIOS_ERR, "CONFIGURING PLL FAILURE\n");
                post_code(POST_PLL_RESET_FAIL);
-               __asm__ __volatile__("hlt\n");
+               die("CONFIGURING PLL FAILURE\n");
 
        }
        printk(BIOS_DEBUG, "PLL configured.\n");