Revert r5902 to make code more readable again. At least three people like to

have this go away again.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Kevin O'Connor <kevin@koconnor.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6273 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 0bea56dbbfaf86cc3466db48ad147f29aba2e1cf..7f66f363efb6c592c9bc7a2b621a6ce5ceaa0fc0 100644 (file)
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -18,7 +18,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include <cpu/x86/car.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/mtrr.h>
 
@@ -46,7 +45,8 @@
  *   xmm3: Backup EBX
  */
 
-       save_bist_result()
+       /* Save the BIST result. */
+       movl    %eax, %ebp
 
        /*
         * For normal part %ebx already contain cpu_init_detected
@@ -56,7 +56,10 @@
 cache_as_ram_setup:
        post_code(0xa0)
 
-       enable_sse()
+       /* Enable SSE. */
+       movl    %cr4, %eax
+       orl     $(3 << 9), %eax
+       movl    %eax, %cr4
 
        /* Figure out the CPU family. */
        cvtsi2sd %ebx, %xmm3
@@ -321,7 +324,10 @@ wbcache_post_fam10_setup:
 
        post_code(0xa1)
 
-       enable_cache()
+       /* Enable cache. */
+       movl    %cr0, %eax
+       andl    $(~((1 << 30) | (1 << 29))), %eax
+       movl    %eax, %cr0
 
        jmp_if_k8(fam10_end_part1)
 
@@ -403,9 +409,13 @@ CAR_FAM10_ap_out:
 
        post_code(0xa5)
 
-       disable_sse()
+       /* Disable SSE. */
+       movl    %cr4, %eax
+       andl    $~(3 << 9), %eax
+       movl    %eax, %cr4
 
-       restore_bist_result()
+       /* Restore the BIST result. */
+       movl    %ebp, %eax
 
        /* We need to set EBP? No need. */
        movl    %esp, %ebp

diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc
index e228f4c4a07004125f2bc88b7c49dda0d5c54345..99c159977e5211b5ae438fc9ba9c7f000fea5918 100644 (file)
--- a/src/cpu/intel/car/cache_as_ram.inc
+++ b/src/cpu/intel/car/cache_as_ram.inc
@@ -21,7 +21,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include <cpu/x86/car.h>
 #include <cpu/x86/stack.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/lapic_def.h>
@@ -29,7 +28,8 @@
 #define CacheSize              CONFIG_DCACHE_RAM_SIZE
 #define CacheBase              (0xd0000 - CacheSize)
 
-       save_bist_result()
+       /* Save the BIST result. */
+       movl    %eax, %ebp
 
 CacheAsRam:
        /* Check whether the processor has HT capability. */
@@ -257,7 +257,10 @@ clear_fixed_var_mtrr_out:
        wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
 
-       enable_cache()
+       /* Enable cache. */
+       movl    %cr0, %eax
+       andl    $(~((1 << 30) | (1 << 29))), %eax
+       movl    %eax, %cr0
 
        /* Read the range with lodsl. */
        movl    $CacheBase, %esi
@@ -318,7 +321,8 @@ clear_fixed_var_mtrr_out:
        movl    $(CacheBase + CacheSize - 4), %eax
        movl    %eax, %esp
 lout:
-       restore_bist_result()
+       /* Restore the BIST result. */
+       movl    %ebp, %eax
 
        /* We need to set EBP? No need. */
        movl    %esp, %ebp
@@ -327,7 +331,10 @@ lout:
 
        /* We don't need CAR from now on. */
 
-       disable_cache()
+       /* Disable cache. */
+       movl    %cr0, %eax
+       orl     $(1 << 30), %eax
+       movl    %eax, %cr0
 
        /* Clear sth. */
        movl    $MTRRfix4K_C8000_MSR, %ecx
@@ -349,7 +356,10 @@ lout:
        movl    $0x00000800, %eax /* Enable variable and disable fixed MTRRs. */
        wrmsr
 
-       enable_cache();
+       /* Enable cache. */
+       movl    %cr0, %eax
+       andl    $(~((1 << 30) | (1 << 29))), %eax
+       movl    %eax, %cr0
 
        /* Clear boot_complete flag. */
        xorl    %ebp, %ebp

diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc
index 9b7cad0cf9150f7ed3b4c8efdac99875a011eaa1..d7dba8bf1b0c5b9a240deb6de4deb133302dd695 100644 (file)
--- a/src/cpu/intel/model_106cx/cache_as_ram.inc
+++ b/src/cpu/intel/model_106cx/cache_as_ram.inc
@@ -18,14 +18,14 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include <cpu/x86/car.h>
 #include <cpu/x86/stack.h>
 #include <cpu/x86/mtrr.h>
 
 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
 
-       save_bist_result()
+       /* Save the BIST result. */
+       movl    %eax, %ebp
 
 cache_as_ram:
        post_code(0x20)
@@ -66,12 +66,19 @@ clear_mtrrs:
        xorl    %edx, %edx
        wrmsr
 
-       enable_mtrr()
+       /* Enable MTRR. */
+       movl    $MTRRdefType_MSR, %ecx
+       rdmsr
+       orl     $(1 << 11), %eax
+       wrmsr
 
-       enable_l2_cache()
+       /* Enable L2 cache. */
+       movl    $0x11e, %ecx
+       rdmsr
+       orl     $(1 << 8), %eax
+       wrmsr
 
        /* Enable cache (CR0.CD = 0, CR0.NW = 0). */
-       /* TODO: enable_cache()? But that doesn't have "invd". */
         movl   %cr0, %eax
        andl    $(~((1 << 30) | (1 << 29))), %eax
        invd
@@ -86,7 +93,9 @@ clear_mtrrs:
        rep     stosl
 
        /* Enable Cache-as-RAM mode by disabling cache. */
-       disable_cache()
+       movl    %cr0, %eax
+       orl     $(1 << 30), %eax
+       movl    %eax, %cr0
 
 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
        /* Enable cache for our code in Flash because we do XIP here */
@@ -112,7 +121,10 @@ clear_mtrrs:
        wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
 
-       enable_cache()
+       /* Enable cache. */
+       movl    %cr0, %eax
+       andl    $(~((1 << 30) | (1 << 29))), %eax
+       movl    %eax, %cr0
 
        /* Set up the stack pointer. */
 #if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1)
@@ -123,8 +135,8 @@ clear_mtrrs:
 #endif
        movl    %eax, %esp
 
-       restore_bist_result()
-
+       /* Restore the BIST result. */
+       movl    %ebp, %eax
        movl    %esp, %ebp
        pushl   %eax
 
@@ -137,11 +149,18 @@ clear_mtrrs:
 
        post_code(0x30)
 
-       disable_cache()
+       /* Disable cache. */
+       movl    %cr0, %eax
+       orl     $(1 << 30), %eax
+       movl    %eax, %cr0
 
        post_code(0x31)
 
-       disable_mtrr()
+       /* Disable MTRR. */
+       movl    $MTRRdefType_MSR, %ecx
+       rdmsr
+       andl    $(~(1 << 11)), %eax
+       wrmsr
 
        post_code(0x31)
 
@@ -161,11 +180,17 @@ clear_mtrrs:
 
        post_code(0x33)
 
-       enable_cache()
+       /* Enable cache. */
+       movl    %cr0, %eax
+       andl    $~((1 << 30) | (1 << 29)), %eax
+       movl    %eax, %cr0
 
        post_code(0x36)
 
-       disable_cache()
+       /* Disable cache. */
+       movl    %cr0, %eax
+       orl     $(1 << 30), %eax
+       movl    %eax, %cr0
 
        post_code(0x38)
 
@@ -182,11 +207,17 @@ clear_mtrrs:
        post_code(0x39)
 
        /* And enable cache again after setting MTRRs. */
-       enable_cache()
+       movl    %cr0, %eax
+       andl    $~((1 << 30) | (1 << 29)), %eax
+       movl    %eax, %cr0
 
        post_code(0x3a)
 
-       enable_mtrr()
+       /* Enable MTRR. */
+       movl    $MTRRdefType_MSR, %ecx
+       rdmsr
+       orl     $(1 << 11), %eax
+       wrmsr
 
        post_code(0x3b)
 

diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index acd0427c516f432bee40eb89928159f5be5aaf9d..b077ff9a48b020b70a94dc6f27dd06d67850c87c 100644 (file)
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -18,14 +18,14 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include <cpu/x86/car.h>
 #include <cpu/x86/stack.h>
 #include <cpu/x86/mtrr.h>
 
 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
 
-       save_bist_result()
+       /* Save the BIST result. */
+       movl    %eax, %ebp
 
 cache_as_ram:
        post_code(0x20)
@@ -66,12 +66,19 @@ clear_mtrrs:
        movl    $0x0000000f, %edx
        wrmsr
 
-       enable_mtrr()
+       /* Enable MTRR. */
+       movl    $MTRRdefType_MSR, %ecx
+       rdmsr
+       orl     $(1 << 11), %eax
+       wrmsr
 
-       enable_l2_cache()
+       /* Enable L2 cache. */
+       movl    $0x11e, %ecx
+       rdmsr
+       orl     $(1 << 8), %eax
+       wrmsr
 
        /* Enable cache (CR0.CD = 0, CR0.NW = 0). */
-       /* TODO: enable_cache()? But that doesn't have "invd". */
         movl   %cr0, %eax
        andl    $(~((1 << 30) | (1 << 29))), %eax
        invd
@@ -86,7 +93,9 @@ clear_mtrrs:
        rep     stosl
 
        /* Enable Cache-as-RAM mode by disabling cache. */
-       disable_cache()
+       movl    %cr0, %eax
+       orl     $(1 << 30), %eax
+       movl    %eax, %cr0
 
 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
        /* Enable cache for our code in Flash because we do XIP here */
@@ -112,7 +121,10 @@ clear_mtrrs:
        wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
 
-       enable_cache()
+       /* Enable cache. */
+       movl    %cr0, %eax
+       andl    $(~((1 << 30) | (1 << 29))), %eax
+       movl    %eax, %cr0
 
        /* Set up the stack pointer. */
 #if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1)
@@ -123,8 +135,8 @@ clear_mtrrs:
 #endif
        movl    %eax, %esp
 
-       restore_bist_result()
-
+       /* Restore the BIST result. */
+       movl    %ebp, %eax
        movl    %esp, %ebp
        pushl   %eax
 
@@ -137,11 +149,18 @@ clear_mtrrs:
 
        post_code(0x30)
 
-       disable_cache()
+       /* Disable cache. */
+       movl    %cr0, %eax
+       orl     $(1 << 30), %eax
+       movl    %eax, %cr0
 
        post_code(0x31)
 
-       disable_mtrr()
+       /* Disable MTRR. */
+       movl    $MTRRdefType_MSR, %ecx
+       rdmsr
+       andl    $(~(1 << 11)), %eax
+       wrmsr
 
        post_code(0x31)
 
@@ -161,11 +180,17 @@ clear_mtrrs:
 
        post_code(0x33)
 
-       enable_cache()
+       /* Enable cache. */
+       movl    %cr0, %eax
+       andl    $~((1 << 30) | (1 << 29)), %eax
+       movl    %eax, %cr0
 
        post_code(0x36)
 
-       disable_cache()
+       /* Disable cache. */
+       movl    %cr0, %eax
+       orl     $(1 << 30), %eax
+       movl    %eax, %cr0
 
        post_code(0x38)
 
@@ -182,11 +207,17 @@ clear_mtrrs:
        post_code(0x39)
 
        /* And enable cache again after setting MTRRs. */
-       enable_cache()
+       movl    %cr0, %eax
+       andl    $~((1 << 30) | (1 << 29)), %eax
+       movl    %eax, %cr0
 
        post_code(0x3a)
 
-       enable_mtrr()
+       /* Enable MTRR. */
+       movl    $MTRRdefType_MSR, %ecx
+       rdmsr
+       orl     $(1 << 11), %eax
+       wrmsr
 
        post_code(0x3b)
 

diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc
index c270e4433026a26894b36a56a51b0a435c2bc051..3737429325fa8001e7f4c40a6b8ba5a498448ee5 100644 (file)
--- a/src/cpu/intel/model_6fx/cache_as_ram.inc
+++ b/src/cpu/intel/model_6fx/cache_as_ram.inc
@@ -18,14 +18,14 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include <cpu/x86/car.h>
 #include <cpu/x86/stack.h>
 #include <cpu/x86/mtrr.h>
 
 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
 
-       save_bist_result()
+       /* Save the BIST result. */
+       movl    %eax, %ebp
 
 cache_as_ram:
        post_code(0x20)
@@ -73,12 +73,19 @@ clear_mtrrs:
        movl    $0x0000000f, %edx
        wrmsr
 
-       enable_mtrr()
+       /* Enable MTRR. */
+       movl    $MTRRdefType_MSR, %ecx
+       rdmsr
+       orl     $(1 << 11), %eax
+       wrmsr
 
-       enable_l2_cache()
+       /* Enable L2 cache. */
+       movl    $0x11e, %ecx
+       rdmsr
+       orl     $(1 << 8), %eax
+       wrmsr
 
        /* Enable cache (CR0.CD = 0, CR0.NW = 0). */
-       /* TODO: enable_cache()? But that doesn't have "invd". */
         movl   %cr0, %eax
        andl    $(~((1 << 30) | (1 << 29))), %eax
        invd
@@ -93,7 +100,9 @@ clear_mtrrs:
        rep     stosl
 
        /* Enable Cache-as-RAM mode by disabling cache. */
-       disable_cache()
+       movl    %cr0, %eax
+       orl     $(1 << 30), %eax
+       movl    %eax, %cr0
 
 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
        /* Enable cache for our code in Flash because we do XIP here */
@@ -119,7 +128,10 @@ clear_mtrrs:
        wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
 
-       enable_cache()
+       /* Enable cache. */
+       movl    %cr0, %eax
+       andl    $(~((1 << 30) | (1 << 29))), %eax
+       movl    %eax, %cr0
 
        /* Set up the stack pointer. */
 #if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1)
@@ -130,8 +142,8 @@ clear_mtrrs:
 #endif
        movl    %eax, %esp
 
-       restore_bist_result()
-
+       /* Restore the BIST result. */
+       movl    %ebp, %eax
        movl    %esp, %ebp
        pushl   %eax
 
@@ -144,11 +156,18 @@ clear_mtrrs:
 
        post_code(0x30)
 
-       disable_cache()
+       /* Disable cache. */
+       movl    %cr0, %eax
+       orl     $(1 << 30), %eax
+       movl    %eax, %cr0
 
        post_code(0x31)
 
-       disable_mtrr()
+       /* Disable MTRR. */
+       movl    $MTRRdefType_MSR, %ecx
+       rdmsr
+       andl    $(~(1 << 11)), %eax
+       wrmsr
 
        post_code(0x31)
 
@@ -168,11 +187,17 @@ clear_mtrrs:
 
        post_code(0x33)
 
-       enable_cache()
+       /* Enable cache. */
+       movl    %cr0, %eax
+       andl    $~((1 << 30) | (1 << 29)), %eax
+       movl    %eax, %cr0
 
        post_code(0x36)
 
-       disable_cache()
+       /* Disable cache. */
+       movl    %cr0, %eax
+       orl     $(1 << 30), %eax
+       movl    %eax, %cr0
 
        post_code(0x38)
 
@@ -189,11 +214,17 @@ clear_mtrrs:
        post_code(0x39)
 
        /* And enable cache again after setting MTRRs. */
-       enable_cache()
+       movl    %cr0, %eax
+       andl    $~((1 << 30) | (1 << 29)), %eax
+       movl    %eax, %cr0
 
        post_code(0x3a)
 
-       enable_mtrr()
+       /* Enable MTRR. */
+       movl    $MTRRdefType_MSR, %ecx
+       rdmsr
+       orl     $(1 << 11), %eax
+       wrmsr
 
        post_code(0x3b)
 

diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
index c3c1cb76646a53ccdc4e985d2be6fa373c49c2de..fcd6c45e5f8f504fc81b5c73a10dd5a6371d3337 100644 (file)
--- a/src/cpu/via/car/cache_as_ram.inc
+++ b/src/cpu/via/car/cache_as_ram.inc
@@ -25,18 +25,21 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include <cpu/x86/car.h>
 #include <cpu/x86/stack.h>
 #include <cpu/x86/mtrr.h>
 
 #define CacheSize              CONFIG_DCACHE_RAM_SIZE
 #define CacheBase              CONFIG_DCACHE_RAM_BASE
 
-       save_bist_result()
+       /* Save the BIST result. */
+       movl    %eax, %ebp
 
 CacheAsRam:
 
-       disable_cache()
+       /* Disable cache. */
+       movl    %cr0, %eax
+       orl     $(1 << 30), %eax
+       movl    %eax, %cr0
        invd
 
        /* Set the default memory type and enable fixed and variable MTRRs. */
@@ -139,7 +142,10 @@ clear_fixed_var_mtrr_out:
        movl    $(MTRRdefTypeEn), %eax
        wrmsr
 
-       enable_cache()
+       /* Enable cache. */
+       movl    %cr0, %eax
+       andl    $(~((1 << 30) | (1 << 29))), %eax
+       movl    %eax, %cr0
 
        /* Read the range with lodsl. */
        cld
@@ -195,7 +201,8 @@ testok:
        jne     stackerr
 #endif
 
-       restore_bist_result()
+       /* Restore the BIST result. */
+       movl    %ebp, %eax
 
        /* We need to set EBP? No need. */
        movl    %esp, %ebp
@@ -210,7 +217,10 @@ testok:
 
        /* We don't need CAR from now on. */
 
-       disable_cache()
+       /* Disable cache. */
+       movl    %cr0, %eax
+       orl     $(1 << 30), %eax
+       movl    %eax, %cr0
 
        /* Set the default memory type and enable variable MTRRs. */
        /* TODO: Or also enable fixed MTRRs? Bug in the code? */
@@ -242,7 +252,10 @@ testok:
        movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
        wrmsr
 
-       enable_cache()
+       /* Enable cache. */
+       movl    %cr0, %eax
+       andl    $(~((1 << 30) | (1 << 29))), %eax
+       movl    %eax, %cr0
        invd
 
        /* Clear boot_complete flag. */

diff --git a/src/include/cpu/x86/car.h b/src/include/cpu/x86/car.h
deleted file mode 100644 (file)
index 45c62c6..0000000
--- a/src/include/cpu/x86/car.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
- * Copyright (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-#include <cpu/x86/mtrr.h>
-
-/* Save the BIST result. */
-#define save_bist_result() \
-       movl    %eax, %ebp
-
-/* Restore the BIST result. */
-#define restore_bist_result() \
-       movl    %ebp, %eax
-
-/* Enable cache. */
-#define enable_cache() \
-       movl    %cr0, %eax; \
-       andl    $(~((1 << 30) | (1 << 29))), %eax; \
-       movl    %eax, %cr0
-
-/* Disable cache. */
-#define disable_cache() \
-       movl    %cr0, %eax; \
-       orl     $(1 << 30), %eax; \
-       movl    %eax, %cr0
-
-/* Enable MTRR. */
-#define enable_mtrr() \
-       movl    $MTRRdefType_MSR, %ecx; \
-       rdmsr; \
-       orl     $(1 << 11), %eax; \
-       wrmsr
-
-/* Disable MTRR. */
-#define disable_mtrr() \
-       movl    $MTRRdefType_MSR, %ecx; \
-       rdmsr; \
-       andl    $(~(1 << 11)), %eax; \
-       wrmsr
-
-/* Enable L2 cache. */
-#define enable_l2_cache() \
-       movl    $0x11e, %ecx; \
-       rdmsr; \
-       orl     $(1 << 8), %eax; \
-       wrmsr
-
-/* Enable SSE. */
-#define enable_sse() \
-       movl    %cr4, %eax; \
-       orl     $(3 << 9), %eax; \
-       movl    %eax, %cr4
-
-/* Disable SSE. */
-#define disable_sse() \
-       movl    %cr4, %eax; \
-       andl    $~(3 << 9), %eax; \
-       movl    %eax, %cr4
-