Remove duplicated GX2 processor IIOC mode setting on CS5535 southbridge code

and fix CIS mode comments.

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6225 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/cpu/amd/model_gx2/cpureginit.c b/src/cpu/amd/model_gx2/cpureginit.c
index cfb86aa327be4338d8beb5a642ad9d7af7500b27..0fc852d531f2ff7c05985e426789e321c1afc16b 100644 (file)
--- a/src/cpu/amd/model_gx2/cpureginit.c
+++ b/src/cpu/amd/model_gx2/cpureginit.c
@@ -88,16 +88,13 @@ void cpuRegInit (void)
        msr.lo =  0x00000603C;
        wrmsr(msrnum, msr);
 
-/* Only do this if we are building for 5535 */
 /* FooGlue Setup */
-#if 1
-       /* Enable CIS mode B in FooGlue */
-       msrnum = MSR_FG + 0x10;
+       /* Set CS5535/CS5536 mode in FooGlue */
+       msrnum = FG_GIO_MSR_SEL;
        msr = rdmsr(msrnum);
        msr.lo &= ~3;
-       msr.lo |= 2;            /* ModeB */
+       msr.lo |= 2;            /* IIOC mode CS5535/CS5536 enable. (according to Jordan Crouse the databook is wrong bits 1:0 have to be 2 instead of 1) */
        wrmsr(msrnum, msr);
-#endif
 
 /* Disable DOT PLL. Graphics init will enable it if needed. */
        msrnum = GLCP_DOTPLL;

diff --git a/src/southbridge/amd/cs5535/early_setup.c b/src/southbridge/amd/cs5535/early_setup.c
index 1a612cc55fc45934831b8112ec822496aa8ab74d..4a2e1b49652b62bbde7f632767274aba408b544e 100644 (file)
--- a/src/southbridge/amd/cs5535/early_setup.c
+++ b/src/southbridge/amd/cs5535/early_setup.c
@@ -107,15 +107,11 @@ static void cs5535_setup_cis_mode(void)
 {
        msr_t msr;
 
-       /* setup CPU interface serial to mode C on both sides */
+       /* Setup CPU serial SouthBridge interface to mode C. */
        msr = rdmsr(GLPCI_SB_CTRL);
        msr.lo &= ~0x18;
        msr.lo |= 0x10;
        wrmsr(GLPCI_SB_CTRL, msr);
-       //Only do this if we are building for 5535
-       msr.lo = 0x2;
-       msr.hi = 0x0;
-       wrmsr(VIP_GIO_MSR_SEL, msr);
 }
 
 static void dummy(void)

diff --git a/src/southbridge/amd/cs5536/early_setup.c b/src/southbridge/amd/cs5536/early_setup.c
index 0a35964ef219f2d05bf38b8013e69eacb587cefe..7d982433d462554b9318aff7dd11572b63507bbb 100644 (file)
--- a/src/southbridge/amd/cs5536/early_setup.c
+++ b/src/southbridge/amd/cs5536/early_setup.c
@@ -145,7 +145,7 @@ static void cs5536_setup_cis_mode(void)
 {
        msr_t msr;
 
-       /* setup CPU interface serial to mode B to match CPU */
+       /* Setup CPU serial SouthBridge interface to mode C. */
        msr = rdmsr(GLPCI_SB_CTRL);
        msr.lo &= ~0x18;
        msr.lo |= 0x10;