#define PCI_DEVICE_ID_ATI_SB700_USB_19_2 0x4396
#define PCI_DEVICE_ID_ATI_SB700_USB_20_5 0x4399
+#define PCI_DEVICE_ID_ATI_SB800_LPC 0x439D
+#define PCI_DEVICE_ID_ATI_SB800_SATA 0x4390
+#define PCI_DEVICE_ID_ATI_SB800_IDE 0x439C
+#define PCI_DEVICE_ID_ATI_SB800_HDA 0x4383
+#define PCI_DEVICE_ID_ATI_SB800_PCI 0x4384
+#define PCI_DEVICE_ID_ATI_SB800_PCIEA 0x43A0
+#define PCI_DEVICE_ID_ATI_SB800_PCIEB 0x43A1
+#define PCI_DEVICE_ID_ATI_SB800_PCIEC 0x43A2
+#define PCI_DEVICE_ID_ATI_SB800_PCIED 0x43A3
+#define PCI_DEVICE_ID_ATI_SB800_SM 0x4385
+#define PCI_DEVICE_ID_ATI_SB800_USB_18_0 0x4397
+#define PCI_DEVICE_ID_ATI_SB800_USB_18_2 0x4396
+#define PCI_DEVICE_ID_ATI_SB800_USB_19_0 0x4397
+#define PCI_DEVICE_ID_ATI_SB800_USB_19_2 0x4396
+#define PCI_DEVICE_ID_ATI_SB800_USB_20_5 0x4399
+#define PCI_DEVICE_ID_ATI_SB800_USB_22_0 0x4397
+#define PCI_DEVICE_ID_ATI_SB800_USB_22_2 0x4396
+#define PCI_DEVICE_ID_ATI_SB800_GEC 0x1699
+
#define PCI_DEVICE_ID_ATI_RS690_HT 0x7910
#define PCI_DEVICE_ID_ATI_RS690_PCIE 0x7912
#define PCI_DEVICE_ID_ATI_RS690_PCIE_DEV2 0x7913
source src/southbridge/amd/sb600/Kconfig
source src/southbridge/amd/rs780/Kconfig
source src/southbridge/amd/sb700/Kconfig
+source src/southbridge/amd/cimx_wrapper/Kconfig
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5530) += cs5530
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5535) += cs5535
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5536) += cs5536
+subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_WRAPPER) += cimx_wrapper
--- /dev/null
+#\r
+# This file is part of the coreboot project.\r
+#\r
+# Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+#\r
+# This program is free software; you can redistribute it and/or modify\r
+# it under the terms of the GNU General Public License as published by\r
+# the Free Software Foundation; version 2 of the License.\r
+#\r
+# This program is distributed in the hope that it will be useful,\r
+# but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+# GNU General Public License for more details.\r
+#\r
+# You should have received a copy of the GNU General Public License\r
+# along with this program; if not, write to the Free Software\r
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+#\r
+#\r
+config SOUTHBRIDGE_AMD_CIMX_WRAPPER\r
+ bool\r
+ default n\r
+\r
+config SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800\r
+ bool\r
+ select IOAPIC\r
+ select SOUTHBRIDGE_AMD_CIMX_WRAPPER\r
+\r
+source src/southbridge/amd/cimx_wrapper/sb800/Kconfig\r
--- /dev/null
+#\r
+# This file is part of the coreboot project.\r
+#\r
+# Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+#\r
+# This program is free software; you can redistribute it and/or modify\r
+# it under the terms of the GNU General Public License as published by\r
+# the Free Software Foundation; version 2 of the License.\r
+#\r
+# This program is distributed in the hope that it will be useful,\r
+# but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+# GNU General Public License for more details.\r
+#\r
+# You should have received a copy of the GNU General Public License\r
+# along with this program; if not, write to the Free Software\r
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+#\r
+subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800) += sb800\r
--- /dev/null
+/*****************************************************************************\r
+ * AMD Generic Encapsulated Software Architecture */\r
+/**\r
+ * @file\r
+ *\r
+ * Agesa structures and definitions\r
+ *\r
+ * Contains AMD AGESA/CIMx core interface\r
+ *\r
+ * @xrefitem bom "File Content Label" "Release Content"\r
+ * @e project: AGESA\r
+ * @e sub-project: Include\r
+ * @e \$Revision:$ @e \$Date:$\r
+ */\r
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+\r
+\r
+#ifndef _AMD_H_\r
+#define _AMD_H_\r
+\r
+//\r
+//\r
+// AGESA Types and Definitions\r
+//\r
+//\r
+#ifndef NULL\r
+ #define NULL 0\r
+#endif\r
+\r
+\r
+#define LAST_ENTRY 0xFFFFFFFF\r
+#define IOCF8 0xCF8\r
+#define IOCFC 0xCFC\r
+#define IN\r
+#define OUT\r
+#define IMAGE_SIGNATURE 'DMA$'\r
+\r
+typedef UINTN AGESA_STATUS;\r
+\r
+\r
+#define AGESA_SUCCESS ((AGESA_STATUS) 0x0)\r
+#define AGESA_ALERT ((AGESA_STATUS) 0x40000000)\r
+#define AGESA_WARNING ((AGESA_STATUS) 0x40000001)\r
+#define AGESA_UNSUPPORTED ((AGESA_STATUS) 0x80000003)\r
+#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001)\r
+#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002)\r
+#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003)\r
+\r
+typedef AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr);\r
+typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT VOID* ConfigPtr);\r
+typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT VOID* ConfigPtr);\r
+\r
+///This allocation type is used by the AmdCreateStruct entry point\r
+typedef enum {\r
+ PreMemHeap = 0, ///< Create heap in cache.\r
+ PostMemDram, ///< Create heap in memory.\r
+ ByHost ///< Create heap by Host.\r
+} ALLOCATION_METHOD;\r
+\r
+/// These width descriptors are used by the library function, and others, to specify the data size\r
+typedef enum ACCESS_WIDTH {\r
+ AccessWidth8 = 1, ///< Access width is 8 bits.\r
+ AccessWidth16, ///< Access width is 16 bits.\r
+ AccessWidth32, ///< Access width is 32 bits.\r
+ AccessWidth64, ///< Access width is 64 bits.\r
+\r
+ AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data.\r
+ AccessS3SaveWidth16, ///< Save 16 bits data.\r
+ AccessS3SaveWidth32, ///< Save 32 bits data.\r
+ AccessS3SaveWidth64, ///< Save 64 bits data.\r
+} ACCESS_WIDTH;\r
+\r
+// AGESA Structures\r
+\r
+/// The standard header for all AGESA services.\r
+typedef struct _AMD_CONFIG_PARAMS {\r
+ IN UINT32 ImageBasePtr; ///< The AGESA Image base address.\r
+ IN UINT32 Func; ///< The service desired, @sa dispatch.h.\r
+ IN UINT32 AltImageBasePtr; ///< Alternate Image location\r
+ IN UINT32 PcieBasePtr; ///< PCIe MMIO Base address, if configured.\r
+ union { ///< Callback pointer\r
+ IN UINT64 PlaceHolder; ///< Place holder\r
+ IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA\r
+ } CALLBACK;\r
+ IN OUT UINT32 Reserved[2]; ///< This space is reserved for future use.\r
+} AMD_CONFIG_PARAMS;\r
+\r
+\r
+/// AGESA Binary module header structure\r
+typedef struct _AMD_IMAGE_HEADER {\r
+ IN UINT32 Signature; ///< Binary Signature\r
+ IN CHAR8 CreatorID[8]; ///< 8 characters ID\r
+ IN CHAR8 Version[12]; ///< 12 characters version\r
+ IN UINT32 ModuleInfoOffset; ///< Offset of module\r
+ IN UINT32 EntryPointAddress; ///< Entry address\r
+ IN UINT32 ImageBase; ///< Image base\r
+ IN UINT32 RelocTableOffset; ///< Relocate Table offset\r
+ IN UINT32 ImageSize; ///< Size\r
+ IN UINT16 Checksum; ///< Checksum\r
+ IN UINT8 ImageType; ///< Type\r
+ IN UINT8 V_Reserved; ///< Reserved\r
+} AMD_IMAGE_HEADER;\r
+\r
+/// AGESA Binary module header structure\r
+typedef struct _AMD_MODULE_HEADER {\r
+ IN UINT32 ModuleHeaderSignature; ///< Module signature\r
+ IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID\r
+ IN CHAR8 ModuleVersion[12]; ///< 12 characters version\r
+ IN MODULE_ENTRY ModuleDispatcherPtr; ///< A pointer point to dispatcher\r
+ IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link\r
+} AMD_MODULE_HEADER;\r
+\r
+\r
+#define FUNC_0 0 // bit-placed for PCI address creation\r
+#define FUNC_1 1\r
+#define FUNC_2 2\r
+#define FUNC_3 3\r
+#define FUNC_4 4\r
+#define FUNC_5 5\r
+#define FUNC_6 6\r
+#define FUNC_7 7\r
+\r
+// SBDFO - Segment Bus Device Function Offset\r
+// 31:28 Segment (4-bits)\r
+// 27:20 Bus (8-bits)\r
+// 19:15 Device (5-bits)\r
+// 14:12 Function (3-bits)\r
+// 11:00 Offset (12-bits)\r
+\r
+#if 0\r
+#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \\r
+ (((UINT32) (Dev)) << 15) | (((UINT32) (Fun)) << 12) | ((UINT32) (Off)))\r
+#endif\r
+#define ILLEGAL_SBDFO 0xFFFFFFFF\r
+\r
+/// CPUID data received registers format\r
+typedef struct _SB_CPUID_DATA {\r
+ IN OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX\r
+ IN OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX\r
+ IN OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX\r
+ IN OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX\r
+} SB_CPUID_DATA;\r
+\r
+#define WARM_RESET 1\r
+#define COLD_RESET 2 // Cold reset\r
+#define RESET_CPU 4 // Triggers a CPU reset\r
+\r
+/// HT frequency for external callbacks\r
+typedef enum {\r
+ HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks\r
+ HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks\r
+ HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks\r
+ HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks\r
+ HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks\r
+ HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks\r
+ HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks\r
+ HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks\r
+ HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks\r
+ HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks\r
+ HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks\r
+ HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks\r
+ HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks\r
+ HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks\r
+ HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks\r
+ HT_FREQUENCY_3200M = 19 ///< HT speed 3200 for external callbacks\r
+} HT_FREQUENCIES;\r
+\r
+#ifndef BIT0\r
+ #define BIT0 0x0000000000000001ull\r
+#endif\r
+#ifndef BIT1\r
+ #define BIT1 0x0000000000000002ull\r
+#endif\r
+#ifndef BIT2\r
+ #define BIT2 0x0000000000000004ull\r
+#endif\r
+#ifndef BIT3\r
+ #define BIT3 0x0000000000000008ull\r
+#endif\r
+#ifndef BIT4\r
+ #define BIT4 0x0000000000000010ull\r
+#endif\r
+#ifndef BIT5\r
+ #define BIT5 0x0000000000000020ull\r
+#endif\r
+#ifndef BIT6\r
+ #define BIT6 0x0000000000000040ull\r
+#endif\r
+#ifndef BIT7\r
+ #define BIT7 0x0000000000000080ull\r
+#endif\r
+#ifndef BIT8\r
+ #define BIT8 0x0000000000000100ull\r
+#endif\r
+#ifndef BIT9\r
+ #define BIT9 0x0000000000000200ull\r
+#endif\r
+#ifndef BIT10\r
+ #define BIT10 0x0000000000000400ull\r
+#endif\r
+#ifndef BIT11\r
+ #define BIT11 0x0000000000000800ull\r
+#endif\r
+#ifndef BIT12\r
+ #define BIT12 0x0000000000001000ull\r
+#endif\r
+#ifndef BIT13\r
+ #define BIT13 0x0000000000002000ull\r
+#endif\r
+#ifndef BIT14\r
+ #define BIT14 0x0000000000004000ull\r
+#endif\r
+#ifndef BIT15\r
+ #define BIT15 0x0000000000008000ull\r
+#endif\r
+#ifndef BIT16\r
+ #define BIT16 0x0000000000010000ull\r
+#endif\r
+#ifndef BIT17\r
+ #define BIT17 0x0000000000020000ull\r
+#endif\r
+#ifndef BIT18\r
+ #define BIT18 0x0000000000040000ull\r
+#endif\r
+#ifndef BIT19\r
+ #define BIT19 0x0000000000080000ull\r
+#endif\r
+#ifndef BIT20\r
+ #define BIT20 0x0000000000100000ull\r
+#endif\r
+#ifndef BIT21\r
+ #define BIT21 0x0000000000200000ull\r
+#endif\r
+#ifndef BIT22\r
+ #define BIT22 0x0000000000400000ull\r
+#endif\r
+#ifndef BIT23\r
+ #define BIT23 0x0000000000800000ull\r
+#endif\r
+#ifndef BIT24\r
+ #define BIT24 0x0000000001000000ull\r
+#endif\r
+#ifndef BIT25\r
+ #define BIT25 0x0000000002000000ull\r
+#endif\r
+#ifndef BIT26\r
+ #define BIT26 0x0000000004000000ull\r
+#endif\r
+#ifndef BIT27\r
+ #define BIT27 0x0000000008000000ull\r
+#endif\r
+#ifndef BIT28\r
+ #define BIT28 0x0000000010000000ull\r
+#endif\r
+#ifndef BIT29\r
+ #define BIT29 0x0000000020000000ull\r
+#endif\r
+#ifndef BIT30\r
+ #define BIT30 0x0000000040000000ull\r
+#endif\r
+#ifndef BIT31\r
+ #define BIT31 0x0000000080000000ull\r
+#endif\r
+#ifndef BIT32\r
+ #define BIT32 0x0000000100000000ull\r
+#endif\r
+#ifndef BIT33\r
+ #define BIT33 0x0000000200000000ull\r
+#endif\r
+#ifndef BIT34\r
+ #define BIT34 0x0000000400000000ull\r
+#endif\r
+#ifndef BIT35\r
+ #define BIT35 0x0000000800000000ull\r
+#endif\r
+#ifndef BIT36\r
+ #define BIT36 0x0000001000000000ull\r
+#endif\r
+#ifndef BIT37\r
+ #define BIT37 0x0000002000000000ull\r
+#endif\r
+#ifndef BIT38\r
+ #define BIT38 0x0000004000000000ull\r
+#endif\r
+#ifndef BIT39\r
+ #define BIT39 0x0000008000000000ull\r
+#endif\r
+#ifndef BIT40\r
+ #define BIT40 0x0000010000000000ull\r
+#endif\r
+#ifndef BIT41\r
+ #define BIT41 0x0000020000000000ull\r
+#endif\r
+#ifndef BIT42\r
+ #define BIT42 0x0000040000000000ull\r
+#endif\r
+#ifndef BIT43\r
+ #define BIT43 0x0000080000000000ull\r
+#endif\r
+#ifndef BIT44\r
+ #define BIT44 0x0000100000000000ull\r
+#endif\r
+#ifndef BIT45\r
+ #define BIT45 0x0000200000000000ull\r
+#endif\r
+#ifndef BIT46\r
+ #define BIT46 0x0000400000000000ull\r
+#endif\r
+#ifndef BIT47\r
+ #define BIT47 0x0000800000000000ull\r
+#endif\r
+#ifndef BIT48\r
+ #define BIT48 0x0001000000000000ull\r
+#endif\r
+#ifndef BIT49\r
+ #define BIT49 0x0002000000000000ull\r
+#endif\r
+#ifndef BIT50\r
+ #define BIT50 0x0004000000000000ull\r
+#endif\r
+#ifndef BIT51\r
+ #define BIT51 0x0008000000000000ull\r
+#endif\r
+#ifndef BIT52\r
+ #define BIT52 0x0010000000000000ull\r
+#endif\r
+#ifndef BIT53\r
+ #define BIT53 0x0020000000000000ull\r
+#endif\r
+#ifndef BIT54\r
+ #define BIT54 0x0040000000000000ull\r
+#endif\r
+#ifndef BIT55\r
+ #define BIT55 0x0080000000000000ull\r
+#endif\r
+#ifndef BIT56\r
+ #define BIT56 0x0100000000000000ull\r
+#endif\r
+#ifndef BIT57\r
+ #define BIT57 0x0200000000000000ull\r
+#endif\r
+#ifndef BIT58\r
+ #define BIT58 0x0400000000000000ull\r
+#endif\r
+#ifndef BIT59\r
+ #define BIT59 0x0800000000000000ull\r
+#endif\r
+#ifndef BIT60\r
+ #define BIT60 0x1000000000000000ull\r
+#endif\r
+#ifndef BIT61\r
+ #define BIT61 0x2000000000000000ull\r
+#endif\r
+#ifndef BIT62\r
+ #define BIT62 0x4000000000000000ull\r
+#endif\r
+#ifndef BIT63\r
+ #define BIT63 0x8000000000000000ull\r
+#endif\r
+#endif\r
--- /dev/null
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+\r
+#ifndef _AMD_SB_LIB_H_\r
+#define _AMD_SB_LIB_H_\r
+\r
+typedef CHAR8 *va_list;\r
+#ifndef _INTSIZEOF\r
+ #define _INTSIZEOF (n) ( (sizeof (n) + sizeof (UINTN) - 1) & ~(sizeof (UINTN) - 1) )\r
+#endif\r
+\r
+// Also support coding convention rules for var arg macros\r
+#ifndef va_start\r
+ #define va_start(ap, v) ( ap = (va_list)&(v) + _INTSIZEOF (v) )\r
+#endif\r
+#define va_arg(ap, t) ( *(t *) ((ap += _INTSIZEOF (t)) - _INTSIZEOF (t)) )\r
+#define va_end(ap) ( ap = (va_list)0 )\r
+\r
+\r
+#pragma pack (push, 1)\r
+\r
+#define IMAGE_ALIGN 32*1024\r
+#define NUM_IMAGE_LOCATION 32\r
+\r
+//Entry Point Call\r
+typedef void (*CIM_IMAGE_ENTRY) (void* pConfig);\r
+\r
+//Hook Call\r
+\r
+typedef struct _CIMFILEHEADER\r
+{\r
+ UINT32 AMDLogo;\r
+ UINT64 CreatorID;\r
+ UINT32 Version1;\r
+ UINT32 Version2;\r
+ UINT32 Version3;\r
+ UINT32 ModuleInfoOffset;\r
+ UINT32 EntryPoint;\r
+ UINT32 ImageBase;\r
+ UINT32 RelocTableOffset;\r
+ UINT32 ImageSize;\r
+ UINT16 CheckSum;\r
+ UINT8 ImageType;\r
+ UINT8 Reserved2;\r
+} CIMFILEHEADER;\r
+\r
+#ifndef BIT0\r
+ #define BIT0 (1 << 0)\r
+#endif\r
+#ifndef BIT1\r
+ #define BIT1 (1 << 1)\r
+#endif\r
+#ifndef BIT2\r
+ #define BIT2 (1 << 2)\r
+#endif\r
+#ifndef BIT3\r
+ #define BIT3 (1 << 3)\r
+#endif\r
+#ifndef BIT4\r
+ #define BIT4 (1 << 4)\r
+#endif\r
+#ifndef BIT5\r
+ #define BIT5 (1 << 5)\r
+#endif\r
+#ifndef BIT6\r
+ #define BIT6 (1 << 6)\r
+#endif\r
+#ifndef BIT7\r
+ #define BIT7 (1 << 7)\r
+#endif\r
+#ifndef BIT8\r
+ #define BIT8 (1 << 8)\r
+#endif\r
+#ifndef BIT9\r
+ #define BIT9 (1 << 9)\r
+#endif\r
+#ifndef BIT10\r
+ #define BIT10 (1 << 10)\r
+#endif\r
+#ifndef BIT11\r
+ #define BIT11 (1 << 11)\r
+#endif\r
+#ifndef BIT12\r
+ #define BIT12 (1 << 12)\r
+#endif\r
+#ifndef BIT13\r
+ #define BIT13 (1 << 13)\r
+#endif\r
+#ifndef BIT14\r
+ #define BIT14 (1 << 14)\r
+#endif\r
+#ifndef BIT15\r
+ #define BIT15 (1 << 15)\r
+#endif\r
+#ifndef BIT16\r
+ #define BIT16 (1 << 16)\r
+#endif\r
+#ifndef BIT17\r
+ #define BIT17 (1 << 17)\r
+#endif\r
+#ifndef BIT18\r
+ #define BIT18 (1 << 18)\r
+#endif\r
+#ifndef BIT19\r
+ #define BIT19 (1 << 19)\r
+#endif\r
+#ifndef BIT20\r
+ #define BIT20 (1 << 20)\r
+#endif\r
+#ifndef BIT21\r
+ #define BIT21 (1 << 21)\r
+#endif\r
+#ifndef BIT22\r
+ #define BIT22 (1 << 22)\r
+#endif\r
+#ifndef BIT23\r
+ #define BIT23 (1 << 23)\r
+#endif\r
+#ifndef BIT24\r
+ #define BIT24 (1 << 24)\r
+#endif\r
+#ifndef BIT25\r
+ #define BIT25 (1 << 25)\r
+#endif\r
+#ifndef BIT26\r
+ #define BIT26 (1 << 26)\r
+#endif\r
+#ifndef BIT27\r
+ #define BIT27 (1 << 27)\r
+#endif\r
+#ifndef BIT28\r
+ #define BIT28 (1 << 28)\r
+#endif\r
+#ifndef BIT29\r
+ #define BIT29 (1 << 29)\r
+#endif\r
+#ifndef BIT30\r
+ #define BIT30 (1 << 30)\r
+#endif\r
+#ifndef BIT31\r
+ #define BIT31 (1 << 31)\r
+#endif\r
+\r
+#pragma pack (pop)\r
+\r
+typedef enum\r
+{\r
+ AccWidthUint8 = 0,\r
+ AccWidthUint16,\r
+ AccWidthUint32,\r
+} ACC_WIDTH;\r
+\r
+#define S3_SAVE 0x80\r
+\r
+#endif\r
--- /dev/null
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Advanced Micro Devices, Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+
+if SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800
+config BOOTBLOCK_SOUTHBRIDGE_INIT
+ string
+ default "southbridge/amd/cimx_wrapper/sb800/bootblock.c"
+endif #SOUTHBRIDGE_AMD_CIMX_WRAPPER_SB800
+
--- /dev/null
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2010 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+#
+
+subdirs-y += ../../../../../src/vendorcode/amd/cimx/sb800
+#TODO: merge with agesa lib function
+subdirs-y += ../../../../../src/vendorcode/amd/cimx/lib
+
+# SB800 Platform Files
+
+romstage-y += sb800_cfg.c
+romstage-y += sb800_early.c
+romstage-y += sb800_smbus.c
+
+ramstage-y += sb800_cfg.c
+ramstage-y += sb800_late.c
+
+driver-y += sb800_smbus.c
+driver-y += sb800_lpc.c
+
--- /dev/null
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+\r
+#ifndef _AMD_SBPLATFORM_H_\r
+#define _AMD_SBPLATFORM_H_\r
+\r
+#include "cbtypes.h"\r
+typedef UINT64 PLACEHOLDER;\r
+#include "Amdlib.h"\r
+#include "Amd.h"\r
+#include "amdlib32.h"//TODO merge with agesa wrapper\r
+#include "SB800.h"\r
+#include "SBTYPE.h"\r
+#include "ACPILIB.h"\r
+#include "SBDEF.h"\r
+#include "AMDSBLIB.h"\r
+#include "SBSUBFUN.h"\r
+#include "OEM.h"\r
+\r
+#ifdef NULL\r
+ #undef NULL\r
+#endif\r
+#define NULL 0\r
+\r
+#ifndef SBOEM_ACPI_RESTORE_SWSMI\r
+ #define SBOEM_BEFORE_PCI_RESTORE_SWSMI 0xD3\r
+ #define SBOEM_AFTER_PCI_RESTORE_SWSMI 0xD4\r
+#endif\r
+\r
+#ifndef _AMD_NB_CIM_X_PROTOCOL_H_\r
+\r
+/// Extended PCI Address\r
+typedef struct _EXT_PCI_ADDR {\r
+ UINT32 Reg :16; ///< / PCI Register\r
+ UINT32 Func:3; ///< / PCI Function\r
+ UINT32 Dev :5; ///< / PCI Device\r
+ UINT32 Bus :8; ///< / PCI Address\r
+} EXT_PCI_ADDR;\r
+\r
+/// PCI Address\r
+typedef union _PCI_ADDR {\r
+ UINT32 ADDR; ///< / 32 bit Address\r
+ EXT_PCI_ADDR Addr; ///< / Extended PCI Address\r
+} PCI_ADDR;\r
+#endif\r
+\r
+#define FIXUP_PTR(ptr) ptr\r
+\r
+\r
+\r
+\r
+//------------------------------------------------------------------------------------------------------------------------//\r
+/**\r
+ * SB_CIMx_PARAMETER 0 1 2 Defult Value When CIMx Take over\r
+ * SpreadSpectrum CIMx take over User (Setup Option) User (Setup Option) Enable\r
+ * SpreadSpectrumType CIMx take over User (Setup Option) User (Setup Option) Normal\r
+ * HpetTimer CIMx take over User (Setup Option) User (Setup Option) Enable\r
+ * HpetMsiDis CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)\r
+ * IrConfig CIMx take over User (Setup Option) User (Setup Option) Disable (0x00)\r
+ * SpiFastReadEnable CIMx take over User (Setup Option) User (Setup Option) Disable\r
+ * SpiFastReadSpeed CIMx take over User (Setup Option) User (Setup Option) Disable (NULL)\r
+ * NbSbGen2 CIMx take over User (Setup Option) User (Setup Option) Enable\r
+ * AlinkPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable\r
+ * ResetCpuOnSyncFlood CIMx take over User (Setup Option) User (Setup Option) Enable\r
+ * GppGen2 CIMx take over User (Setup Option) User (Setup Option) Disable\r
+ * GppMemWrImprove CIMx take over User (Setup Option) User (Setup Option) Enable\r
+ * GppPortAspm CIMx take over User (Setup Option) User (Setup Option) Disable\r
+ * GppLaneReversal CIMx take over User (Setup Option) User (Setup Option) Disable\r
+ * GppPhyPllPowerDown CIMx take over User (Setup Option) User (Setup Option) Enable\r
+ * UsbPhyPowerDown CIMx take over User (Setup Option) User (Setup Option) Disable\r
+ * SBGecDebugBus CIMx take over User (Setup Option) User (Setup Option) Disable\r
+ * SBGecPwr CIMx take over User (Setup Option) User (Setup Option) Nerver Power down (0x11)\r
+ * SataSetMaxGen2 CIMx take over User (Setup Option) User (Setup Option) Max Gen3 (0x00)\r
+ * SataClkMode CIMx take over User (Setup Option) User (Setup Option) 0x90 int. 100Mhz\r
+ * SataAggrLinkPmCap CIMx take over User (Setup Option) User (Setup Option) Enable\r
+ * SataPortMultCap CIMx take over User (Setup Option) User (Setup Option) Enable\r
+ * SataPscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)\r
+ * SataSscCap CIMx take over User (Setup Option) User (Setup Option) Enable (0x00)\r
+ * SataFisBasedSwitching CIMx take over User (Setup Option) User (Setup Option) Disable\r
+ * SataCccSupport CIMx take over User (Setup Option) User (Setup Option) Disable\r
+ * SataMsiCapability CIMx take over User (Setup Option) User (Setup Option) Enable\r
+ * SataClkAutoOff CIMx take over User (Setup Option) User (Setup Option) Disable\r
+ * AcDcMsg CIMx take over User (Setup Option) User (Setup Option) Disable\r
+ * TimerTickTrack CIMx take over User (Setup Option) User (Setup Option) Disable\r
+ * ClockInterruptTag CIMx take over User (Setup Option) User (Setup Option) Disable\r
+ * OhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable\r
+ * EhciTrafficHanding CIMx take over User (Setup Option) User (Setup Option) Disable\r
+ * FusionMsgCMultiCore CIMx take over User (Setup Option) User (Setup Option) Disable\r
+ * FusionMsgCStage CIMx take over User (Setup Option) User (Setup Option) Disable\r
+ */\r
+#define SB_CIMx_PARAMETER 0x02\r
+\r
+// Generic \r
+#define cimSpreadSpectrumDefault TRUE\r
+#define cimSpreadSpectrumTypeDefault 0x00 // Normal\r
+#define cimHpetTimerDefault TRUE\r
+#define cimHpetMsiDisDefault FALSE // Enable\r
+#define cimIrConfigDefault 0x00 // Disable\r
+#define cimSpiFastReadEnableDefault 0x00 // Disable\r
+#define cimSpiFastReadSpeedDefault 0x00 // NULL\r
+// GPP/AB Controller \r
+#define cimNbSbGen2Default TRUE\r
+#define cimAlinkPhyPllPowerDownDefault TRUE\r
+#define cimResetCpuOnSyncFloodDefault TRUE\r
+#define cimGppGen2Default FALSE\r
+#define cimGppMemWrImproveDefault TRUE\r
+#define cimGppPortAspmDefault FALSE\r
+#define cimGppLaneReversalDefault FALSE\r
+#define cimGppPhyPllPowerDownDefault TRUE \r
+// USB Controller\r
+#define cimUsbPhyPowerDownDefault FALSE\r
+// GEC Controller\r
+#define cimSBGecDebugBusDefault FALSE\r
+#define cimSBGecPwrDefault 0x03\r
+// Sata Controller \r
+#define cimSataSetMaxGen2Default 0x00\r
+#define cimSATARefClkSelDefault 0x10\r
+#define cimSATARefDivSelDefault 0x80\r
+#define cimSataAggrLinkPmCapDefault TRUE\r
+#define cimSataPortMultCapDefault TRUE\r
+#define cimSataPscCapDefault 0x00 // Enable\r
+#define cimSataSscCapDefault 0x00 // Enable\r
+#define cimSataFisBasedSwitchingDefault FALSE \r
+#define cimSataCccSupportDefault FALSE\r
+#define cimSataClkAutoOffDefault FALSE\r
+#define cimNativepciesupportDefault FALSE\r
+// Fusion Related \r
+#define cimAcDcMsgDefault FALSE\r
+#define cimTimerTickTrackDefault FALSE\r
+#define cimClockInterruptTagDefault FALSE\r
+#define cimOhciTrafficHandingDefault FALSE\r
+#define cimEhciTrafficHandingDefault FALSE\r
+#define cimFusionMsgCMultiCoreDefault FALSE\r
+#define cimFusionMsgCStageDefault FALSE\r
+\r
+#endif // _AMD_SBPLATFORM_H_\r
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#ifndef _CIMX_SB_EARLY_H_
+#define _CIMX_SB_EARLY_H_
+
+/**
+ * @brief Get SouthBridge device number, called by finalize_node_setup()
+ * @param[in] bus target bus number
+ * @return southbridge device number
+ */
+u32 get_sbdn(u32 bus);
+
+/**
+ * South Bridge CIMx romstage entry, sbPowerOnInit entry point wrapper.
+ */
+void sb_poweron_init(void);
+//void sb_before_pci_init(void);
+
+#endif
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+
+
+#if CONFIG_SERIAL_POST == 1
+
+/* Data */
+#define UART_RBR 0x00
+#define UART_TBR 0x00
+
+/* Control */
+#define UART_IER 0x01
+#define UART_IIR 0x02
+#define UART_FCR 0x02
+#define UART_LCR 0x03
+#define UART_MCR 0x04
+#define UART_DLL 0x00
+#define UART_DLM 0x01
+
+/* Status */
+#define UART_LSR 0x05
+#define UART_MSR 0x06
+#define UART_SCR 0x07
+
+#ifndef CONFIG_TTYS0_DIV
+#if ((115200%CONFIG_TTYS0_BAUD) != 0)
+#error Bad ttys0 baud rate
+#endif
+#define CONFIG_TTYS0_DIV (115200/CONFIG_TTYS0_BAUD)
+#endif // CONFIG_TTYS0_DIV
+
+#define UART_LCS CONFIG_TTYS0_LCS
+
+#endif // CONFIG_SERIAL_POST == 1
+
+
+static void sb800_enable_rom(void)
+{
+ u32 word;
+ u32 dword;
+ device_t dev;
+
+ dev = PCI_DEV(0, 0x14, 0x03);
+ /* SB800 LPC Bridge 0:20:3:44h.
+ * BIT6: Port Enable for serial port 0x3f8-0x3ff
+ * BIT29: Port Enable for KBC port 0x60 and 0x64
+ * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62
+ */
+ dword = pci_io_read_config32(dev, 0x44);
+ //dword |= (1<<6) | (1<<29) | (1<<30) ;
+ /*Turn on all of LPC IO Port decode enable */
+ dword = 0xffffffff;
+ pci_io_write_config32(dev, 0x44, dword);
+
+ /* SB800 LPC Bridge 0:20:3:48h.
+ * BIT0: Port Enable for SuperIO 0x2E-0x2F
+ * BIT1: Port Enable for SuperIO 0x4E-0x4F
+ * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C)
+ * BIT6: Port Enable for RTC IO 0x70-0x73
+ * BIT21: Port Enable for Port 0x80
+ */
+ dword = pci_io_read_config32(dev, 0x48);
+ dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ;
+ pci_io_write_config32(dev, 0x48, dword);
+
+ /* Enable 2MB rom access at 0xFFE00000 - 0xFFFFFFFF */
+ /* Set the 2MB enable bits */
+ word = pci_io_read_config16(dev, 0x6c);
+ word = 0xFFE0;
+ pci_io_write_config16(dev, 0x6c, word);
+}
+
+
+static void uart_init(void)
+{
+#if CONFIG_SERIAL_POST == 1
+ /* disable interrupts */
+ outb(0x0, CONFIG_TTYS0_BASE + UART_IER);
+ /* enable fifo's */
+ outb(0x01, CONFIG_TTYS0_BASE + UART_FCR);
+ /* Set Baud Rate Divisor to 12 ==> 115200 Baud */
+ outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
+ outb(CONFIG_TTYS0_DIV & 0xFF, CONFIG_TTYS0_BASE + UART_DLL);
+ outb((CONFIG_TTYS0_DIV >> 8) & 0xFF, CONFIG_TTYS0_BASE + UART_DLM);
+ outb(UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
+#endif // CONFIG_SERIAL_POST == 1
+}
+
+
+static void bootblock_southbridge_init(void)
+{
+ /* Setup the rom access for 2M */
+ sb800_enable_rom();
+ uart_init();
+}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _CBTYPES_H_
+#define _CBTYPES_H_
+
+//#include <stdint.h>
+
+typedef signed long long __int64;
+typedef void VOID;
+typedef unsigned int UINTN;
+typedef signed char CHAR8;
+typedef unsigned char UINT8;
+typedef unsigned short UINT16;
+typedef unsigned int UINT32;
+typedef unsigned long long UINT64;
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+
+#ifndef FALSE
+#define FALSE 0
+#endif
+typedef unsigned char BOOLEAN;
+
+#ifndef VOLATILE
+#define VOLATILE volatile
+#endif
+
+#ifndef IN
+#define IN
+#endif
+#ifndef OUT
+#define OUT
+#endif
+
+#endif
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _CIMX_WRAPPER_SB800_CHIP_H_
+#define _CIMX_WRAPPER_SB800_CHIP_H_
+
+extern struct chip_operations southbridge_amd_cimx_wrapper_sb800_ops;
+
+/*
+ * configuration set in mainboard/devicetree.cb
+ * boot_switch_sata_ide:
+ * 0 -set SATA as primary, PATA(IDE) as secondary.
+ * 1 -set PATA(IDE) as primary, SATA as secondary. if you want to boot from IDE,
+ * gpp_configuration - The configuration of General Purpose Port A/B/C/D
+ * 0(GPP_CFGMODE_X4000) -PortA Lanes[3:0]
+ * 2(GPP_CFGMODE_X2200) -PortA Lanes[1:0], PortB Lanes[3:2]
+ * 3(GPP_CFGMODE_X2110) -PortA Lanes[1:0], PortB Lane2, PortC Lane3
+ * 4(GPP_CFGMODE_X1111) -PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
+ */
+struct southbridge_amd_cimx_wrapper_sb800_config
+{
+ u32 boot_switch_sata_ide : 1;
+ u8 gpp_configuration;
+};
+
+#endif /* _CIMX_WRAPPER_SB800_CHIP_H_ */
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations southbridge_amd_cimx_wrapper_sb800_ops = {
+ CHIP_NAME("AMD South Bridge SB800")
+};
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#include "SBPLATFORM.h"
+#include "sb800_cfg.h"
+
+
+/**
+ * @brief South Bridge CIMx configuration
+ *
+ * should be called before exeucte CIMx function.
+ * this function will be called in romstage and ramstage.
+ */
+void sb800_cimx_config(AMDSBCFG *sb_config)
+{
+ if (!sb_config) {
+ return;
+ }
+ //memset(sb_config, 0, sizeof(AMDSBCFG));
+
+ /* header */
+ sb_config->StdHeader.PcieBasePtr = PCIEX_BASE_ADDRESS;
+
+ /* static Build Parameters */
+ sb_config->BuildParameters.BiosSize = BIOS_SIZE;
+ sb_config->BuildParameters.LegacyFree = LEGACY_FREE;
+ sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS;
+ sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS;
+ sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS;
+ sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS;
+ sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS;
+ sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS;
+ sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS;
+ sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS;
+ sb_config->BuildParameters.GecShadowRomBase = GEC_BASE_ADDRESS;
+ sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS;
+ sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS;
+ sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID;
+ sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID;
+ sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID;
+ sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID;
+ sb_config->BuildParameters.OhciSsid = OHCI_SSID;
+ sb_config->BuildParameters.EhciSsid = EHCI_SSID;
+ sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID;
+ sb_config->BuildParameters.SmbusSsid = SMBUS_SSID;
+ sb_config->BuildParameters.IdeSsid = IDE_SSID;
+ sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID;
+ sb_config->BuildParameters.LpcSsid = LPC_SSID;
+ sb_config->BuildParameters.PCIBSsid = PCIB_SSID;
+ sb_config->BuildParameters.SpreadSpectrumType = Spread_Spectrum_Type;
+ sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS;
+
+ /* General */
+ sb_config->SpreadSpectrum = SPREAD_SPECTRUM;
+ sb_config->PciClks = PCI_CLOCK_CTRL;
+ sb_config->HpetTimer = HPET_TIMER;
+
+ /* USB */
+ sb_config->USBMODE.UsbModeReg = USB_CINFIG;
+ sb_config->SbUsbPll = 0;
+
+ /* SATA */
+ sb_config->SataClass = SATA_MODE;
+ sb_config->SataIdeMode = SATA_IDE_MODE;
+ sb_config->SataPortMultCap = SATA_PORT_MULT_CAP_RESERVED;
+ sb_config->SATAMODE.SataMode.SataController = SATA_CONTROLLER;
+ sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary.
+ //TODO: set to secondary not take effect.
+ sb_config->SATAMODE.SataMode.SataIdeCombinedMode = 0; //IDE controlor exposed and combined mode enabled
+ sb_config->SATAMODE.SataMode.SATARefClkSel = SATA_CLOCK_SOURCE;
+
+ /* Azalia HDA */
+ sb_config->AzaliaController = AZALIA_CONTROLLER;
+ sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG;
+ sb_config->AZALIACONFIG.AzaliaSdinPin = AZALIA_SDIN_PIN;
+ sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr = NULL;
+
+ /*
+ * GPP. default configure only enable port0 with 4 lanes,
+ * configure in devicetree.cb would overwrite the default configuration
+ */
+ sb_config->GppFunctionEnable = GPP_CONTROLLER;
+ sb_config->GppLinkConfig = GPP_CFGMODE;
+ //sb_config->PORTCONFIG[0].PortCfg.PortHotPlug = TRUE;
+ sb_config->PORTCONFIG[0].PortCfg.PortPresent = ENABLED;
+ sb_config->PORTCONFIG[1].PortCfg.PortPresent = ENABLED;
+ sb_config->PORTCONFIG[2].PortCfg.PortPresent = ENABLED;
+ sb_config->PORTCONFIG[3].PortCfg.PortPresent = ENABLED;
+ sb_config->GppUnhidePorts = TRUE; //visable always, even port empty
+ //sb_config->NbSbGen2 = TRUE;
+ //sb_config->GppGen2 = TRUE;
+
+ //cimx BTS fix
+ sb_config->GppMemWrImprove = TRUE;
+ sb_config->SbPcieOrderRule = TRUE;
+ sb_config->AlinkPhyPllPowerDown = TRUE;
+ sb_config->GppPhyPllPowerDown = TRUE; //GPP power saving
+ sb_config->SBGecPwr = 0x03;//11b << 5, rpr BDF: 00:20:06, PLATFORM.H default define 0x11 was wrong
+ sb_config->GecConfig = 0; //ENABLE GEC controller
+
+#ifndef __PRE_RAM__
+ /* ramstage cimx config here */
+ if (!sb_config->StdHeader.CALLBACK.CalloutPtr) {
+ sb_config->StdHeader.CALLBACK.CalloutPtr = sb800_callout_entry;
+ }
+
+ //sb_config->
+#endif //!__PRE_RAM__
+}
+
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#ifndef _SB800_CFG_H_
+#define _SB800_CFG_H_
+
+#include <stdint.h>
+
+
+/**
+ * @def BIOS_SIZE_1M
+ * @def BIOS_SIZE_2M
+ * @def BIOS_SIZE_4M
+ * @def BIOS_SIZE_8M
+ */
+#define BIOS_SIZE_1M 0
+#define BIOS_SIZE_2M 1
+#define BIOS_SIZE_4M 3
+#define BIOS_SIZE_8M 7
+
+/* In SB800, default ROM size is 1M Bytes, if your platform ROM
+ * bigger than 1M you have to set the ROM size outside CIMx module and
+ * before AGESA module get call.
+ */
+#ifndef BIOS_SIZE
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+ #define BIOS_SIZE BIOS_SIZE_1M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
+ #define BIOS_SIZE BIOS_SIZE_2M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1
+ #define BIOS_SIZE BIOS_SIZE_4M
+#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1
+ #define BIOS_SIZE BIOS_SIZE_8M
+#endif
+#endif
+
+/**
+ * @def SPREAD_SPECTRUM
+ * @brief
+ * 0 - Disable Spread Spectrum function
+ * 1 - Enable Spread Spectrum function
+ */
+#define SPREAD_SPECTRUM 0
+
+/**
+ * @def SB_HPET_TIMER
+ * @breif
+ * 0 - Disable hpet
+ * 1 - Enable hpet
+ */
+#define HPET_TIMER 1
+
+/**
+ * @def USB_CONFIG
+ * @brief bit[0-6] used to control USB
+ * 0 - Disable
+ * 1 - Enable
+ * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0
+ * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1
+ * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2
+ * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3
+ * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4
+ * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5
+ * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6
+ */
+#define USB_CINFIG 0x7F
+
+/**
+ * @def PCI_CLOCK_CTRL
+ * @breif bit[0-4] used for PCI Slots Clock Control,
+ * 0 - disable
+ * 1 - enable
+ * PCI SLOT 0 define at BIT0
+ * PCI SLOT 1 define at BIT1
+ * PCI SLOT 2 define at BIT2
+ * PCI SLOT 3 define at BIT3
+ * PCI SLOT 4 define at BIT4
+ */
+#define PCI_CLOCK_CTRL 0x1F
+
+/**
+ * @def SATA_CONTROLLER
+ * @breif INCHIP Sata Controller
+ */
+#ifndef SATA_CONTROLLER
+ #define SATA_CONTROLLER ENABLED
+#endif
+
+/**
+ * @def SATA_MODE
+ * @breif INCHIP Sata Controller Mode
+ * NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#ifndef SATA_MODE
+ #define SATA_MODE NATIVE_IDE_MODE
+#endif
+
+/**
+ * @breif INCHIP Sata IDE Controller Mode
+ */
+#define IDE_LEGACY_MODE 0
+#define IDE_NATIVE_MODE 1
+
+/**
+ * @def SATA_IDE_MODE
+ * @breif INCHIP Sata IDE Controller Mode
+ * NOTE: DO NOT ALLOW SATA & IDE use same mode
+ */
+#ifndef SATA_IDE_MODE
+ #define SATA_IDE_MODE IDE_LEGACY_MODE
+#endif
+
+/**
+ * @def EXTERNAL_CLOCK
+ * @brief 00/10: Reference clock from crystal oscillator via
+ * PAD_XTALI and PAD_XTALO
+ *
+ * @def INTERNAL_CLOCK
+ * @brief 01/11: Reference clock from internal clock through
+ * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL
+ */
+#define EXTERNAL_CLOCK 0x00
+#define INTERNAL_CLOCK 0x01
+
+/* NOTE: inagua have to using internal clock,
+ * otherwise can not detect sata drive
+ */
+#define SATA_CLOCK_SOURCE INTERNAL_CLOCK
+
+/**
+ * @def SATA_PORT_MULT_CAP_RESERVED
+ * @brief 1 ON, 0 0FF
+ */
+#define SATA_PORT_MULT_CAP_RESERVED 1
+
+
+/**
+ * @def AZALIA_AUTO
+ * @brief Detect Azalia controller automatically.
+ *
+ * @def AZALIA_DISABLE
+ * @brief Disable Azalia controller.
+
+ * @def AZALIA_ENABLE
+ * @brief Enable Azalia controller.
+ */
+#define AZALIA_AUTO 0
+#define AZALIA_DISABLE 1
+#define AZALIA_ENABLE 2
+
+/**
+ * @breif INCHIP HDA controller
+ */
+#ifndef AZALIA_CONTROLLER
+ #define AZALIA_CONTROLLER AZALIA_AUTO
+#endif
+
+/**
+ * @def AZALIA_PIN_CONFIG
+ * @brief
+ * 0 - disable
+ * 1 - enable
+ */
+#ifndef AZALIA_PIN_CONFIG
+ #define AZALIA_PIN_CONFIG 1
+#endif
+
+/**
+ * @def AZALIA_SDIN_PIN
+ * @brief
+ * SDIN0 is define at BIT0 & BIT1
+ * 00 - GPIO PIN
+ * 01 - Reserved
+ * 10 - As a Azalia SDIN pin
+ * SDIN1 is define at BIT2 & BIT3
+ * SDIN2 is define at BIT4 & BIT5
+ * SDIN3 is define at BIT6 & BIT7
+ */
+#ifndef AZALIA_SDIN_PIN
+ //#define AZALIA_SDIN_PIN 0xAA
+ #define AZALIA_SDIN_PIN 0x2A
+#endif
+
+/**
+ * @def GPP_CONTROLLER
+ */
+#ifndef GPP_CONTROLLER
+ #define GPP_CONTROLLER ENABLED
+#endif
+
+/**
+ * @def GPP_CFGMODE
+ * @brief GPP Link Configuration
+ * four possible configuration:
+ * GPP_CFGMODE_X4000
+ * GPP_CFGMODE_X2200
+ * GPP_CFGMODE_X2110
+ * GPP_CFGMODE_X1111
+ */
+#ifndef GPP_CFGMODE
+ #define GPP_CFGMODE GPP_CFGMODE_X1111
+#endif
+
+
+/**
+ * @brief South Bridge CIMx configuration
+ *
+ */
+void sb800_cimx_config(AMDSBCFG *sb_cfg);
+
+/**
+ * @brief Entry point of Southbridge CIMx callout
+ *
+ * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)
+ *
+ * @param[in] func Southbridge CIMx Function ID.
+ * @param[in] data Southbridge Input Data.
+ * @param[in] sb_cfg Southbridge configuration structure pointer.
+ *
+ */
+u32 sb800_callout_entry(u32 func, u32 data, void* sb_cfg);
+
+#endif
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+//#include <config.h>
+#include <stdint.h>
+#include <device/pci_ids.h>
+#include <arch/io.h> /* inl, outl */
+#include <arch/romcc_io.h> /* device_t */
+#include "SBPLATFORM.h"
+#include "SbEarly.h"
+#include "sb800_cfg.h" /*sb800_cimx_config*/
+
+
+/**
+ * @brief Get SouthBridge device number
+ * @param[in] bus target bus number
+ * @return southbridge device number
+ */
+u32 get_sbdn(u32 bus)
+{
+ device_t dev;
+
+ //dev = PCI_DEV(bus, 0x14, 0);
+ dev = pci_locate_device_on_bus(
+ PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB800_SM),
+ bus);
+
+ return (dev >> 15) & 0x1f;
+}
+
+
+/**
+ * @brief South Bridge CIMx romstage entry,
+ * wrapper of sbPowerOnInit entry point.
+ */
+void sb_poweron_init(void)
+{
+ AMDSBCFG sb_early_cfg;
+
+ sb800_cimx_config(&sb_early_cfg);
+ //sb_early_cfg.StdHeader.Func = SB_POWERON_INIT;
+ //AmdSbDispatcher(&sb_early_cfg);
+ //TODO
+ //AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
+ // VerifyImage() will fail, LocateImage() take minitues to find the image.
+ sbPowerOnInit(&sb_early_cfg);
+}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#include <device/device.h> /* device_t */
+#include <device/pci.h> /* device_operations */
+#include <device/pci_ids.h>
+#include <device/smbus.h> /* smbus_bus_operations */
+#include <console/console.h> /* printk */
+#include "sb800_lpc.h" /* lpc_read_resources */
+#include "SBPLATFORM.h" /* Platfrom Specific Definitions */
+#include "sb800_cfg.h" /* sb800 Cimx configuration */
+#include "chip.h" /* struct southbridge_amd_cimx_wrapper_sb800_config */
+
+
+/*implement in mainboard.c*/
+//void set_pcie_assert(void);
+//void set_pcie_deassert(void);
+void set_pcie_reset(void);
+void set_pcie_dereset(void);
+
+
+#ifndef _RAMSTAGE_
+#define _RAMSTAGE_
+#endif
+static AMDSBCFG sb_late_cfg; //global, init in sb800_cimx_config
+static AMDSBCFG *sb_config = &sb_late_cfg;
+
+
+/**
+ * @brief Entry point of Southbridge CIMx callout
+ *
+ * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)
+ *
+ * @param[in] func Southbridge CIMx Function ID.
+ * @param[in] data Southbridge Input Data.
+ * @param[in] sb_config Southbridge configuration structure pointer.
+ *
+ */
+u32 sb800_callout_entry(u32 func, u32 data, void* config)
+{
+ u32 ret = 0;
+
+ switch (func) {
+ case CB_SBGPP_RESET_ASSERT:
+ //set_pcie_assert();
+ set_pcie_reset();
+ break;
+
+ case CB_SBGPP_RESET_DEASSERT:
+ //set_pcie_deassert();
+ set_pcie_dereset();
+ break;
+
+ case IMC_FIRMWARE_FAIL:
+ break;
+
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+
+static struct pci_operations lops_pci = {
+ .set_subsystem = 0,
+};
+
+static void lpc_enable_resources(device_t dev)
+{
+
+ pci_dev_enable_resources(dev);
+ //lpc_enable_childrens_resources(dev);
+}
+
+static void lpc_init(device_t dev)
+{
+ /* SB Configure HPET base and enable bit */
+ hpetInit(sb_config, &(sb_config->BuildParameters));
+}
+
+static struct device_operations lpc_ops = {
+ .read_resources = lpc_read_resources,
+ .set_resources = lpc_set_resources,
+ .enable_resources = lpc_enable_resources,
+ .init = lpc_init,
+ .scan_bus = scan_static_bus,
+ .ops_pci = &lops_pci,
+};
+
+static const struct pci_driver lpc_driver __pci_driver = {
+ .ops = &lpc_ops,
+ .vendor = PCI_VENDOR_ID_ATI,
+ .device = PCI_DEVICE_ID_ATI_SB800_LPC,
+};
+
+
+static void sata_enable_resources(struct device *dev)
+{
+ sataInitAfterPciEnum(sb_config);
+ pci_dev_enable_resources(dev);
+}
+
+static void sata_init(struct device *dev)
+{
+ sb_config->StdHeader.Func = SB_MID_POST_INIT;
+ AmdSbDispatcher(sb_config); //sataInitMidPost only
+ commonInitLateBoot(sb_config);
+ sataInitLatePost(sb_config);
+}
+
+static struct device_operations sata_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = sata_enable_resources, //pci_dev_enable_resources,
+ .init = sata_init,
+ .scan_bus = 0,
+ .ops_pci = &lops_pci,
+};
+
+static const struct pci_driver sata_driver __pci_driver = {
+ .ops = &sata_ops,
+ .vendor = PCI_VENDOR_ID_ATI,
+ .device = PCI_DEVICE_ID_ATI_SB800_SATA, //SATA IDE Mode 4390
+};
+
+
+#if CONFIG_USBDEBUG
+static void usb_set_resources(struct device *dev)
+{
+ struct resource *res;
+ u32 base;
+ u32 old_debug;
+
+ old_debug = get_ehci_debug();
+ set_ehci_debug(0);
+
+ pci_dev_set_resources(dev);
+
+ res = find_resource(dev, 0x10);
+ set_ehci_debug(old_debug);
+ if (!res)
+ return;
+ base = res->base;
+ set_ehci_base(base);
+ report_resource_stored(dev, res, "");
+}
+#endif
+
+static void usb_init(struct device *dev)
+{
+ usbInitAfterPciInit(sb_config);
+ commonInitLateBoot(sb_config);
+}
+
+static struct device_operations usb_ops = {
+ .read_resources = pci_dev_read_resources,
+#if CONFIG_USBDEBUG
+ .set_resources = usb_set_resources,
+#else
+ .set_resources = pci_dev_set_resources,
+#endif
+ .enable_resources = pci_dev_enable_resources,
+ .init = usb_init,
+ .scan_bus = 0,
+ .ops_pci = &lops_pci,
+};
+
+/*
+ * The pci id of usb ctrl 0 and 1 are the same.
+ */
+static const struct pci_driver usb_ohci123_driver __pci_driver = {
+ .ops = &usb_ops,
+ .vendor = PCI_VENDOR_ID_ATI,
+ .device = PCI_DEVICE_ID_ATI_SB800_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */
+};
+
+static const struct pci_driver usb_ehci123_driver __pci_driver = {
+ .ops = &usb_ops,
+ .vendor = PCI_VENDOR_ID_ATI,
+ .device = PCI_DEVICE_ID_ATI_SB800_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */
+};
+
+static const struct pci_driver usb_ohci4_driver __pci_driver = {
+ .ops = &usb_ops,
+ .vendor = PCI_VENDOR_ID_ATI,
+ .device = PCI_DEVICE_ID_ATI_SB800_USB_20_5, /* OHCI-USB4 */
+};
+
+
+static void azalia_init(struct device *dev)
+{
+ azaliaInitAfterPciEnum(sb_config); //Detect and configure High Definition Audio
+}
+
+static struct device_operations azalia_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = azalia_init,
+ .scan_bus = 0,
+ .ops_pci = &lops_pci,
+};
+
+static const struct pci_driver azalia_driver __pci_driver = {
+ .ops = &azalia_ops,
+ .vendor = PCI_VENDOR_ID_ATI,
+ .device = PCI_DEVICE_ID_ATI_SB800_HDA,
+};
+
+
+static void gec_init(struct device *dev)
+{
+ gecInitAfterPciEnum(sb_config);
+ gecInitLatePost(sb_config);
+ printk(BIOS_DEBUG, "gec hda enabled\n");
+}
+
+static struct device_operations gec_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = gec_init,
+ .scan_bus = 0,
+ .ops_pci = &lops_pci,
+};
+
+static const struct pci_driver gec_driver __pci_driver = {
+ .ops = &gec_ops,
+ .vendor = PCI_VENDOR_ID_ATI,
+ .device = PCI_DEVICE_ID_ATI_SB800_GEC,
+};
+
+
+static void pcie_init(device_t dev)
+{
+ sbPcieGppLateInit(sb_config);
+}
+
+static struct device_operations pci_ops = {
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_bus_enable_resources,
+ .init = pcie_init,
+ .scan_bus = pci_scan_bridge,
+ .reset_bus = pci_bus_reset,
+ .ops_pci = &lops_pci,
+};
+
+static const struct pci_driver pci_driver __pci_driver = {
+ .ops = &pci_ops,
+ .vendor = PCI_VENDOR_ID_ATI,
+ .device = PCI_DEVICE_ID_ATI_SB800_PCI,
+};
+
+
+struct device_operations bridge_ops = {
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_bus_enable_resources,
+ .init = pcie_init,
+ .scan_bus = pci_scan_bridge,
+ .enable = 0,
+ .reset_bus = pci_bus_reset,
+ .ops_pci = &lops_pci,
+};
+
+/* 0:15:0 PCIe PortA */
+static const struct pci_driver PORTA_driver __pci_driver = {
+ .ops = &bridge_ops,
+ .vendor = PCI_VENDOR_ID_ATI,
+ .device = PCI_DEVICE_ID_ATI_SB800_PCIEA,
+};
+
+/* 0:15:1 PCIe PortB */
+static const struct pci_driver PORTB_driver __pci_driver = {
+ .ops = &bridge_ops,
+ .vendor = PCI_VENDOR_ID_ATI,
+ .device = PCI_DEVICE_ID_ATI_SB800_PCIEB,
+};
+
+/* 0:15:2 PCIe PortC */
+static const struct pci_driver PORTC_driver __pci_driver = {
+ .ops = &bridge_ops,
+ .vendor = PCI_VENDOR_ID_ATI,
+ .device = PCI_DEVICE_ID_ATI_SB800_PCIEC,
+};
+
+/* 0:15:3 PCIe PortD */
+static const struct pci_driver PORTD_driver __pci_driver = {
+ .ops = &bridge_ops,
+ .vendor = PCI_VENDOR_ID_ATI,
+ .device = PCI_DEVICE_ID_ATI_SB800_PCIED,
+};
+
+
+/**
+ * @brief SB Cimx entry point sbBeforePciInit wrapper
+ */
+static void sb800_enable(device_t dev)
+{
+ u8 gpp_port = 0;
+ struct southbridge_amd_cimx_wrapper_sb800_config *sb_chip =
+ (struct southbridge_amd_cimx_wrapper_sb800_config *)(dev->chip_info);
+
+ sb800_cimx_config(sb_config);
+ printk(BIOS_DEBUG, "sb800_enable() ");
+
+ /* Config SouthBridge SMBUS/ACPI/IDE/LPC/PCIB.*/
+ commonInitEarlyBoot(sb_config);
+ commonInitEarlyPost(sb_config);
+
+ switch (dev->path.pci.devfn) {
+ case (0x11 << 3) | 0: /* 0:11.0 SATA */
+ if (dev->enabled) {
+ sb_config->SATAMODE.SataMode.SataController = ENABLED;
+ if (1 == sb_chip->boot_switch_sata_ide)
+ sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary.
+ else if (0 == sb_chip->boot_switch_sata_ide)
+ sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary.
+ } else {
+ sb_config->SATAMODE.SataMode.SataController = DISABLED;
+ }
+
+ sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
+ break;
+
+ case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */
+ case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */
+ case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */
+ case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */
+ case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */
+ case (0x16 << 3) | 0: /* 0:16:0 OHCI-USB3 */
+ case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */
+ usbInitBeforePciEnum(sb_config); // USB POST TIME Only
+ break;
+
+ case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
+ break;
+
+ case (0x14 << 3) | 1: /* 0:14:1 IDE */
+ if (dev->enabled) {
+ sb_config->SATAMODE.SataMode.SataIdeCombinedMode = ENABLED;
+ } else {
+ sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED;
+ }
+ sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
+ break;
+
+ case (0x14 << 3) | 2: /* 0:14:2 HDA */
+ if (dev->enabled) {
+ if (AZALIA_DISABLE == sb_config->AzaliaController) {
+ sb_config->AzaliaController = AZALIA_AUTO;
+ }
+ printk(BIOS_DEBUG, "hda enabled\n");
+ } else {
+ sb_config->AzaliaController = AZALIA_DISABLE;
+ printk(BIOS_DEBUG, "hda disabled\n");
+ }
+ azaliaInitBeforePciEnum(sb_config); // Detect and configure High Definition Audio
+ break;
+
+
+ case (0x14 << 3) | 3: /* 0:14:3 LPC */
+ break;
+
+ case (0x14 << 3) | 4: /* 0:14:4 PCI */
+ break;
+
+ case (0x14 << 3) | 6: /* 0:14:6 GEC */
+ if (dev->enabled) {
+ sb_config->GecConfig = 0;
+ printk(BIOS_DEBUG, "gec enabled\n");
+ } else {
+ sb_config->GecConfig = 1;
+ printk(BIOS_DEBUG, "gec disabled\n");
+ }
+ gecInitBeforePciEnum(sb_config); // Init GEC
+ break;
+
+ case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */
+ case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */
+ case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */
+ case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */
+ gpp_port = (dev->path.pci.devfn) & 0x03;
+ if (dev->enabled) {
+ sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = ENABLED;
+ } else {
+ sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = DISABLED;
+ }
+
+ /*
+ * GPP_CFGMODE_X4000: PortA Lanes[3:0]
+ * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2]
+ * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3
+ * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
+ */
+ if (sb_config->GppLinkConfig != sb_chip->gpp_configuration) {
+ sb_config->GppLinkConfig = sb_chip->gpp_configuration;
+ }
+
+ sbPcieGppEarlyInit(sb_config);
+ break;
+
+ default:
+ break;
+ }
+
+ /* Special setting ABCFG registers before PCI emulation. */
+ abSpecialSetBeforePciEnum(sb_config);
+ usbDesertPll(sb_config);
+ //sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT;
+ //AmdSbDispatcher(sb_config);
+}
+
+struct chip_operations southbridge_amd_cimx_wrapper_sb800_ops = {
+ CHIP_NAME("ATI SB800")
+ .enable_dev = sb800_enable,
+};
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/pci.h>
+#include "sb800_lpc.h"
+
+
+void lpc_read_resources(device_t dev)
+{
+ struct resource *res;
+
+ /* Get the normal pci resources of this device */
+ pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */
+
+ pci_get_resource(dev, SPIROM_BASE_ADDRESS); /* SPI ROM base address */
+
+ /* Add an extra subtractive resource for both memory and I/O. */
+ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+ res->base = 0;
+ res->size = 0x1000;
+ res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+ IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+ res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+ res->base = 0xff800000;
+ res->size = 0x00800000; /* 8 MB for flash */
+ res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+ IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+ res = new_resource(dev, 3); /* IOAPIC */
+ res->base = 0xfec00000;
+ res->size = 0x00001000;
+ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+ compact_resources(dev);
+}
+
+void lpc_set_resources(struct device *dev)
+{
+ struct resource *res;
+
+ pci_dev_set_resources(dev);
+
+ /* Specical case. SPI Base Address. The SpiRomEnable should be set. */
+ res = find_resource(dev, SPIROM_BASE_ADDRESS);
+ pci_write_config32(dev, SPIROM_BASE_ADDRESS, res->base | 1 << 1);
+
+}
+
+/**
+ * @brief Enable resources for children devices
+ *
+ * @param dev the device whos children's resources are to be enabled
+ *
+ */
+void lpc_enable_childrens_resources(device_t dev)
+{
+ struct bus *link;
+ u32 reg, reg_x;
+ int var_num = 0;
+ u16 reg_var[3];
+
+ reg = pci_read_config32(dev, 0x44);
+ reg_x = pci_read_config32(dev, 0x48);
+
+ for (link = dev->link_list; link; link = link->next) {
+ device_t child;
+ for (child = link->children; child;
+ child = child->sibling) {
+ if (child->enabled
+ && (child->path.type == DEVICE_PATH_PNP)) {
+ struct resource *res;
+ for (res = child->resource_list; res; res = res->next) {
+ u32 base, end; /* don't need long long */
+ if (!(res->flags & IORESOURCE_IO))
+ continue;
+ base = res->base;
+ end = resource_end(res);
+/*
+ printk(BIOS_DEBUG, "sb800 lpc decode:%s, base=0x%08x, end=0x%08x\n",
+ dev_path(child), base, end);
+*/
+ switch (base) {
+ case 0x60: /* KB */
+ case 0x64: /* MS */
+ reg |= (1 << 29);
+ break;
+ case 0x3f8: /* COM1 */
+ reg |= (1 << 6);
+ break;
+ case 0x2f8: /* COM2 */
+ reg |= (1 << 7);
+ break;
+ case 0x378: /* Parallal 1 */
+ reg |= (1 << 0);
+ break;
+ case 0x3f0: /* FD0 */
+ reg |= (1 << 26);
+ break;
+ case 0x220: /* Aduio 0 */
+ reg |= (1 << 8);
+ break;
+ case 0x300: /* Midi 0 */
+ reg |= (1 << 18);
+ break;
+ case 0x400:
+ reg_x |= (1 << 16);
+ break;
+ case 0x480:
+ reg_x |= (1 << 17);
+ break;
+ case 0x500:
+ reg_x |= (1 << 18);
+ break;
+ case 0x580:
+ reg_x |= (1 << 19);
+ break;
+ case 0x4700:
+ reg_x |= (1 << 22);
+ break;
+ case 0xfd60:
+ reg_x |= (1 << 23);
+ break;
+ default:
+ if (var_num >= 3)
+ continue; /* only 3 var ; compact them ? */
+ switch (var_num) {
+ case 0:
+ reg_x |= (1 << 2);
+ break;
+ case 1:
+ reg_x |= (1 << 24);
+ break;
+ case 2:
+ reg_x |= (1 << 25);
+ break;
+ }
+ reg_var[var_num++] =
+ base & 0xffff;
+ }
+ }
+ }
+ }
+ }
+ pci_write_config32(dev, 0x44, reg);
+ pci_write_config32(dev, 0x48, reg_x);
+ /* Set WideIO for as many IOs found (fall through is on purpose) */
+ switch (var_num) {
+ case 2:
+ pci_write_config16(dev, 0x90, reg_var[2]);
+ case 1:
+ pci_write_config16(dev, 0x66, reg_var[1]);
+ case 0:
+ //pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata
+ break;
+ }
+}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _SB800_LPC_H_
+#define _SB800_LPC_H_
+
+
+#define SPIROM_BASE_ADDRESS 0xA0 /* SPI ROM base address */
+
+void lpc_read_resources(device_t dev);
+void lpc_set_resources(device_t dev);
+void lpc_enable_childrens_resources(device_t dev);
+
+#endif
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#include <arch/io.h>
+#include "sb800_smbus.h"
+
+static inline void smbus_delay(void)
+{
+ outb(inb(0x80), 0x80);
+}
+
+static int smbus_wait_until_ready(u32 smbus_io_base)
+{
+ u32 loops;
+
+ loops = SMBUS_TIMEOUT;
+ do {
+ u8 val;
+ val = inb(smbus_io_base + SMBHSTSTAT);
+ val &= 0x1f;
+ if (val == 0) { /* ready now */
+ return 0;
+ }
+ outb(val, smbus_io_base + SMBHSTSTAT);
+ } while (--loops);
+
+ return -2; /* time out */
+}
+
+static int smbus_wait_until_done(u32 smbus_io_base)
+{
+ u32 loops;
+
+ loops = SMBUS_TIMEOUT;
+ do {
+ u8 val;
+
+ val = inb(smbus_io_base + SMBHSTSTAT);
+ val &= 0x1f; /* mask off reserved bits */
+ if (val & 0x1c) {
+ return -5; /* error */
+ }
+ if (val == 0x02) {
+ outb(val, smbus_io_base + SMBHSTSTAT); /* clear status */
+ return 0;
+ }
+ } while (--loops);
+
+ return -3; /* timeout */
+}
+
+int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
+{
+ u8 byte;
+
+ if (smbus_wait_until_ready(smbus_io_base) < 0) {
+ return -2; /* not ready */
+ }
+
+ /* set the device I'm talking too */
+ outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
+
+ byte = inb(smbus_io_base + SMBHSTCTRL);
+ byte &= 0xe3; /* Clear [4:2] */
+ byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */
+ outb(byte, smbus_io_base + SMBHSTCTRL);
+
+ /* poll for transaction completion */
+ if (smbus_wait_until_done(smbus_io_base) < 0) {
+ return -3; /* timeout or error */
+ }
+
+ /* read results of transaction */
+ byte = inb(smbus_io_base + SMBHSTCMD);
+
+ return byte;
+}
+
+int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val)
+{
+ u8 byte;
+
+ if (smbus_wait_until_ready(smbus_io_base) < 0) {
+ return -2; /* not ready */
+ }
+
+ /* set the command... */
+ outb(val, smbus_io_base + SMBHSTCMD);
+
+ /* set the device I'm talking too */
+ outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
+
+ byte = inb(smbus_io_base + SMBHSTCTRL);
+ byte &= 0xe3; /* Clear [4:2] */
+ byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */
+ outb(byte, smbus_io_base + SMBHSTCTRL);
+
+ /* poll for transaction completion */
+ if (smbus_wait_until_done(smbus_io_base) < 0) {
+ return -3; /* timeout or error */
+ }
+
+ return 0;
+}
+
+int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address)
+{
+ u8 byte;
+
+ if (smbus_wait_until_ready(smbus_io_base) < 0) {
+ return -2; /* not ready */
+ }
+
+ /* set the command/address... */
+ outb(address & 0xff, smbus_io_base + SMBHSTCMD);
+
+ /* set the device I'm talking too */
+ outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
+
+ byte = inb(smbus_io_base + SMBHSTCTRL);
+ byte &= 0xe3; /* Clear [4:2] */
+ byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */
+ outb(byte, smbus_io_base + SMBHSTCTRL);
+
+ /* poll for transaction completion */
+ if (smbus_wait_until_done(smbus_io_base) < 0) {
+ return -3; /* timeout or error */
+ }
+
+ /* read results of transaction */
+ byte = inb(smbus_io_base + SMBHSTDAT0);
+
+ return byte;
+}
+
+int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val)
+{
+ u8 byte;
+
+ if (smbus_wait_until_ready(smbus_io_base) < 0) {
+ return -2; /* not ready */
+ }
+
+ /* set the command/address... */
+ outb(address & 0xff, smbus_io_base + SMBHSTCMD);
+
+ /* set the device I'm talking too */
+ outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
+
+ /* output value */
+ outb(val, smbus_io_base + SMBHSTDAT0);
+
+ byte = inb(smbus_io_base + SMBHSTCTRL);
+ byte &= 0xe3; /* Clear [4:2] */
+ byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */
+ outb(byte, smbus_io_base + SMBHSTCTRL);
+
+ /* poll for transaction completion */
+ if (smbus_wait_until_done(smbus_io_base) < 0) {
+ return -3; /* timeout or error */
+ }
+
+ return 0;
+}
+
+void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
+{
+ u32 tmp;
+
+ outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX);
+ tmp = inl(AB_DATA);
+ /* rpr 4.2
+ * For certain revisions of the chip, the ABCFG registers,
+ * with an address of 0x100NN (where 'N' is any hexadecimal
+ * number), require an extra programming step.*/
+ outl(0, AB_INDX);
+
+ tmp &= ~mask;
+ tmp |= val;
+
+ /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */
+ outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we dont have to do it again. */
+ outl(tmp, AB_DATA);
+ outl(0, AB_INDX);
+}
+
+void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val)
+{
+ u32 tmp;
+
+ outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX);
+ tmp = inl(AB_DATA);
+ /* rpr 4.2
+ * For certain revisions of the chip, the ABCFG registers,
+ * with an address of 0x100NN (where 'N' is any hexadecimal
+ * number), require an extra programming step.*/
+ outl(0, AB_INDX);
+
+ tmp &= ~mask;
+ tmp |= val;
+
+ //printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr);
+ outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we dont have to do it again. */
+ outl(tmp, AB_DATA);
+ outl(0, AB_INDX);
+}
+
+/* space = 0: AX_INDXC, AX_DATAC
+ * space = 1: AX_INDXP, AX_DATAP
+ */
+void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val)
+{
+ u32 tmp;
+
+ /* read axindc to tmp */
+ outl(space << 29 | space << 3 | 0x30, AB_INDX);
+ outl(axindc, AB_DATA);
+ outl(0, AB_INDX);
+ outl(space << 29 | space << 3 | 0x34, AB_INDX);
+ tmp = inl(AB_DATA);
+ outl(0, AB_INDX);
+
+ tmp &= ~mask;
+ tmp |= val;
+
+ /* write tmp */
+ outl(space << 29 | space << 3 | 0x30, AB_INDX);
+ outl(axindc, AB_DATA);
+ outl(0, AB_INDX);
+ outl(space << 29 | space << 3 | 0x34, AB_INDX);
+ outl(tmp, AB_DATA);
+ outl(0, AB_INDX);
+}
+
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _SB800_SMBUS_H_
+#define _SB800_SMBUS_H_
+
+//#include <stdint.h>
+
+#define SMBUS_IO_BASE SMBUS0_BASE_ADDRESS
+
+#define SMBHSTSTAT 0x0
+#define SMBSLVSTAT 0x1
+#define SMBHSTCTRL 0x2
+#define SMBHSTCMD 0x3
+#define SMBHSTADDR 0x4
+#define SMBHSTDAT0 0x5
+#define SMBHSTDAT1 0x6
+#define SMBHSTBLKDAT 0x7
+
+#define SMBSLVCTRL 0x8
+#define SMBSLVCMD_SHADOW 0x9
+#define SMBSLVEVT 0xa
+#define SMBSLVDAT 0xc
+
+/*//SB00.H
+#define AX_INDXC 0
+#define AX_INDXP 2
+#define AXCFG 4
+#define ABCFG 6
+#define RC_INDXC 1
+#define RC_INDXP 3
+*/
+
+#define AB_INDX 0xCD8
+#define AB_DATA (AB_INDX+4)
+
+/* Between 1-10 seconds, We should never timeout normally
+ * Longer than this is just painful when a timeout condition occurs.
+ */
+#define SMBUS_TIMEOUT (100*1000*10)
+
+#define abcfg_reg(reg, mask, val) \
+ alink_ab_indx((ABCFG), (reg), (mask), (val))
+#define axcfg_reg(reg, mask, val) \
+ alink_ab_indx((AXCFG), (reg), (mask), (val))
+#define axindxc_reg(reg, mask, val) \
+ alink_ax_indx((AX_INDXC), (reg), (mask), (val))
+#define axindxp_reg(reg, mask, val) \
+ alink_ax_indx((AX_INDXP), (reg), (mask), (val))
+#define rcindxc_reg(reg, port, mask, val) \
+ alink_rc_indx((RC_INDXC), (reg), (port), (mask), (val))
+#define rcindxp_reg(reg, port, mask, val) \
+ alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val))
+
+int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
+int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
+int do_smbus_recv_byte(u32 smbus_io_base, u32 device);
+int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val);
+void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val);
+void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val);
+void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val);
+
+#endif
projects / coreboot.git / commitdiff