BUILD-y := src/lib src/boot src/console src/devices src/southbridge src/northbridge src/superio src/drivers
BUILD-y += util/cbfstool util/sconfig
BUILD-$(CONFIG_ARCH_X86) += src/pc80
+BUILD-y += src/vendorcode
ifneq ($(CONFIG_LOCALVERSION),"")
COREBOOT_EXTRA_VERSION := -$(call strip_quotes,$(CONFIG_LOCALVERSION))
#include <cpu/x86/mtrr/earlymtrr.c>
#include <northbridge/amd/amdfam10/raminit_amdmct.c>
+#include <reset.h>
static void prep_fid_change(void);
static void init_fidvid_stage2(u32 apicid, u32 nodeid);
--- /dev/null
+subdirs-y += amd
--- /dev/null
+
+romstage-y += amdlib32.c
+ramstage-y += amdlib32.c
--- /dev/null
+#include "amdlib32.h"
+
+UINT8 ReadIo8 (IN UINT16 port)
+{
+ UINT8 value;
+ __asm__ __volatile__ ("inb %w1, %b0" : "=a"(value) : "Nd" (port));
+ return value;
+}
+
+UINT16 ReadIo16 (IN UINT16 port)
+{
+ UINT16 value;
+ __asm__ __volatile__ ("inw %w1, %w0" : "=a"(value) : "Nd" (port));
+ return value;
+}
+
+UINT32 ReadIo32 (IN UINT16 port)
+{
+ UINT32 value;
+ __asm__ __volatile__ ("inl %w1, %0" : "=a"(value) : "Nd" (port));
+ return value;
+}
+
+VOID WriteIo8 (IN UINT16 port, IN UINT8 value)
+{
+ __asm__ __volatile__ ("outb %b0, %w1" : : "a" (value), "Nd" (port));
+}
+
+VOID WriteIo16 (IN UINT16 port, IN UINT16 value)
+{
+ __asm__ __volatile__ ("outw %w0, %w1" : : "a" (value), "Nd" (port));
+}
+
+VOID WriteIo32 (IN UINT16 port, IN UINT32 value)
+{
+ __asm__ __volatile__ ("outl %0, %w1" : : "a" (value), "Nd" (port));
+}
+
+UINT64 ReadTSC(VOID)
+{
+ struct tsc_struct {
+ unsigned lo;
+ unsigned hi;
+ } res;
+ UINT64 ret;
+
+ __asm__ __volatile__ (
+ "rdtsc"
+ : "=a" (res.lo), "=d"(res.hi) /* outputs */
+ );
+ ret = res.hi;
+ ret <<= 32;
+ ret |= res.lo;
+ return ret;
+}
+
+VOID CpuidRead(IN UINT32 op, IN OUT SB_CPUID_DATA* Data)
+{
+ asm volatile(
+ "cpuid"
+ : "=a" (Data->EAX_Reg),
+ "=b" (Data->EBX_Reg),
+ "=c" (Data->ECX_Reg),
+ "=d" (Data->EDX_Reg)
+ : "0" (op));
+}
+
+static inline unsigned int cpuid_ecx(unsigned int op)
+{
+ unsigned int eax, ecx;
+
+ __asm__("cpuid"
+ : "=a" (eax), "=c" (ecx)
+ : "0" (op)
+ : "ebx", "edx" );
+ return ecx;
+}
+
+//static inline unsigned get_core_num(void)
+UINT8 ReadNumberOfCpuCores(VOID)
+{
+ return (cpuid_ecx(0x80000008) & 0xff);
+}
+
--- /dev/null
+#ifndef _AMDLIB32_H_
+#define _AMDLIB32_H_
+
+#include "cbtypes.h"
+#include "Amd.h"
+
+UINT8 ReadIo8 (IN UINT16 port);
+UINT16 ReadIo16 (IN UINT16 port);
+UINT32 ReadIo32 (IN UINT16 port);
+VOID WriteIo8 (IN UINT16 port, IN UINT8 value);
+VOID WriteIo16 (IN UINT16 port, IN UINT16 value);
+VOID WriteIo32 (IN UINT16 port, IN UINT32 value);
+UINT64 ReadTSC(VOID);
+VOID CpuidRead(IN UINT32 op, IN OUT SB_CPUID_DATA* Data);
+UINT8 ReadNumberOfCpuCores(VOID);
+#endif //_AMDLIB32_H_
--- /dev/null
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+\r
+#include "SBPLATFORM.h"\r
+\r
+//\r
+//\r
+// Routine Description:\r
+//\r
+// Locate ACPI table\r
+//\r
+// Arguments:\r
+//\r
+// Signature - table signature\r
+//\r
+//Returns:\r
+//\r
+// pointer to ACPI table\r
+//\r
+//\r
+VOID*\r
+ACPI_LocateTable (\r
+ IN UINT32 Signature\r
+ )\r
+{\r
+ UINT32 i;\r
+ UINT32* RsdPtr;\r
+ UINT32* Rsdt;\r
+ UINTN tableOffset;\r
+ DESCRIPTION_HEADER* CurrentTable;\r
+\r
+ RsdPtr = (UINT32*) (UINTN)0xe0000;\r
+ Rsdt = NULL;\r
+ do {\r
+ //if ( *RsdPtr == ' DSR' && *(RsdPtr + 1) == ' RTP' ) { //gcc multi-character character constant warning\r
+ if ( *RsdPtr == 0x20445352 && *(RsdPtr + 1) == 0x20525450) {\r
+\r
+ Rsdt = (UINT32*) (UINTN) ((RSDP*)RsdPtr)->RsdtAddress;\r
+ break;\r
+ }\r
+ RsdPtr += 4;\r
+ } while ( RsdPtr <= (UINT32*) (UINTN)0xffff0 );\r
+ if ( Rsdt != NULL && ACPI_GetTableChecksum (Rsdt) == 0 ) {\r
+ for ( i = 0; i < (((DESCRIPTION_HEADER*)Rsdt)->Length - sizeof (DESCRIPTION_HEADER)) / 4; i++ ) {\r
+ tableOffset = *(UINTN*) ((UINT8*)Rsdt + sizeof (DESCRIPTION_HEADER) + i * 4);\r
+ CurrentTable = (DESCRIPTION_HEADER*)tableOffset;\r
+ if ( CurrentTable->Signature == Signature ) {\r
+ return CurrentTable;\r
+ }\r
+ }\r
+ }\r
+ return NULL;\r
+}\r
+\r
+//\r
+//\r
+// Routine Description:\r
+//\r
+// Update table checksum\r
+//\r
+// Arguments:\r
+//\r
+// TablePtr - table pointer\r
+//\r
+// Returns:\r
+//\r
+// none\r
+//\r
+//\r
+VOID\r
+ACPI_SetTableChecksum (\r
+ IN VOID* TablePtr\r
+ )\r
+{\r
+ UINT8 Checksum;\r
+ Checksum = 0;\r
+ ((DESCRIPTION_HEADER*)TablePtr)->Checksum = 0;\r
+ Checksum = ACPI_GetTableChecksum (TablePtr);\r
+ ((DESCRIPTION_HEADER*)TablePtr)->Checksum = (UINT8)(0x100 - Checksum);\r
+}\r
+\r
+//\r
+//\r
+// Routine Description:\r
+//\r
+// Get table checksum\r
+//\r
+// Arguments:\r
+//\r
+// TablePtr - table pointer\r
+//\r
+// Returns:\r
+//\r
+// none\r
+//\r
+//\r
+UINT8\r
+ACPI_GetTableChecksum (\r
+ IN VOID* TablePtr\r
+ )\r
+{\r
+ return GetByteSum (TablePtr, ((DESCRIPTION_HEADER*)TablePtr)->Length);\r
+}\r
+\r
+\r
+UINT8\r
+GetByteSum (\r
+ IN VOID* pData,\r
+ IN UINT32 Length\r
+ )\r
+{\r
+ UINT32 i;\r
+ UINT8 Checksum;\r
+ Checksum = 0;\r
+ for ( i = 0; i < Length; i++ ) {\r
+ Checksum = Checksum + (*((UINT8*)pData + i));\r
+ }\r
+ return Checksum;\r
+}\r
+VOID\r
+GetSbAcpiMmioBase (\r
+ OUT UINT32* AcpiMmioBase\r
+ )\r
+{\r
+ UINT32 Value16;\r
+\r
+ ReadPMIO (SB_PMIOA_REG24 + 2, AccWidthUint16, &Value16);\r
+ *AcpiMmioBase = Value16 << 16;\r
+}\r
+\r
+VOID\r
+GetSbAcpiPmBase (\r
+ OUT UINT16* AcpiPmBase\r
+ )\r
+{\r
+ ReadPMIO (SB_PMIOA_REG60, AccWidthUint16, AcpiPmBase);\r
+}\r
+\r
--- /dev/null
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+\r
+/**\r
+ * RSDP - ACPI 2.0 table RSDP\r
+ */\r
+typedef struct _RSDP\r
+{\r
+ UINT64 Signature; /* RSDP signature "RSD PTR" */\r
+ UINT8 Checksum; /* checksum of the first 20 bytes */\r
+ UINT8 OEMID[6]; /* OEM ID, "LXBIOS" */\r
+ UINT8 Revision; /* 0 for APCI 1.0, 2 for ACPI 2.0 */\r
+ UINT32 RsdtAddress; /* physical address of RSDT */\r
+ UINT32 Length; /* total length of RSDP (including extended part) */\r
+ UINT64 XsdtAddress; /* physical address of XSDT */\r
+ UINT8 ExtendedChecksum; /* chechsum of whole table */\r
+ UINT8 Reserved[3];\r
+} RSDP;\r
+\r
+\r
+/**\r
+ * DESCRIPTION_HEADER - ACPI common table header\r
+ */\r
+typedef struct _DESCRIPTION_HEADER\r
+{\r
+ UINT32 Signature; /* ACPI signature (4 ASCII characters) */\r
+ UINT32 Length; /* Length of table, in bytes, including header */\r
+ UINT8 Revision; /* ACPI Specification minor version # */\r
+ UINT8 Checksum; /* To make sum of entire table == 0 */\r
+ UINT8 OEMID[6]; /* OEM identification */\r
+ UINT8 OEMTableID[8]; /* OEM table identification */\r
+ UINT32 OEMRevision; /* OEM revision number */\r
+ UINT32 CreatorID; /* ASL compiler vendor ID */\r
+ UINT32 CreatorRevision; /* ASL compiler revision number */\r
+} DESCRIPTION_HEADER;\r
+\r
+VOID* ACPI_LocateTable (IN UINT32 Signature);\r
+VOID ACPI_SetTableChecksum (IN VOID* TablePtr);\r
+UINT8 ACPI_GetTableChecksum (IN VOID* TablePtr);\r
+UINT8 GetByteSum (IN VOID* pData, IN UINT32 Length);\r
--- /dev/null
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+\r
+#include "SBPLATFORM.h"\r
+\r
+UINT8\r
+getNumberOfCpuCores (\r
+ OUT VOID\r
+ )\r
+{\r
+ UINT8 Result;\r
+ Result = 1;\r
+ Result = ReadNumberOfCpuCores ();\r
+ return Result;\r
+}\r
+\r
+UINT32\r
+readAlink (\r
+ IN UINT32 Index\r
+ )\r
+{\r
+ UINT32 Data;\r
+ WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32, &Index);\r
+ ReadIO (ALINK_ACCESS_DATA, AccWidthUint32, &Data);\r
+ //Clear Index\r
+ Index = 0;\r
+ WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32, &Index);\r
+ return Data;\r
+}\r
+\r
+VOID\r
+writeAlink (\r
+ IN UINT32 Index,\r
+ IN UINT32 Data\r
+ )\r
+{\r
+ WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &Index);\r
+ WriteIO (ALINK_ACCESS_DATA, AccWidthUint32 | S3_SAVE, &Data);\r
+ //Clear Index\r
+ Index = 0;\r
+ WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &Index);\r
+}\r
+\r
+VOID\r
+rwAlink (\r
+ IN UINT32 Index,\r
+ IN UINT32 AndMask,\r
+ IN UINT32 OrMask\r
+ )\r
+{\r
+ UINT32 AccesType;\r
+ AccesType = Index & 0xE0000000;\r
+ if (AccesType == (AXINDC << 29)) {\r
+ writeAlink ((SB_AX_INDXC_REG30 | AccesType), Index & 0x1FFFFFFF);\r
+ Index = (SB_AX_DATAC_REG34 | AccesType);\r
+ } else if (AccesType == (AXINDP << 29)) {\r
+ writeAlink ((SB_AX_INDXP_REG38 | AccesType), Index & 0x1FFFFFFF);\r
+ Index = (SB_AX_DATAP_REG3C | AccesType);\r
+ }\r
+ writeAlink (Index, (readAlink (Index) & AndMask) | OrMask );\r
+}\r
+\r
--- /dev/null
+/**\r
+ * @file\r
+ *\r
+ * Southbridge IO access common routine\r
+ *\r
+ *\r
+ *\r
+ * @xrefitem bom "File Content Label" "Release Content"\r
+ * @e project: CIMx-SB\r
+ * @e sub-project:\r
+ * @e \$Revision:$ @e \$Date:$\r
+ *\r
+ */\r
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+\r
+#include "SBPLATFORM.h"\r
+\r
+/*----------------------------------------------------------------------------------------*/\r
+/**\r
+ * SbStall - Delay routine\r
+ *\r
+ *\r
+ *\r
+ * @param[in] uSec\r
+ *\r
+ */\r
+VOID\r
+SbStall (\r
+ IN UINT32 uSec\r
+ )\r
+{\r
+ UINT16 timerAddr;\r
+ UINT32 startTime;\r
+ UINT32 elapsedTime;\r
+\r
+ ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG64, AccWidthUint16, &timerAddr);\r
+ if ( timerAddr == 0 ) {\r
+ uSec = uSec / 2;\r
+ while ( uSec != 0 ) {\r
+ ReadIO (0x80, AccWidthUint8, (UINT8 *) (&startTime));\r
+ uSec--;\r
+ }\r
+ } else {\r
+ ReadIO (timerAddr, AccWidthUint32, &startTime);\r
+ for ( ;; ) {\r
+ ReadIO (timerAddr, AccWidthUint32, &elapsedTime);\r
+ if ( elapsedTime < startTime ) {\r
+ elapsedTime = elapsedTime + 0xFFFFFFFF - startTime;\r
+ } else {\r
+ elapsedTime = elapsedTime - startTime;\r
+ }\r
+ if ( (elapsedTime * 28 / 100) > uSec ) {\r
+ break;\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/*----------------------------------------------------------------------------------------*/\r
+/**\r
+ * SbReset - Generate a reset command\r
+ *\r
+ *\r
+ *\r
+ * @param[in] OpFlag - Dummy\r
+ *\r
+ */\r
+VOID\r
+SbReset (\r
+ IN UINT8 OpFlag\r
+ )\r
+{\r
+ UINT8 Temp;\r
+ Temp = OpFlag;\r
+ RWIO (0xcf9, AccWidthUint8, 0x0, 0x06);\r
+}\r
+\r
+/*----------------------------------------------------------------------------------------*/\r
+/**\r
+ * outPort80 - Send data to PORT 80 (debug port)\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pcode - debug code (32 bits)\r
+ *\r
+ */\r
+VOID\r
+outPort80 (\r
+ IN UINT32 pcode\r
+ )\r
+{\r
+ WriteIO (0x80, AccWidthUint8, &pcode);\r
+ return;\r
+}\r
+\r
+/**\r
+ * AmdSbCopyMem - Memory copy\r
+ *\r
+ * @param[in] pDest - Destance address point\r
+ * @param[in] pSource - Source Address point\r
+ * @param[in] Length - Data length\r
+ *\r
+ */\r
+VOID\r
+AmdSbCopyMem (\r
+ IN VOID* pDest,\r
+ IN VOID* pSource,\r
+ IN UINTN Length\r
+ )\r
+{\r
+ UINTN i;\r
+ UINT8 *Ptr;\r
+ UINT8 *Source;\r
+ Ptr = (UINT8*)pDest;\r
+ Source = (UINT8*)pSource;\r
+ for (i = 0; i < Length; i++) {\r
+ *Ptr = *Source;\r
+ Source++;\r
+ Ptr++;\r
+ }\r
+}\r
--- /dev/null
+/**\r
+ * @file\r
+ *\r
+ * Southbridge IO access common routine define file\r
+ *\r
+ *\r
+ *\r
+ * @xrefitem bom "File Content Label" "Release Content"\r
+ * @e project: CIMx-SB\r
+ * @e sub-project:\r
+ * @e \$Revision:$ @e \$Date:$\r
+ *\r
+ */\r
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+\r
+\r
+//AMDSBLIB Routines\r
+\r
+/**\r
+ * SbStall - Delay routine\r
+ *\r
+ *\r
+ *\r
+ * @param[in] uSec\r
+ *\r
+ */\r
+VOID SbStall (IN UINT32 uSec);\r
+\r
+/**\r
+ * SbReset - Generate a reset command\r
+ *\r
+ *\r
+ *\r
+ * @param[in] OpFlag - Dummy\r
+ *\r
+ */\r
+VOID SbReset (IN UINT8 OpFlag);\r
+\r
+/**\r
+ * outPort80 - Send data to PORT 80 (debug port)\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pcode - debug code (32 bits)\r
+ *\r
+ */\r
+VOID outPort80 (IN UINT32 pcode);\r
+\r
+/**\r
+ * getEfuseStatue - Get Efuse status\r
+ *\r
+ *\r
+ * @param[in] Value - Return Chip strap status\r
+ *\r
+ */\r
+VOID getEfuseStatus (IN VOID* Value);\r
+\r
+/**\r
+ * AmdSbDispatcher - Dispatch Southbridge function\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+AGESA_STATUS AmdSbDispatcher (IN VOID *pConfig);\r
+\r
+/**\r
+ * AmdSbCopyMem - Memory copy\r
+ *\r
+ * @param[in] pDest - Destance address point\r
+ * @param[in] pSource - Source Address point\r
+ * @param[in] Length - Data length\r
+ *\r
+ */\r
+VOID AmdSbCopyMem (IN VOID* pDest, IN VOID* pSource, IN UINTN Length);\r
--- /dev/null
+/**\r
+ * @file\r
+ *\r
+ * Config Southbridge HD Audio Controller\r
+ *\r
+ *\r
+ *\r
+ * @xrefitem bom "File Content Label" "Release Content"\r
+ * @e project: CIMx-SB\r
+ * @e sub-project:\r
+ * @e \$Revision:$ @e \$Date:$\r
+ *\r
+ */\r
+\r
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+\r
+\r
+#include "SBPLATFORM.h"\r
+\r
+//\r
+// Declaration of local functions\r
+//\r
+\r
+VOID configureAzaliaPinCmd (IN AMDSBCFG* pConfig, IN UINT32 ddBAR0, IN UINT8 dbChannelNum);\r
+VOID configureAzaliaSetConfigD4Dword (IN CODECENTRY* tempAzaliaCodecEntryPtr, IN UINT32 ddChannelNum, IN UINT32 ddBAR0);\r
+\r
+/**\r
+ * Pin Config for ALC880, ALC882 and ALC883.\r
+ *\r
+ *\r
+ *\r
+ */\r
+CODECENTRY AzaliaCodecAlc882Table[] =\r
+{\r
+ {0x14, 0x01014010},\r
+ {0x15, 0x01011012},\r
+ {0x16, 0x01016011},\r
+ {0x17, 0x01012014},\r
+ {0x18, 0x01A19030},\r
+ {0x19, 0x411111F0},\r
+ {0x1a, 0x01813080},\r
+ {0x1b, 0x411111F0},\r
+ {0x1C, 0x411111F0},\r
+ {0x1d, 0x411111F0},\r
+ {0x1e, 0x01441150},\r
+ {0x1f, 0x01C46160},\r
+ {0xff, 0xffffffff}\r
+};\r
+\r
+/**\r
+ * Pin Config for ALC0262.\r
+ *\r
+ *\r
+ *\r
+ */\r
+CODECENTRY AzaliaCodecAlc262Table[] =\r
+{\r
+ {0x14, 0x01014010},\r
+ {0x15, 0x411111F0},\r
+ {0x16, 0x411111F0},\r
+ {0x18, 0x01A19830},\r
+ {0x19, 0x02A19C40},\r
+ {0x1a, 0x01813031},\r
+ {0x1b, 0x02014C20},\r
+ {0x1c, 0x411111F0},\r
+ {0x1d, 0x411111F0},\r
+ {0x1e, 0x0144111E},\r
+ {0x1f, 0x01C46150},\r
+ {0xff, 0xffffffff}\r
+};\r
+\r
+/**\r
+ * Pin Config for ALC0269.\r
+ *\r
+ *\r
+ *\r
+ */\r
+CODECENTRY AzaliaCodecAlc269Table[] =\r
+{\r
+ {0x12, 0x99A30960},\r
+ {0x14, 0x99130110},\r
+ {0x15, 0x0221401F},\r
+ {0x16, 0x99130120},\r
+ {0x18, 0x01A19850},\r
+ {0x19, 0x02A15951},\r
+ {0x1a, 0x01813052},\r
+ {0x1b, 0x0181405F},\r
+ {0x1d, 0x40134601},\r
+ {0x1e, 0x01441130},\r
+ {0x11, 0x18567140},\r
+ {0x20, 0x0030FFFF},\r
+ {0xff, 0xffffffff}\r
+};\r
+\r
+/**\r
+ * Pin Config for ALC0861.\r
+ *\r
+ *\r
+ *\r
+ */\r
+CODECENTRY AzaliaCodecAlc861Table[] =\r
+{\r
+ {0x01, 0x8086C601},\r
+ {0x0B, 0x01014110},\r
+ {0x0C, 0x01813140},\r
+ {0x0D, 0x01A19941},\r
+ {0x0E, 0x411111F0},\r
+ {0x0F, 0x02214420},\r
+ {0x10, 0x02A1994E},\r
+ {0x11, 0x99330142},\r
+ {0x12, 0x01451130},\r
+ {0x1F, 0x411111F0},\r
+ {0x20, 0x411111F0},\r
+ {0x23, 0x411111F0},\r
+ {0xff, 0xffffffff}\r
+};\r
+\r
+/**\r
+ * Pin Config for ALC0889.\r
+ *\r
+ *\r
+ *\r
+ */\r
+CODECENTRY AzaliaCodecAlc889Table[] =\r
+{\r
+ {0x11, 0x411111F0},\r
+ {0x14, 0x01014010},\r
+ {0x15, 0x01011012},\r
+ {0x16, 0x01016011},\r
+ {0x17, 0x01013014},\r
+ {0x18, 0x01A19030},\r
+ {0x19, 0x411111F0},\r
+ {0x1a, 0x411111F0},\r
+ {0x1b, 0x411111F0},\r
+ {0x1C, 0x411111F0},\r
+ {0x1d, 0x411111F0},\r
+ {0x1e, 0x01442150},\r
+ {0x1f, 0x01C42160},\r
+ {0xff, 0xffffffff}\r
+};\r
+\r
+/**\r
+ * Pin Config for ADI1984.\r
+ *\r
+ *\r
+ *\r
+ */\r
+CODECENTRY AzaliaCodecAd1984Table[] =\r
+{\r
+ {0x11, 0x0221401F},\r
+ {0x12, 0x90170110},\r
+ {0x13, 0x511301F0},\r
+ {0x14, 0x02A15020},\r
+ {0x15, 0x50A301F0},\r
+ {0x16, 0x593301F0},\r
+ {0x17, 0x55A601F0},\r
+ {0x18, 0x55A601F0},\r
+ {0x1A, 0x91F311F0},\r
+ {0x1B, 0x014511A0},\r
+ {0x1C, 0x599301F0},\r
+ {0xff, 0xffffffff}\r
+};\r
+\r
+/**\r
+ * FrontPanel Config table list\r
+ *\r
+ *\r
+ *\r
+ */\r
+CODECENTRY FrontPanelAzaliaCodecTableList[] =\r
+{\r
+ {0x19, 0x02A19040},\r
+ {0x1b, 0x02214020},\r
+ {0xff, 0xffffffff}\r
+};\r
+\r
+/**\r
+ * Current HD Audio support codec list\r
+ *\r
+ *\r
+ *\r
+ */\r
+CODECTBLLIST azaliaCodecTableList[] =\r
+{\r
+ {0x010ec0880, &AzaliaCodecAlc882Table[0]},\r
+ {0x010ec0882, &AzaliaCodecAlc882Table[0]},\r
+ {0x010ec0883, &AzaliaCodecAlc882Table[0]},\r
+ {0x010ec0885, &AzaliaCodecAlc882Table[0]},\r
+ {0x010ec0889, &AzaliaCodecAlc889Table[0]},\r
+ {0x010ec0262, &AzaliaCodecAlc262Table[0]},\r
+ {0x010ec0269, &AzaliaCodecAlc269Table[0]},\r
+ {0x010ec0861, &AzaliaCodecAlc861Table[0]},\r
+ {0x011d41984, &AzaliaCodecAd1984Table[0]},\r
+ { (UINT32) 0x0FFFFFFFF, (CODECENTRY*) (UINTN)0x0FFFFFFFF}\r
+};\r
+\r
+/**\r
+ * azaliaInitBeforePciEnum - Config HD Audio Before PCI emulation\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+azaliaInitBeforePciEnum (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ if ( pConfig->AzaliaController == 1 ) {\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, 0);\r
+ } else {\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, BIT0);\r
+ if ( pConfig->BuildParameters.HdAudioMsi) {\r
+ RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG44, AccWidthUint32 | S3_SAVE, ~BIT8, BIT8);\r
+ RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG60, AccWidthUint32 | S3_SAVE, ~BIT16, BIT16);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * azaliaInitAfterPciEnum - Config HD Audio after PCI emulation\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+azaliaInitAfterPciEnum (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT8 Data;\r
+ UINT8 i;\r
+ UINT8 dbEnableAzalia;\r
+ UINT8 dbPinRouting;\r
+ UINT8 dbChannelNum;\r
+ UINT8 dbTempVariable;\r
+ UINT16 dwTempVariable;\r
+ UINT32 ddBAR0;\r
+ UINT32 ddTempVariable;\r
+ dbEnableAzalia = 0;\r
+ dbChannelNum = 0;\r
+ dbTempVariable = 0;\r
+ dwTempVariable = 0;\r
+ ddBAR0 = 0;\r
+ ddTempVariable = 0;\r
+\r
+ if ( pConfig->AzaliaController == 1 ) {\r
+ return;\r
+ }\r
+\r
+ if ( pConfig->AzaliaController != 1 ) {\r
+ RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~BIT1, BIT1);\r
+ if ( pConfig->BuildParameters.AzaliaSsid != NULL ) {\r
+ RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.AzaliaSsid);\r
+ } \r
+ ReadPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0);\r
+ if ( ddBAR0 != 0 ) {\r
+ if ( ddBAR0 != 0xFFFFFFFF ) {\r
+ ddBAR0 &= ~(0x03FFF);\r
+ dbEnableAzalia = 1;\r
+ }\r
+ }\r
+ }\r
+\r
+ if ( dbEnableAzalia ) {\r
+ // Get SDIN Configuration\r
+ if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin0 == 2 ) {\r
+ RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x3E);\r
+ RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x00);\r
+ } else {\r
+ RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x0);\r
+ RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG167, AccWidthUint8, 0, 0x01);\r
+ }\r
+ if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin1 == 2 ) {\r
+ RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x3E);\r
+ RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x00);\r
+ } else {\r
+ RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x0);\r
+ RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG168, AccWidthUint8, 0, 0x01);\r
+ }\r
+ if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin2 == 2 ) {\r
+ RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x3E);\r
+ RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x00);\r
+ } else {\r
+ RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x0);\r
+ RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG169, AccWidthUint8, 0, 0x01);\r
+ }\r
+ if ( pConfig->AZALIACONFIG.AzaliaConfig.AzaliaSdin3 == 2 ) {\r
+ RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x3E);\r
+ RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x00);\r
+ } else {\r
+ RWMEM (ACPI_MMIO_BASE + GPIO_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x0);\r
+ RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG170, AccWidthUint8, 0, 0x01);\r
+ }\r
+ // INT#A Azalia resource\r
+ Data = 0x93; // Azalia APIC index\r
+ WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &Data);\r
+ Data = 0x10; // IRQ16 (INTA#)\r
+ WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &Data);\r
+\r
+ i = 11;\r
+ do {\r
+ ReadMEM ( ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);\r
+ dbTempVariable |= BIT0;\r
+ WriteMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);\r
+ SbStall (1000);\r
+ ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);\r
+ i--;\r
+ } while ((! (dbTempVariable & BIT0)) && (i > 0) );\r
+\r
+ if ( i == 0 ) {\r
+ return;\r
+ }\r
+\r
+ SbStall (1000);\r
+ ReadMEM ( ddBAR0 + SB_AZ_BAR_REG0E, AccWidthUint16, &dwTempVariable);\r
+ if ( dwTempVariable & 0x0F ) {\r
+\r
+ //atleast one azalia codec found\r
+ // ?? E0 is not real register what we expect. we have change to GPIO/and program GPIO Mux\r
+ //ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGE0, AccWidthUint8, &dbPinRouting);\r
+ dbPinRouting = pConfig->AZALIACONFIG.AzaliaSdinPin;\r
+ do {\r
+ if ( ( ! (dbPinRouting & BIT0) ) && (dbPinRouting & BIT1) ) {\r
+// dbChannelNum = 3;\r
+ configureAzaliaPinCmd (pConfig, ddBAR0, dbChannelNum);\r
+ }\r
+ dbPinRouting >>= 2;\r
+ dbChannelNum++;\r
+ } while ( dbChannelNum != 4 );\r
+ } else {\r
+ //No Azalia codec found\r
+ if ( pConfig->AzaliaController != 2 ) {\r
+ dbEnableAzalia = 0; //set flag to disable Azalia\r
+ }\r
+ }\r
+ }\r
+\r
+ if ( dbEnableAzalia ) {\r
+ //redo clear reset\r
+ do {\r
+ dwTempVariable = 0;\r
+ WriteMEM ( ddBAR0 + SB_AZ_BAR_REG0C, AccWidthUint16 | S3_SAVE, &dwTempVariable);\r
+ ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);\r
+ dbTempVariable &= ~(BIT0);\r
+ WriteMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);\r
+ ReadMEM (ddBAR0 + SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);\r
+ } while ( dbTempVariable & BIT0 );\r
+\r
+ if ( pConfig->AzaliaSnoop == 1 ) {\r
+ RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG42, AccWidthUint8 | S3_SAVE, 0xFF, BIT1 + BIT0);\r
+ }\r
+ } else {\r
+ //disable Azalia controller\r
+ RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint16 | S3_SAVE, 0, 0);\r
+ // RWPMIO (SB_PMIO_REG59, AccWidthUint8 | S3_SAVE, ~BIT3, 0);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, 0);\r
+ // RWPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGFC, AccWidthUint8 | S3_SAVE, 0, 0x55);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEB, AccWidthUint8, ~BIT0, 0);\r
+ }\r
+}\r
+\r
+/**\r
+ * configureAzaliaPinCmd - Configuration HD Audio PIN Command\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ * @param[in] ddBAR0 HD Audio BAR0 base address.\r
+ * @param[in] dbChannelNum Channel Number.\r
+ *\r
+ */\r
+VOID\r
+configureAzaliaPinCmd (\r
+ IN AMDSBCFG* pConfig,\r
+ IN UINT32 ddBAR0,\r
+ IN UINT8 dbChannelNum\r
+ )\r
+{\r
+ UINT32 ddTempVariable;\r
+ UINT32 ddChannelNum;\r
+ CODECTBLLIST* ptempAzaliaOemCodecTablePtr;\r
+ CODECENTRY* tempAzaliaCodecEntryPtr;\r
+\r
+ if ( (pConfig->AzaliaPinCfg) != 1 ) {\r
+ return;\r
+ }\r
+\r
+ ddChannelNum = dbChannelNum << 28;\r
+ ddTempVariable = 0xF0000;\r
+ ddTempVariable |= ddChannelNum;\r
+\r
+ WriteMEM (ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddTempVariable);\r
+ SbStall (600);\r
+ ReadMEM (ddBAR0 + SB_AZ_BAR_REG64, AccWidthUint32 | S3_SAVE, &ddTempVariable);\r
+\r
+ if ( ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) (UINTN)0xFFFFFFFF))) {\r
+ ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) FIXUP_PTR (&azaliaCodecTableList[0]);\r
+ } else {\r
+ ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr;\r
+ }\r
+\r
+ while ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF ) {\r
+ if ( ptempAzaliaOemCodecTablePtr->CodecID == ddTempVariable ) {\r
+ break;\r
+ } else {\r
+ ++ptempAzaliaOemCodecTablePtr;\r
+ }\r
+ }\r
+\r
+ if ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF ) {\r
+ tempAzaliaCodecEntryPtr = (CODECENTRY*) ptempAzaliaOemCodecTablePtr->CodecTablePtr;\r
+\r
+ if ( ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->AZOEMTBL.pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) (UINTN)0xFFFFFFFF)) ) {\r
+ tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR (tempAzaliaCodecEntryPtr);\r
+ }\r
+ configureAzaliaSetConfigD4Dword (tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0);\r
+ if ( pConfig->AzaliaFrontPanel != 1 ) {\r
+ if ( (pConfig->AzaliaFrontPanel == 2) || (pConfig->FrontPanelDetected == 1) ) {\r
+ if ( ((pConfig->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr) == NULL) || ((pConfig->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr) == (VOID*) (UINTN)0xFFFFFFFF) ) {\r
+ tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR (&FrontPanelAzaliaCodecTableList[0]);\r
+ } else {\r
+ tempAzaliaCodecEntryPtr = (CODECENTRY*) pConfig->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr;\r
+ }\r
+ configureAzaliaSetConfigD4Dword (tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0);\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * configureAzaliaSetConfigD4Dword - Configuration HD Audio Codec table\r
+ *\r
+ *\r
+ * @param[in] tempAzaliaCodecEntryPtr HD Audio Codec table structure pointer.\r
+ * @param[in] ddChannelNum HD Audio Channel Number.\r
+ * @param[in] ddBAR0 HD Audio BAR0 base address.\r
+ *\r
+ */\r
+VOID\r
+configureAzaliaSetConfigD4Dword (\r
+ IN CODECENTRY* tempAzaliaCodecEntryPtr,\r
+ IN UINT32 ddChannelNum,\r
+ IN UINT32 ddBAR0\r
+ )\r
+{\r
+ UINT8 dbtemp1;\r
+ UINT8 dbtemp2;\r
+ UINT8 i;\r
+ UINT32 ddtemp;\r
+ UINT32 ddtemp2;\r
+ ddtemp = 0;\r
+ ddtemp2 = 0;\r
+ while ( (tempAzaliaCodecEntryPtr->Nid) != 0xFF ) {\r
+ dbtemp1 = 0x20;\r
+ if ( (tempAzaliaCodecEntryPtr->Nid) == 0x1 ) {\r
+ dbtemp1 = 0x24;\r
+ }\r
+\r
+ ddtemp = tempAzaliaCodecEntryPtr->Nid;\r
+ ddtemp &= 0xff;\r
+ ddtemp <<= 20;\r
+ ddtemp |= ddChannelNum;\r
+\r
+ ddtemp |= (0x700 << 8);\r
+ for ( i = 4; i > 0; i-- ) {\r
+ do {\r
+ ReadMEM (ddBAR0 + SB_AZ_BAR_REG68, AccWidthUint32, &ddtemp2);\r
+ } while ( ddtemp2 & BIT0 );\r
+\r
+ dbtemp2 = (UINT8) (( (tempAzaliaCodecEntryPtr->Byte40) >> ((4 - i) * 8 ) ) & 0xff);\r
+ ddtemp = (ddtemp & 0xFFFF0000) + ((dbtemp1 - i) << 8) + dbtemp2;\r
+ WriteMEM (ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddtemp);\r
+ SbStall (60);\r
+ }\r
+ ++tempAzaliaCodecEntryPtr;\r
+ }\r
+}\r
+\r
--- /dev/null
+/**\r
+ * @file\r
+ *\r
+ * Function dispatcher.\r
+ *\r
+ *\r
+ *\r
+ * @xrefitem bom "File Content Label" "Release Content"\r
+ * @e project: CIMx-SB\r
+ * @e sub-project:\r
+ * @e \$Revision:$ @e \$Date:$\r
+ *\r
+ */\r
+\r
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+/*----------------------------------------------------------------------------------------\r
+ * M O D U L E S U S E D\r
+ *----------------------------------------------------------------------------------------\r
+ */\r
+\r
+#include "SBPLATFORM.h"\r
+\r
+/*----------------------------------------------------------------------------------------\r
+ * P R O T O T Y P E S O F L O C A L F U N C T I O N S\r
+ *----------------------------------------------------------------------------------------\r
+*/\r
+\r
+\r
+//\r
+// Declaration of local functions\r
+//\r
+\r
+VOID saveConfigPointer (IN AMDSBCFG* pConfig);\r
+VOID* VerifyImage (IN UINT64 Signature, IN VOID* ImagePtr);\r
+VOID* LocateImage (IN UINT64 Signature);\r
+\r
+/*----------------------------------------------------------------------------------------\r
+ * T Y P E D E F S A N D S T R U C T U R E S\r
+ *----------------------------------------------------------------------------------------\r
+ */\r
+\r
+/*----------------------------------------------------------------------------------------\r
+ * E X P O R T E D F U N C T I O N S\r
+ *----------------------------------------------------------------------------------------\r
+ */\r
+\r
+/**\r
+ * AmdSbDispatcher - Dispatch Southbridge function\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+AGESA_STATUS\r
+AmdSbDispatcher (\r
+ IN VOID *pConfig\r
+ )\r
+{\r
+ AGESA_STATUS Status;\r
+\r
+#ifdef B1_IMAGE\r
+ VOID *pAltImagePtr;\r
+ CIM_IMAGE_ENTRY AltImageEntry;\r
+#endif\r
+\r
+ UINT64 tdValue;\r
+ tdValue = 0x32314130384253ULL;\r
+\r
+#ifdef B1_IMAGE\r
+ pAltImagePtr = NULL;\r
+#endif\r
+ Status = AGESA_UNSUPPORTED;\r
+\r
+#ifdef B1_IMAGE\r
+ if ((UINT32) (UINTN) (((AMD_CONFIG_PARAMS*)pConfig)->AltImageBasePtr) != 0xffffffff ) {\r
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->AltImageBasePtr ) {\r
+ pAltImagePtr = VerifyImage ( tdValue, (VOID*) (UINTN) ((AMD_CONFIG_PARAMS*)pConfig)->AltImageBasePtr);\r
+ }\r
+ if ( pAltImagePtr == NULL ) {\r
+ pAltImagePtr = LocateImage ( tdValue );\r
+ }\r
+ if ( pAltImagePtr != NULL ) {\r
+ ((AMD_CONFIG_PARAMS*)pConfig)->ImageBasePtr = (UINT32) (UINTN) pAltImagePtr;\r
+ AltImageEntry = (CIM_IMAGE_ENTRY) (UINTN) ((UINT32) (UINTN) pAltImagePtr + (UINT32) (((AMD_IMAGE_HEADER*) (UINTN) pAltImagePtr)->EntryPointAddress));\r
+ (*AltImageEntry) (pConfig);\r
+ return Status;\r
+ }\r
+ }\r
+#endif\r
+ saveConfigPointer (pConfig);\r
+\r
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_POWERON_INIT ) {\r
+ sbPowerOnInit ((AMDSBCFG*) pConfig);\r
+ }\r
+\r
+#ifndef B1_IMAGE\r
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_INIT ) {\r
+ sbBeforePciInit ((AMDSBCFG*)pConfig);\r
+ }\r
+\r
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_INIT ) {\r
+ sbAfterPciInit ((AMDSBCFG*)pConfig);\r
+ }\r
+\r
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_MID_POST_INIT ) {\r
+ sbMidPostInit ((AMDSBCFG*)pConfig);\r
+ }\r
+\r
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_LATE_POST_INIT ) {\r
+ sbLatePost ((AMDSBCFG*)pConfig);\r
+ }\r
+\r
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_RESTORE_INIT ) {\r
+ sbBeforePciRestoreInit ((AMDSBCFG*)pConfig);\r
+ }\r
+\r
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_RESTORE_INIT ) {\r
+ sbAfterPciRestoreInit ((AMDSBCFG*)pConfig);\r
+ }\r
+\r
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_SERVICE ) {\r
+ sbSmmService ((AMDSBCFG*)pConfig);\r
+ }\r
+\r
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_ACPION ) {\r
+ sbSmmAcpiOn ((AMDSBCFG*)pConfig);\r
+ }\r
+\r
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_EC_FANCONTROL ) {\r
+ sbECfancontrolservice((AMDSBCFG*)pConfig);;\r
+ }\r
+#endif\r
+ return Status;\r
+}\r
+\r
+/**\r
+ * LocateImage - Locate Southbridge CIMx module\r
+ *\r
+ *\r
+ *\r
+ * @param[in] Signature Southbridge CIMx image signature.\r
+ *\r
+ */\r
+VOID*\r
+LocateImage (\r
+ IN UINT64 Signature\r
+ )\r
+{\r
+ VOID *Result;\r
+ UINT32 ImagePtr;\r
+ ImagePtr = 0xffffffff - (IMAGE_ALIGN - 1);\r
+\r
+ while ( ImagePtr >= (0xfffffff - (NUM_IMAGE_LOCATION * IMAGE_ALIGN - 1)) ) {\r
+#ifdef x64\r
+ 12346789\r
+#else\r
+ Result = VerifyImage (Signature, (VOID*) ImagePtr);\r
+#endif\r
+ if ( Result != NULL ) {\r
+ return Result;\r
+ }\r
+ ImagePtr -= IMAGE_ALIGN;\r
+ }\r
+ return NULL;\r
+}\r
+\r
+/**\r
+ * VerifyImage - Verify Southbridge CIMx module\r
+ *\r
+ *\r
+ * @param[in] Signature Southbridge CIMx image signature.\r
+ * @param[in] ImagePtr Southbridge CIMx image address.\r
+ *\r
+ */\r
+VOID*\r
+VerifyImage (\r
+ IN UINT64 Signature,\r
+ IN VOID* ImagePtr\r
+ )\r
+{\r
+ UINT16 *TempImagePtr;\r
+ UINT16 Sum;\r
+ UINT32 i;\r
+ Sum = 0;\r
+ //if ( (*((UINT32*)ImagePtr) == 'DMA$' && ((CIMFILEHEADER*)ImagePtr)->CreatorID == Signature) ) { //gcc multi-character character constant warning\r
+ if ( (*((UINT32*)ImagePtr) == 0x444d4124 && ((CIMFILEHEADER*)ImagePtr)->CreatorID == Signature) ) {//'DMA$'\r
+ //GetImage Image size\r
+ TempImagePtr = (UINT16*)ImagePtr;\r
+ for ( i = 0; i < (((CIMFILEHEADER*)ImagePtr)->ImageSize); i += 2 ) {\r
+ Sum = Sum + *TempImagePtr;\r
+ TempImagePtr++;\r
+ }\r
+ if ( Sum == 0 ) {\r
+ return ImagePtr;\r
+ }\r
+ }\r
+ return NULL;\r
+}\r
+\r
+/**\r
+ * saveConfigPointer - Verify Southbridge CIMx module\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+saveConfigPointer (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT8 dbReg;\r
+ UINT8 i;\r
+ UINT32 ddValue;\r
+\r
+ ddValue = (UINT32) (UINTN)pConfig;\r
+ dbReg = SB_ECMOS_REG08;\r
+\r
+ for ( i = 0; i <= 3; i++ ) {\r
+ WriteIO (SB_IOMAP_REG72, AccWidthUint8, &dbReg);\r
+ WriteIO (SB_IOMAP_REG73, AccWidthUint8, (UINT8*)&ddValue);\r
+ ddValue = (ddValue >> 8);\r
+ dbReg++;\r
+ }\r
+}\r
--- /dev/null
+\r
+/**\r
+ * @file\r
+ *\r
+ * Config Southbridge EC Controller\r
+ *\r
+ * Init EC features.\r
+ *\r
+ * @xrefitem bom "File Content Label" "Release Content"\r
+ * @e project: CIMx-SB\r
+ * @e sub-project:\r
+ * @e \$Revision:$ @e \$Date:$\r
+ *\r
+ */\r
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+\r
+#include "SBPLATFORM.h"\r
+\r
+#ifndef NO_EC_SUPPORT\r
+\r
+/**\r
+ * Config EC controller during power-on\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+ecPowerOnInit (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ //Enable config mode\r
+ EnterEcConfig ();\r
+\r
+ //Do settings for mailbox - logical device 0x09\r
+ RWEC8 (0x07, 0x00, 0x09); //switch to device 9 (Mailbox)\r
+ RWEC8 (0x60, 0x00, (MailBoxPort >> 8)); //set MSB of Mailbox port\r
+ RWEC8 (0x61, 0x00, (MailBoxPort & 0xFF)); //set LSB of Mailbox port\r
+ RWEC8 (0x30, 0x00, 0x01); //;Enable Mailbox Registers Interface, bit0=1\r
+\r
+ if ( pConfig->BuildParameters.EcKbd == ENABLED) {\r
+ //Enable KBRST#, IRQ1 & IRQ12, GateA20 Function signal from IMC\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD6, AccWidthUint8, ~BIT8, BIT0 + BIT1 + BIT2 + BIT3);\r
+\r
+ //Disable LPC Decoding of port 60/64\r
+ RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG47), AccWidthUint8 | S3_SAVE, ~BIT5, 0);\r
+\r
+ //Enable logical device 0x07 (Keyboard controller)\r
+ RWEC8 (0x07, 0x00, 0x07);\r
+ RWEC8 (0x30, 0x00, 0x01);\r
+ }\r
+\r
+ if ( pConfig->BuildParameters.EcChannel0 == ENABLED) {\r
+ //Logical device 0x03\r
+ RWEC8 (0x07, 0x00, 0x03);\r
+ RWEC8 (0x60, 0x00, 0x00);\r
+ RWEC8 (0x61, 0x00, 0x62);\r
+ RWEC8 (0x30, 0x00, 0x01); //;Enable Device 8\r
+ }\r
+\r
+ //Enable EC (IMC) to generate SMI to BIOS\r
+ RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGB3, AccWidthUint8, ~BIT6, BIT6);\r
+ ExitEcConfig ();\r
+}\r
+\r
+/**\r
+ * Config EC controller before PCI emulation\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+ecInitBeforePciEnum (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ AMDSBCFG* pTmp; // dummy code\r
+ pTmp = pConfig;\r
+}\r
+\r
+/**\r
+ * Prepare EC controller to boot to OS.\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+ecInitLatePost (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ AMDSBCFG* pTmp; // dummy code\r
+ pTmp = pConfig;\r
+}\r
+#endif\r
--- /dev/null
+/**\r
+ * @file\r
+ *\r
+ * Southbridge EC IO access common routine\r
+ *\r
+ */\r
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+\r
+#include "SBPLATFORM.h"\r
+\r
+// #ifndef NO_EC_SUPPORT\r
+\r
+/*----------------------------------------------------------------------------------------*/\r
+/**\r
+ * EnterEcConfig - Force EC into Config mode\r
+ *\r
+ *\r
+ *\r
+ *\r
+ */\r
+VOID\r
+EnterEcConfig (\r
+ )\r
+{\r
+ UINT16 dwEcIndexPort;\r
+\r
+ ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);\r
+ dwEcIndexPort &= ~(BIT0);\r
+ RWIO (dwEcIndexPort, AccWidthUint8, 0x00, 0x5A);\r
+}\r
+\r
+/*----------------------------------------------------------------------------------------*/\r
+/**\r
+ * ExitEcConfig - Force EC exit Config mode\r
+ *\r
+ *\r
+ *\r
+ *\r
+ */\r
+VOID\r
+ExitEcConfig (\r
+ )\r
+{\r
+ UINT16 dwEcIndexPort;\r
+\r
+ ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);\r
+ dwEcIndexPort &= ~(BIT0);\r
+ RWIO (dwEcIndexPort, AccWidthUint8, 0x00, 0xA5);\r
+}\r
+\r
+/*----------------------------------------------------------------------------------------*/\r
+/**\r
+ * ReadEC8 - Read EC register data\r
+ *\r
+ *\r
+ *\r
+ * @param[in] Address - EC Register Offset Value\r
+ * @param[in] Value - Read Data Buffer\r
+ *\r
+ */\r
+VOID\r
+ReadEC8 (\r
+ IN UINT8 Address,\r
+ IN UINT8* Value\r
+ )\r
+{\r
+ UINT16 dwEcIndexPort;\r
+\r
+ ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);\r
+ dwEcIndexPort &= ~(BIT0);\r
+ WriteIO (dwEcIndexPort, AccWidthUint8, &Address);\r
+ ReadIO (dwEcIndexPort + 1, AccWidthUint8, Value);\r
+}\r
+\r
+/*----------------------------------------------------------------------------------------*/\r
+/**\r
+ * WriteEC8 - Write date into EC register\r
+ *\r
+ *\r
+ *\r
+ * @param[in] Address - EC Register Offset Value\r
+ * @param[in] Value - Write Data Buffer\r
+ *\r
+ */\r
+VOID\r
+WriteEC8 (\r
+ IN UINT8 Address,\r
+ IN UINT8* Value\r
+ )\r
+{\r
+ UINT16 dwEcIndexPort;\r
+\r
+ ReadPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);\r
+ dwEcIndexPort &= ~(BIT0);\r
+\r
+ WriteIO (dwEcIndexPort, AccWidthUint8, &Address);\r
+ WriteIO (dwEcIndexPort + 1, AccWidthUint8, Value);\r
+}\r
+\r
+/*----------------------------------------------------------------------------------------*/\r
+/**\r
+ * RWEC8 - Read/Write EC register\r
+ *\r
+ *\r
+ *\r
+ * @param[in] Address - EC Register Offset Value\r
+ * @param[in] AndMask - Data And Mask 8 bits\r
+ * @param[in] OrMask - Data OR Mask 8 bits\r
+ *\r
+ */\r
+VOID\r
+RWEC8 (\r
+ IN UINT8 Address,\r
+ IN UINT8 AndMask,\r
+ IN UINT8 OrMask\r
+ )\r
+{\r
+ UINT8 Result;\r
+ ReadEC8 (Address, &Result);\r
+ Result = (Result & AndMask) | OrMask;\r
+ WriteEC8 (Address, &Result);\r
+}\r
+\r
+// #endif\r
+\r
--- /dev/null
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+\r
+\r
+VOID WriteECmsg (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value);\r
+VOID WaitForEcLDN9MailboxCmdAck (VOID);\r
+VOID ReadECmsg (IN UINT8 Address, IN UINT8 OpFlag, OUT VOID* Value);\r
+\r
+// IMC Message Register Software Interface\r
+#define CPU_MISC_BUS_DEV_FUN ((0x18 << 3) + 3)\r
+\r
+#define MSG_SYS_TO_IMC 0x80\r
+#define Fun_80 0x80\r
+#define Fun_81 0x81\r
+#define Fun_82 0x82\r
+#define Fun_83 0x83\r
+#define Fun_84 0x84\r
+#define Fun_85 0x85\r
+#define Fun_86 0x86\r
+#define Fun_87 0x87\r
+#define Fun_88 0x88\r
+#define Fun_89 0x89\r
+#define Fun_90 0x90\r
+#define MSG_IMC_TO_SYS 0x81\r
+#define MSG_REG0 0x82\r
+#define MSG_REG1 0x83\r
+#define MSG_REG2 0x84\r
+#define MSG_REG3 0x85\r
+#define MSG_REG4 0x86\r
+#define MSG_REG5 0x87\r
+#define MSG_REG6 0x88\r
+#define MSG_REG7 0x89\r
+#define MSG_REG8 0x8A\r
+#define MSG_REG9 0x8B\r
+#define MSG_REGA 0x8C\r
+#define MSG_REGB 0x8D\r
+#define MSG_REGC 0x8E\r
+#define MSG_REGD 0x8F\r
+\r
+\r
--- /dev/null
+/**\r
+ * @file\r
+ *\r
+ * Southbridge EC IO access common routine\r
+ *\r
+ */\r
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+\r
+#include "SBPLATFORM.h"\r
+#include "ECfan.h"\r
+\r
+VOID\r
+ReadECmsg (\r
+ IN UINT8 Address,\r
+ IN UINT8 OpFlag,\r
+ OUT VOID* Value\r
+ )\r
+{\r
+ UINT8 i;\r
+\r
+ OpFlag = OpFlag & 0x7f;\r
+ if (OpFlag == 0x02) OpFlag = 0x03;\r
+ for (i = 0; i <= OpFlag; i++) {\r
+ WriteIO(MailBoxPort, AccWidthUint8, &Address); // EC_LDN9_MAILBOX_BASE_ADDRESS\r
+ Address++;\r
+ ReadIO(MailBoxPort + 1, AccWidthUint8, (UINT8 *)Value+i); // EC_LDN9_MAILBOX_BASE_ADDRESS\r
+ }\r
+}\r
+\r
+\r
+VOID\r
+WriteECmsg (\r
+ IN UINT8 Address,\r
+ IN UINT8 OpFlag,\r
+ IN VOID* Value\r
+ )\r
+{\r
+ UINT8 i;\r
+\r
+ OpFlag = OpFlag & 0x7f;\r
+ if (OpFlag == 0x02) OpFlag = 0x03;\r
+ for (i = 0; i <= OpFlag; i++) {\r
+ WriteIO(MailBoxPort, AccWidthUint8, &Address); // EC_LDN9_MAILBOX_BASE_ADDRESS\r
+ Address++;\r
+ WriteIO(MailBoxPort + 1, AccWidthUint8, (UINT8 *)Value+i); // EC_LDN9_MAILBOX_BASE_ADDRESS\r
+ }\r
+}\r
+\r
+VOID\r
+WaitForEcLDN9MailboxCmdAck (\r
+ VOID\r
+ )\r
+{\r
+ UINT8 Msgdata;\r
+ UINT16 Delaytime;\r
+ Msgdata = 0;\r
+ for (Delaytime = 0; Delaytime <= 500; Delaytime++) {\r
+ ReadECmsg (MSG_REG0, AccWidthUint8, &Msgdata);\r
+ if ( Msgdata == 0xfa) {\r
+ break;\r
+ }\r
+ SbStall (1000); // Wait for 1ms\r
+ }\r
+}\r
+\r
+\r
--- /dev/null
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+\r
+\r
+#include "SBPLATFORM.h"\r
+#include "ECfan.h"\r
+/**\r
+ * Table for Function Number\r
+ *\r
+ *\r
+ *\r
+ *\r
+ */\r
+UINT8 FunctionNumber[] =\r
+{\r
+ Fun_81,\r
+ Fun_83,\r
+ Fun_85,\r
+ Fun_89,\r
+};\r
+\r
+/**\r
+ * Table for Max Thermal Zone\r
+ *\r
+ *\r
+ *\r
+ *\r
+ */\r
+UINT8 MaxZone[] =\r
+{\r
+ 4,\r
+ 4,\r
+ 4,\r
+ 4,\r
+};\r
+\r
+/**\r
+ * Table for Max Register\r
+ *\r
+ *\r
+ *\r
+ *\r
+ */\r
+UINT8 MaxRegister[] =\r
+{\r
+ MSG_REG9,\r
+ MSG_REGB,\r
+ MSG_REG9,\r
+ MSG_REGA,\r
+};\r
+\r
+/*-------------------------------------------------------------------------------\r
+;Procedure: IsZoneFuncEnable\r
+;\r
+;Description: This routine will check every zone support function with BitMap from user define\r
+;\r
+;\r
+;Exit: None\r
+;\r
+;Modified: None\r
+;\r
+;-----------------------------------------------------------------------------\r
+*/\r
+BOOLEAN\r
+IsZoneFuncEnable (\r
+ UINT16 Flag,\r
+ UINT8 func,\r
+ UINT8 Zone\r
+)\r
+{\r
+ return (BOOLEAN)(((Flag >> (func *4)) & 0xF) & ((UINT8 )1 << Zone));\r
+}\r
+\r
+/*-------------------------------------------------------------------------------\r
+;Procedure: sbECfancontrolservice\r
+;\r
+;Description: This routine service EC fan policy\r
+;\r
+;\r
+;Exit: None\r
+;\r
+;Modified: None\r
+;\r
+;-----------------------------------------------------------------------------\r
+*/\r
+VOID\r
+sbECfancontrolservice (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT8 ZoneNum;\r
+ UINT8 FunNum;\r
+ UINT8 RegNum;\r
+ UINT8 * CurPoint;\r
+ UINT8 FunIndex;\r
+ BOOLEAN IsSendEcMsg;\r
+\r
+ CurPoint = &pConfig->Pecstruct.MSGFun81zone0MSGREG0 + MaxZone[0] * (MaxRegister[0] - MSG_REG0 + 1);\r
+ for ( FunIndex = 1; FunIndex <= 3; FunIndex++ ) {\r
+ FunNum = FunctionNumber[FunIndex];\r
+ for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) {\r
+ IsSendEcMsg = IsZoneFuncEnable (pConfig->Pecstruct.IMCFUNSupportBitMap, FunIndex, ZoneNum);\r
+ for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) {\r
+ if (IsSendEcMsg) {\r
+ WriteECmsg (RegNum, AccWidthUint8, CurPoint); //\r
+ }\r
+ CurPoint += 1;\r
+ }\r
+ if (IsSendEcMsg) {\r
+ WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &FunNum); // function number\r
+ WaitForEcLDN9MailboxCmdAck ();\r
+ }\r
+ }\r
+ }\r
+ CurPoint = &pConfig->Pecstruct.MSGFun81zone0MSGREG0;\r
+ for ( FunIndex = 0; FunIndex <= 0; FunIndex++ ) {\r
+ FunNum = FunctionNumber[FunIndex];\r
+ for ( ZoneNum = 0; ZoneNum < MaxZone[FunIndex]; ZoneNum++ ) {\r
+ IsSendEcMsg = IsZoneFuncEnable (pConfig->Pecstruct.IMCFUNSupportBitMap, FunIndex, ZoneNum);\r
+ for ( RegNum = MSG_REG0; RegNum <= MaxRegister[FunIndex]; RegNum++ ) {\r
+ if (IsSendEcMsg) {\r
+ WriteECmsg (RegNum, AccWidthUint8, CurPoint); //\r
+ }\r
+ CurPoint += 1;\r
+ }\r
+ if (IsSendEcMsg) {\r
+ WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &FunNum); // function number\r
+ WaitForEcLDN9MailboxCmdAck ();\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/*-------------------------------------------------------------------------------\r
+;Procedure: SBIMCFanInitializeS3\r
+;\r
+;Description: This routine initialize IMC fan when S3 resume\r
+;\r
+;\r
+;Exit: None\r
+;\r
+;Modified: None\r
+;\r
+;-----------------------------------------------------------------------------\r
+*/\r
+VOID\r
+SBIMCFanInitializeS3 (VOID)\r
+{\r
+ UINT8 dbPortStatus,Value80,Value82,Value83,Value84;\r
+\r
+ getChipSysMode (&dbPortStatus);\r
+ if ((dbPortStatus & ChipSysEcEnable) != 0) {\r
+ Value80 = 0x98;\r
+ Value82 = 0x00;\r
+ Value83 = 0x02;\r
+ Value84 = 0x00;\r
+\r
+ // Clear MSG_REG0 to receive acknowledge byte\r
+ WriteECmsg (MSG_REG0, AccWidthUint8, &Value82);\r
+ \r
+ // Set MSG_REG1\r
+ // 0x02 - Notify IMC that the system is waken from any sleep state\r
+ WriteECmsg (MSG_REG1, AccWidthUint8, &Value83);\r
+ \r
+ // Set timeout counter value to 00 which disables watchdog timer\r
+ WriteECmsg (MSG_REG2, AccWidthUint8, &Value84);\r
+ \r
+ // Write mailbox function number to kick off the command\r
+ // 0x98 - IMC System Sleep and Wake Services \r
+ WriteECmsg (MSG_SYS_TO_IMC, AccWidthUint8, &Value80);\r
+ \r
+ // Read acknowledge byte to make sure function is executed properly\r
+ WaitForEcLDN9MailboxCmdAck ();\r
+ }\r
+}\r
--- /dev/null
+/**\r
+ * @file\r
+ *\r
+ * Config Southbridge GEC controller\r
+ *\r
+ * Init GEC features.\r
+ *\r
+ * @xrefitem bom "File Content Label" "Release Content"\r
+ * @e project: CIMx-SB\r
+ * @e sub-project:\r
+ * @e \$Revision:$ @e \$Date:$\r
+ *\r
+ */\r
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+\r
+#include "SBPLATFORM.h"\r
+\r
+/**\r
+ * gecInitBeforePciEnum - Config GEC controller before PCI emulation\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+gecInitBeforePciEnum (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT8 cimSBGecDebugBus;\r
+ UINT8 cimSBGecPwr;\r
+\r
+ cimSBGecDebugBus = (UINT8) pConfig->SBGecDebugBus;\r
+ cimSBGecPwr = (UINT8) pConfig->SBGecPwr;\r
+#if SB_CIMx_PARAMETER == 0\r
+ cimSBGecDebugBus = cimSBGecDebugBusDefault;\r
+ cimSBGecPwr = cimSBGecPwrDefault;\r
+#endif\r
+ if ( pConfig->GecConfig == 0) {\r
+ // GEC Enabled\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT0, 0x00);\r
+ RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GEVENT_REG11, AccWidthUint8, 0, 0x00);\r
+ RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GEVENT_REG21, AccWidthUint8, 0, 0x01);\r
+ RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG166, AccWidthUint8, 0, 0x01);\r
+ //RWMEM (ACPI_MMIO_BASE + IOMUX_BASE + SB_GPIO_REG181, AccWidthUint8, 0, 0x01);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF8, AccWidthUint8, ~(BIT5 + BIT6), (UINT8) ((cimSBGecPwr) << 5));\r
+ } else {\r
+ // GEC Disabled\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT0, BIT0);\r
+ return; //return if GEC controller is disabled.\r
+ }\r
+ if ( cimSBGecDebugBus == 1) {\r
+ // GEC Debug Bus Enabled\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT3, BIT3);\r
+ } else {\r
+ // GEC Debug Bus Disabled\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF6, AccWidthUint8, ~BIT3, 0x00);\r
+ }\r
+}\r
+\r
+/**\r
+ * gecInitAfterPciEnum - Config GEC controller after PCI emulation\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+gecInitAfterPciEnum (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ VOID* GecRomAddress;\r
+ VOID* GecShadowRomAddress;\r
+ UINT32 ddTemp;\r
+ UINT8 dbVar;\r
+ UINT8 dbTemp;\r
+ if ( pConfig->GecConfig == 0) {\r
+ dbVar = 0;\r
+ ReadPCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbVar);\r
+ dbTemp = 0x07;\r
+ WritePCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbTemp);\r
+ if ( !pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr == NULL ) {\r
+ GecRomAddress = pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr;\r
+ GecShadowRomAddress = (VOID*) (UINTN) pConfig->BuildParameters.GecShadowRomBase;\r
+ AmdSbCopyMem (GecShadowRomAddress, GecRomAddress, 0x100);\r
+ ReadPCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG10, AccWidthUint32, &ddTemp);\r
+ ddTemp = ddTemp & 0xFFFFFFF0;\r
+ RWMEM (ddTemp + 0x6804, AccWidthUint32, 0, BIT0 + BIT29);\r
+ }\r
+ WritePCI ((GEC_BUS_DEV_FUN << 16) + SB_GEC_REG04, AccWidthUint8, &dbVar);\r
+ }\r
+}\r
+\r
+/**\r
+ * gecInitLatePost - Prepare GEC controller to boot to OS.\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+gecInitLatePost (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ if ( !pConfig->GecConfig == 0) {\r
+ return; //return if GEC controller is disabled.\r
+ }\r
+}\r
+\r
+\r
--- /dev/null
+\r
+/**\r
+ * @file\r
+ *\r
+ * Config Southbridge GPP controller\r
+ *\r
+ * Init GPP features.\r
+ *\r
+ * @xrefitem bom "File Content Label" "Release Content"\r
+ * @e project: CIMx-SB\r
+ * @e sub-project\r
+ * @e \$Revision:$ @e \$Date:$\r
+ *\r
+ */\r
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+ \r
+#include "SBPLATFORM.h"\r
+\r
+/**\r
+ * PCIE_CAP_ID - PCIe Cap ID\r
+ *\r
+ */\r
+#define PCIE_CAP_ID 0x10\r
+\r
+//\r
+// Declaration of local functions\r
+//\r
+\r
+/**\r
+ * PreInitGppLink - Enable GPP link training.\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+ VOID PreInitGppLink (IN AMDSBCFG* pConfig);\r
+ UINT8 CheckGppLinkStatus (IN AMDSBCFG* pConfig);\r
+ VOID AfterGppLinkInit (IN AMDSBCFG* pConfig);\r
+ VOID sbGppForceGen2 (IN UINT32 portId );\r
+ VOID sbGppForceGen1 (IN UINT32 portId );\r
+ VOID sbGppDisableUnusedPadMap (IN AMDSBCFG* pConfig );\r
+ VOID sbGppSetAspm (IN UINT32 pciAddress, IN UINT8 LxState);\r
+ UINT8 sbFindPciCap (IN UINT32 pciAddress, IN UINT8 targetCapId);\r
+\r
+//\r
+// Declaration of external functions\r
+//\r
+\r
+//\r
+//-----------------------------------------------------------------------------------\r
+// Early SB800 GPP initialization sequence:\r
+//\r
+// 1) Set port enable bit fields by current GPP link configuration mode\r
+// 2) Deassert GPP reset and pull EP out of reset - Clear GPP_RESET (abcfg:0xC0[8] = 0)\r
+// 3) Loop polling for the link status of all ports\r
+// 4) Misc operations after link training:\r
+// - (optional) Detect GFX device\r
+// - Hide empty GPP configuration spaces (Disable empty GPP ports)\r
+// - (optional) Power down unused GPP ports\r
+// - (optional) Configure PCIE_P2P_Int_Map (abcfg:0xC4[7:0])\r
+// 5) GPP init completed\r
+//\r
+//\r
+// *) Gen2 vs Gen1\r
+// Gen2 mode Gen1 mode\r
+// ---------------------------------------------------------------\r
+// STRAP_PHY_PLL_CLKF[6:0] 7'h32 7'h19\r
+// STRAP_BIF_GEN2_EN 1 0\r
+//\r
+// PCIE_PHY_PLL clock locks @ 5GHz\r
+//\r
+//\r
+\r
+/**\r
+ * GPP early programming and link training. On exit all populated EPs should be fully operational.\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+sbPcieGppEarlyInit (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT8 TogglePort;\r
+ UINT8 portNum;\r
+ UINT32 reg32Value;\r
+ UINT8 retryCount;\r
+ UINT8 cimGppMemWrImprove;\r
+ UINT8 cimGppLaneReversal;\r
+ UINT8 cimAlinkPhyPllPowerDown;\r
+\r
+ cimGppMemWrImprove = pConfig->GppMemWrImprove;\r
+ cimGppLaneReversal = (UINT8) pConfig->GppLaneReversal;\r
+ cimAlinkPhyPllPowerDown = (UINT8) pConfig->AlinkPhyPllPowerDown;\r
+#if SB_CIMx_PARAMETER == 0\r
+ cimGppMemWrImprove = cimGppMemWrImproveDefault;\r
+ cimGppLaneReversal = cimGppLaneReversalDefault;\r
+ cimAlinkPhyPllPowerDown = cimAlinkPhyPllPowerDownDefault;\r
+#endif\r
+\r
+//\r
+// Configure NB-SB link PCIE PHY PLL power down for L1\r
+//\r
+ if ( cimAlinkPhyPllPowerDown == TRUE ) {\r
+ UINT32 abValue;\r
+ // Set PCIE_P_CNTL in Alink PCIEIND space\r
+ writeAlink (SB_AX_INDXC_REG30 | (UINT32) (AXINDC << 29), 0x40);\r
+ abValue = readAlink (SB_AX_DATAC_REG34 | (UINT32) (AXINDC << 29));\r
+ abValue |= BIT12 + BIT3 + BIT0;\r
+ abValue &= ~(BIT9 + BIT4);\r
+ writeAlink (SB_AX_DATAC_REG34 | (UINT32) (AXINDC << 29), abValue);\r
+ rwAlink (SB_AX_INDXC_REG02 | (UINT32) (AXINDC << 29), ~BIT8, (BIT8));\r
+ }\r
+\r
+//\r
+// Set ABCFG 0x031C[0] = 1 enable the lane reversal support.\r
+//\r
+ reg32Value = readAlink (SB_ABCFG_REG31C | (UINT32) (ABCFG << 29));\r
+ if ( cimGppLaneReversal ) {\r
+ writeAlink (SB_ABCFG_REG31C | (UINT32) (ABCFG << 29), reg32Value | BIT0);\r
+ } else {\r
+ writeAlink (SB_ABCFG_REG31C | (UINT32) (ABCFG << 29), reg32Value | 0x00);\r
+ }\r
+//\r
+// Set abcfg:0x90[20] = 1 to enable GPP bridge multi-function\r
+//\r
+ reg32Value = readAlink (SB_ABCFG_REG90 | (UINT32) (ABCFG << 29));\r
+ writeAlink (SB_ABCFG_REG90 | (UINT32) (ABCFG << 29), reg32Value | BIT20);\r
+\r
+\r
+//\r
+// Initialize and configure GPP\r
+//\r
+ if (pConfig->GppFunctionEnable) {\r
+ // PreInit - Enable GPP link training\r
+ PreInitGppLink (pConfig);\r
+\r
+//\r
+// GPP Upstream Memory Write Arbitration Enhancement ABCFG 0x54[26] = 1\r
+// GPP Memory Write Max Payload Improvement RCINDC_Reg 0x10[12:10] = 0x4\r
+//\r
+ if ( cimGppMemWrImprove == TRUE ) {\r
+ rwAlink (SB_ABCFG_REG54 | (UINT32) (ABCFG << 29), ~BIT26, (BIT26));\r
+ rwAlink (SB_RCINDXC_REG10 | (UINT32) (RCINDXC << 29), ~(BIT12 + BIT11 + BIT10), (BIT12));\r
+ }\r
+\r
+ if ( pConfig->S3Resume ) {\r
+ for ( portNum = 0; portNum < MAX_GPP_PORTS; portNum++ ) {\r
+ reg32Value = readAlink ((SB_ABCFG_REG340 + portNum * 4) | (UINT32) (ABCFG << 29));\r
+ writeAlink ((SB_ABCFG_REG340 + portNum * 4) | (UINT32) (ABCFG << 29), reg32Value & ~BIT21);\r
+ }\r
+ }\r
+ //\r
+ // a) Loop polling regA5 -> LcState (timeout ~100ms);\r
+ // b) if (LcState[5:0] == 0x10), training successful, go to g);\r
+ // c) if any of (LcState[13:8], [21:16], [29:24]) == 0x29 or 0x2A:\r
+ // d) Clear De-emphasis bit for relevant ports;\r
+ // e) Toggle GPP reset signal (via OEM callback);\r
+ // f) go back to a);\r
+ // g) exit;\r
+ //\r
+ for (retryCount = 0; retryCount < MAX_GPP_RESETS; retryCount++) {\r
+ // Polling each GPP port for link status\r
+ TogglePort = CheckGppLinkStatus (pConfig);\r
+\r
+ if (TogglePort == 0) {\r
+ break;\r
+ } else {\r
+ // Check failure port and clear STRAP_BIF_DE_EMPHASIS_SEL_x_GPP bit (abcfg:0x34[0, 4, 8, C][21]=0)\r
+ for ( portNum = 0; portNum < MAX_GPP_PORTS; portNum++ ) {\r
+ if (TogglePort & (1 << portNum)) {\r
+ reg32Value = readAlink ((SB_ABCFG_REG340 + portNum * 4) | (UINT32) (ABCFG << 29));\r
+ writeAlink ((SB_ABCFG_REG340 + portNum * 4) | (UINT32) (ABCFG << 29), reg32Value & ~BIT21);\r
+ }\r
+ sbGppForceGen1 (portNum);\r
+ }\r
+\r
+ // Toggle GPP reset (Note this affects all SB800 GPP ports)\r
+ CallBackToOEM (CB_SBGPP_RESET_ASSERT, (UINT32)TogglePort, pConfig);\r
+ SbStall (500);\r
+ CallBackToOEM (CB_SBGPP_RESET_DEASSERT, (UINT32)TogglePort, pConfig);\r
+ }\r
+ };\r
+\r
+ // Misc operations after link training\r
+ AfterGppLinkInit (pConfig);\r
+ } else {\r
+\r
+// RPR 5.11 Power Saving With GPP Disable\r
+// ABCFG 0xC0[8] = 0x0\r
+// ABCFG 0xC0[15:12] = 0xF\r
+// Enable "Power Saving Feature for A-Link Express Lanes"\r
+// Enable "Power Saving Feature for GPP Lanes"\r
+// ABCFG 0x90[19] = 1\r
+// ABCFG 0x90[6] = 1\r
+// RCINDC_Reg 0x65 [27:0] = 0xFFFFFFF\r
+// ABCFG 0xC0[7:4] = 0x0\r
+\r
+ rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), ~BIT8, (BIT4 + BIT5 + BIT6 + BIT7));\r
+ rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, (BIT12 + BIT13 + BIT14 + BIT15));\r
+ rwAlink (SB_AX_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12));\r
+ rwAlink (RC_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12));\r
+ rwAlink ((SB_ABCFG_REG90 | (UINT32) (ABCFG << 29)), 0xFFFFFFFF, (BIT6 + BIT19));\r
+ rwAlink (RC_INDXC_REG65, 0xFFFFFFFF, 0x0fffffff);\r
+ rwAlink ((SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29)), ~(BIT4 + BIT5 + BIT6 + BIT7), 0);\r
+ }\r
+ sbGppDisableUnusedPadMap ( pConfig );\r
+}\r
+\r
+/**\r
+ * PreInitGppLink - Enable GPP link training.\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+PreInitGppLink (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT8 portMask[5] = {0x01,\r
+ 0x00,\r
+ 0x03,\r
+ 0x07,\r
+ 0x0F\r
+ };\r
+ UINT8 cfgMode;\r
+ UINT8 portId;\r
+ UINT32 reg32Value;\r
+ UINT16 tmp16Value;\r
+\r
+// PCIE_GPP_ENABLE (abcfg:0xC0):\r
+//\r
+// GPP_LINK_CONFIG ([3:0]) PortA PortB PortC PortD Description\r
+// ----------------------------------------------------------------------------------\r
+// 0000 0-3 x4 Config\r
+// 0001 N/A\r
+// 0010 0-1 2-3 0 2:2 Config\r
+// 0011 0-1 2 3 2:1:1 Config\r
+// 0100 0 1 2 3 1:1:1:1 Config\r
+//\r
+// For A12 and above:\r
+// ABCFG:0xC0[12] - Port A hold training (default 1)\r
+// ABCFG:0xC0[13] - Port B hold training (default 1)\r
+// ABCFG:0xC0[14] - Port C hold training (default 1)\r
+// ABCFG:0xC0[15] - Port D hold training (default 1)\r
+//\r
+//\r
+ //\r
+ // Set port enable bit fields based on current GPP link configuration mode\r
+ //\r
+ cfgMode = (UINT8) pConfig->GppLinkConfig;\r
+ if ( cfgMode > GPP_CFGMODE_X1111 || cfgMode == 1 ) {\r
+ cfgMode = GPP_CFGMODE_X4000;\r
+ pConfig->GppLinkConfig = GPP_CFGMODE_X4000;\r
+ }\r
+ reg32Value = (UINT32) portMask[cfgMode];\r
+\r
+ // Mask out non-applicable ports according to the target link configuration mode\r
+ for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {\r
+ pConfig->PORTCONFIG[portId].PortCfg.PortPresent &= (reg32Value >> portId) & BIT0;\r
+ }\r
+\r
+ //\r
+ // Deassert GPP reset and pull EP out of reset - Clear GPP_RESET (abcfg:0xC0[8] = 0)\r
+ //\r
+ tmp16Value = (UINT16) (~reg32Value << 12);\r
+ reg32Value = (UINT32) (tmp16Value + (reg32Value << 4) + cfgMode);\r
+ writeAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), reg32Value);\r
+\r
+ reg32Value = readAlink (0xC0 | (UINT32) (RCINDXC << 29));\r
+ writeAlink (0xC0 | (UINT32) (RCINDXC << 29), reg32Value | 0x400); // Set STRAP_F0_MSI_EN\r
+\r
+ // A-Link L1 Entry Delay Shortening\r
+ // AXINDP_Reg 0xA0[7:4] = 0x3\r
+ rwAlink (SB_AX_INDXP_REGA0, 0xFFFFFF0F, 0x30);\r
+ rwAlink (SB_AX_INDXP_REGB1, 0xFFFFFFFF, BIT19);\r
+ rwAlink (SB_AX_INDXP_REGB1, 0xFFFFFFFF, BIT28);\r
+\r
+ // RPR5.22 GPP L1 Entry Delay Shortening\r
+ // RCINDP_Reg 0xA0[7:4] = 0x1 Enter L1 sooner after ACK'ing PM request.\r
+ // This is done to reduce number of NAK received with L1 enabled.\r
+ for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {\r
+ rwAlink (SB_RCINDXP_REGA0 | portId << 24, 0xFFFFFF0F, 0x10);\r
+ }\r
+}\r
+\r
+/**\r
+ * CheckGppLinkStatus - loop polling the link status for each GPP port\r
+ *\r
+ *\r
+ * Return: ToggleStatus[3:0] = Port bitmap for those need to clear De-emphasis\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+UINT8\r
+CheckGppLinkStatus (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT32 retryCounter;\r
+ UINT32 portId;\r
+ UINT32 abIndex;\r
+ UINT32 Data32;\r
+ UINT8 portScanMap;\r
+ UINT8 portScanMap2;\r
+ UINT8 ToggleStatus;\r
+ UINT16 i;\r
+ SBGPPPORTCONFIG *portCfg;\r
+\r
+\r
+ portScanMap = 0;\r
+ retryCounter = MAX_TRAINING_RETRY;\r
+ ToggleStatus = 0;\r
+\r
+ // Obtain a list of ports to be checked\r
+ for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {\r
+ portCfg = &pConfig->PORTCONFIG[portId].PortCfg;\r
+ if ( portCfg->PortPresent == TRUE && portCfg->PortDetected == FALSE ) {\r
+ portScanMap |= 1 << portId;\r
+ }\r
+ }\r
+ portScanMap2 = portScanMap;\r
+\r
+ //\r
+ // After training is enabled, Check LCSTATE for each port, if LCSTATE<= 4, then keep\r
+ // polling for up to 40ms. If LCSTATE still <= 4, then assume the port to be empty.\r
+ //\r
+ i = 400;\r
+ while ( --i && portScanMap2) {\r
+ for (portId = 0; portId < MAX_GPP_PORTS; portId++) {\r
+ portCfg = &pConfig->PORTCONFIG[portId].PortCfg;\r
+ if (((portCfg->PortHotPlug == FALSE) || ((portCfg->PortHotPlug == TRUE) && (pConfig->S3Resume == FALSE)) ) && (portScanMap2 & (1 << portId))) {\r
+ //\r
+ // Get port link state (reading LC_CURRENT_STATE of PCIEIND_P)\r
+ //\r
+ abIndex = SB_RCINDXP_REGA5 | (UINT32) (RCINDXP << 29) | (portId << 24);\r
+ Data32 = readAlink (abIndex) & 0x3F;\r
+ if ((UINT8) (Data32) > 4) {\r
+ portScanMap2 &= ~(1 << portId); // This port is not empty\r
+ break;\r
+ }\r
+ SbStall (100); // Delay 100us\r
+ }\r
+ }\r
+ }\r
+ portScanMap &= ~portScanMap2; // Mark remaining ports as empty\r
+\r
+\r
+ while ( --retryCounter && portScanMap ) {\r
+ for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {\r
+ portCfg = &pConfig->PORTCONFIG[portId].PortCfg;\r
+ if (( portCfg->PortHotPlug == TRUE ) && ( pConfig->S3Resume )) {\r
+ continue;\r
+ }\r
+ if ( portCfg->PortPresent == TRUE && portCfg->PortDetected == FALSE ) {\r
+ //\r
+ // Get port link state (reading LC_CURRENT_STATE of PCIEIND_P)\r
+ //\r
+ SbStall (1000); // Delay 400us\r
+ abIndex = SB_RCINDXP_REGA5 | (UINT32) (RCINDXP << 29) | (portId << 24);\r
+ Data32 = readAlink (abIndex) & 0x3F3F3F3F;\r
+\r
+ if ( (UINT8) (Data32) == 0x10 ) {\r
+ portCfg->PortDetected = TRUE;\r
+ portScanMap &= ~(1 << portId);\r
+ } else {\r
+ for (i = 0; i < 4; i++) {\r
+ //\r
+ // Compliance mode (0x7), downgrade from Gen2 to Gen1 (*A12)\r
+ //\r
+ if ((UINT8) (Data32) == 0x29 || (UINT8) (Data32) == 0x2A || (UINT8) (Data32) == 0x7 ) {\r
+ ToggleStatus |= (1 << portId); // A11 only: need to toggle GPP reset\r
+ portScanMap &= ~(1 << portId);\r
+ }\r
+ Data32 >>= 8;\r
+ }\r
+ }\r
+ }\r
+ }\r
+ }\r
+ return ToggleStatus;\r
+}\r
+\r
+\r
+/**\r
+ * AfterGppLinkInit\r
+ * - Search for display device behind each GPP port\r
+ * - If the port is empty AND not hotplug-capable:\r
+ * * Turn off link training\r
+ * * (optional) Power down the port\r
+ * * Hide the configuration space (Turn off the port)\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+AfterGppLinkInit (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT32 portId;\r
+ SBGPPPORTCONFIG *portCfg;\r
+ UINT32 regBusNumber;\r
+ UINT32 abValue;\r
+ UINT32 abIndex;\r
+ UINT32 i;\r
+ UINT32 Data32;\r
+ UINT8 bValue;\r
+ UINT8 cimGppGen2;\r
+\r
+ cimGppGen2 = pConfig->GppGen2;\r
+#if SB_CIMx_PARAMETER == 0\r
+ cimGppGen2 = cimGppGen2Default;\r
+#endif\r
+\r
+ bValue = GPP_EFUSE_LOCATION;\r
+ getEfuseStatus (&bValue);\r
+ if ( (bValue & GPP_GEN2_EFUSE_BIT) != 0 ) {\r
+ cimGppGen2 = FALSE;\r
+ } else {\r
+ pConfig->CoreGen2Enable = TRUE; // Output for platform use\r
+ }\r
+\r
+//GPP Gen2 Speed Change\r
+// if ((GPP Gen2 == enabled) and (RCINDP_Reg 0xA4[0] == 0x1)) {\r
+// PCIe_Cfg 0x88[3:0] = 0x2\r
+// RCINDP_Reg 0xA2[13] = 0x0\r
+// RCINDP_Reg 0xC0[15] = 0x0\r
+// RCINDP_Reg 0xA4[29] = 0x1\r
+// } else {\r
+// PCIe_Cfg 0x88[3:0] = 0x1\r
+// RCINDP_Reg 0xA4[0] = 0x0\r
+// RCINDP_Reg 0xA2[13] = 0x1\r
+// RCINDP_Reg 0xC0[15] = 0x0\r
+// RCINDP_Reg 0xA4[29] = 0x1\r
+// }\r
+ for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {\r
+ portCfg = &pConfig->PORTCONFIG[portId].PortCfg;\r
+ abValue = readAlink (SB_RCINDXP_REGA4 | portId << 24) & BIT0;\r
+ if (( cimGppGen2 == TRUE ) && (abValue == BIT0) && (portCfg->PortDetected == TRUE)) {\r
+ portCfg->PortIsGen2 = TRUE; // Output for platform use\r
+ sbGppForceGen2 (portId);\r
+ //_asm {jmp $};\r
+ SbStall (400); // Delay 400us\r
+ i = 500;\r
+ Data32 = 0;\r
+ while ( --i ) {\r
+ abIndex = SB_RCINDXP_REGA5 | (UINT32) (RCINDXP << 29) | (portId << 24);\r
+ Data32 = readAlink (abIndex) & 0x3F;\r
+ if ((UINT8) (Data32) == 0x10) {\r
+ break;\r
+ }\r
+ SbStall (400); // Delay 100us\r
+ }\r
+ if (!( (UINT8) (Data32) == 0x10 )) {\r
+ if (pConfig->GppCompliance == FALSE) {\r
+ portCfg->PortIsGen2 = FALSE; // Revert to default; output for platform use\r
+ sbGppForceGen1 (portId);\r
+ }\r
+ }\r
+ } else {\r
+ if (pConfig->GppCompliance == FALSE) {\r
+ sbGppForceGen1 (portId);\r
+ }\r
+ }\r
+//RPR 5.9 Link Bandwidth Notification Capability Enable\r
+//RCINDC 0xC1[0] = 1\r
+//PCIe Cfg 0x68[10] = 0\r
+//PCIe Cfg 0x68[11] = 0\r
+\r
+ rwAlink (SB_RCINDXC_REGC1, 0xFFFFFFFF, BIT0);\r
+ RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x68), AccWidthUint16, ~(BIT10 + BIT11), 0);\r
+ }\r
+\r
+// Status = AGESA_SUCCESS;\r
+ pConfig->GppFoundGfxDev = 0;\r
+ abValue = readAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29));\r
+\r
+ for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {\r
+ portCfg = &pConfig->PORTCONFIG[portId].PortCfg;\r
+ // Check if there is GFX device behind each GPP port\r
+ if ( portCfg->PortDetected == TRUE ) {\r
+ regBusNumber = (SBTEMP_BUS << 16) + (SBTEMP_BUS << 8);\r
+ WritePCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x18), AccWidthUint32, ®BusNumber);\r
+ // *** Stall ();\r
+ ReadPCI (PCI_ADDRESS (SBTEMP_BUS, 0, 0, 0x0B), AccWidthUint8, &bValue);\r
+ if ( bValue == 3 ) {\r
+ pConfig->GppFoundGfxDev |= (1 << portId);\r
+ }\r
+ regBusNumber = 0;\r
+ WritePCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x18), AccWidthUint32, ®BusNumber);\r
+ }\r
+\r
+ // Mask off non-applicable ports\r
+ else if ( portCfg->PortPresent == FALSE ) {\r
+ abValue &= ~(1 << (portId + 4));\r
+ }\r
+ // Mask off empty port if the port is not hotplug-capable\r
+ else if ( portCfg->PortHotPlug == FALSE ) {\r
+ abValue &= ~(1 << (portId + 4));\r
+ }\r
+ // Clear STRAP_BIF_DE_EMPHASIS_SEL_x_GPP bit (abcfg:0x34[0, 4, 8, C][21]=0) to make hotplug working\r
+ if ( portCfg->PortHotPlug == TRUE ) {\r
+ rwAlink ((SB_ABCFG_REG340 + portId * 4) | (UINT32) (ABCFG << 29), ~BIT21, 0);\r
+\r
+// RPR5.12 Hot Plug: PCIe Native Support\r
+// RCINDP_Reg 0x10[3] = 0x1\r
+// PCIe_Cfg 0x5A[8] = 0x1\r
+// PCIe_Cfg 0x6C[6] = 0x1\r
+// RCINDP_Reg 0x20[19] = 0x0\r
+\r
+ rwAlink ((SB_RCINDXP_REG10 | (UINT32) (RCINDXP << 29) | (portId << 24)), 0xFFFFFFFF, BIT3);\r
+ RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x5b), AccWidthUint8, 0xff, BIT0);\r
+ RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x6c), AccWidthUint8, 0xff, BIT6);\r
+ rwAlink ((SB_RCINDXP_REG20 | (UINT32) (RCINDXP << 29) | (portId << 24)), ~BIT19, 0);\r
+ }\r
+ }\r
+ if ( pConfig->GppUnhidePorts == FALSE ) {\r
+ if ((abValue & 0xF0) == 0) {\r
+ abValue = BIT8; // if all ports are empty set GPP_RESET\r
+ } else if ((abValue & 0xE0) != 0 && (abValue & 0x10) == 0) {\r
+ abValue |= BIT4; // PortA should always be visible whenever other ports are exist\r
+ }\r
+\r
+ // Update GPP_Portx_Enable (abcfg:0xC0[7:5])\r
+ writeAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), abValue);\r
+ }\r
+\r
+ //\r
+ // Common initialization for open GPP ports\r
+ //\r
+ for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {\r
+ ReadPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x80), AccWidthUint8, &bValue);\r
+ if (bValue != 0xff) {\r
+ // Set pciCfg:PCIE_DEVICE_CNTL2[3:0] = 4'h6 (0x80[3:0])\r
+ bValue &= 0xf0;\r
+ bValue |= 0x06;\r
+ WritePCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x80), AccWidthUint8, &bValue);\r
+\r
+ // Set PCIEIND_P:PCIE_RX_CNTL[RX_RCB_CPL_TIMEOUT_MODE] (0x70:[19]) = 1\r
+ abIndex = SB_RCINDXP_REG70 | (UINT32) (RCINDXP << 29) | (portId << 24);\r
+ abValue = readAlink (abIndex) | BIT19;\r
+ writeAlink (abIndex, abValue);\r
+\r
+ // Set PCIEIND_P:PCIE_TX_CNTL[TX_FLUSH_TLP_DIS] (0x20:[19]) = 0\r
+ abIndex = SB_RCINDXP_REG20 | (UINT32) (RCINDXP << 29) | (portId << 24);\r
+ abValue = readAlink (abIndex) & ~BIT19;\r
+ writeAlink (abIndex, abValue);\r
+\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ * sbPcieGppLateInit - Late PCIE initialization for SB800 GPP component\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+sbPcieGppLateInit (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT32 reg32Value;\r
+ UINT8 portId;\r
+ UINT8 busNum;\r
+ UINT8 aspmValue;\r
+ UINT8 reg8Value;\r
+ UINT8 cimGppPhyPllPowerDown;\r
+\r
+ reg8Value = 0x01;\r
+//\r
+// Configure ASPM\r
+//\r
+// writeAlink (0xC0 | (UINT32) (RCINDXC << 29), 0x400); // Set STRAP_F0_MSI_EN\r
+ aspmValue = (UINT8)pConfig->GppPortAspm;\r
+ cimGppPhyPllPowerDown = (UINT8) pConfig->GppPhyPllPowerDown;\r
+#if SB_CIMx_PARAMETER == 0\r
+ aspmValue = cimGppPortAspmDefault;\r
+ cimGppPhyPllPowerDown = cimGppPhyPllPowerDownDefault;\r
+#endif\r
+\r
+ for ( portId = 0; portId < MAX_GPP_PORTS; portId++ ) {\r
+ // write pci_reg3d with 0x01 to fix yellow mark for GPP bridge under Vista\r
+ // when native PCIE is enabled but MSI is not available\r
+ // SB02029: SB800 BIF/GPP allowing strap STRAP_BIF_INTERRUPT_PIN_SB controlled by AB reg\r
+ WritePCI (PCI_ADDRESS (0, 21, portId, 0x3d), AccWidthUint8, ®8Value);\r
+ ReadPCI (PCI_ADDRESS (0, 21, portId, 0x19), AccWidthUint8, &busNum);\r
+ if (busNum != 0xFF) {\r
+ ReadPCI (PCI_ADDRESS (busNum, 0, 0, 0x00), AccWidthUint32, ®32Value);\r
+ if (reg32Value != 0xffffffff) {\r
+ // Set ASPM on EP side\r
+ sbGppSetAspm (PCI_ADDRESS (busNum, 0, 0, 0), aspmValue & 0x3);\r
+ // Set ASPM on port side\r
+ sbGppSetAspm (PCI_ADDRESS (0, 21, portId, 0), aspmValue & 0x3);\r
+ }\r
+ }\r
+ aspmValue = aspmValue >> 2;\r
+ }\r
+\r
+//\r
+// Configure Lock HWInit registers\r
+//\r
+ reg32Value = readAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29));\r
+ if (reg32Value & 0xF0) {\r
+ reg32Value = readAlink (SB_RCINDXC_REG10 | (UINT32) (RCINDXC << 29));\r
+ writeAlink (SB_RCINDXC_REG10 | (UINT32) (RCINDXC << 29), reg32Value | BIT0); // Set HWINIT_WR_LOCK\r
+\r
+ if ( cimGppPhyPllPowerDown == TRUE ) {\r
+//\r
+// RPR 5.4 Power Saving Feature for GPP Lanes\r
+//\r
+ UINT32 abValue;\r
+ // Set PCIE_P_CNTL in Alink PCIEIND space\r
+ abValue = readAlink (RC_INDXC_REG40 | (UINT32) (RCINDXC << 29));\r
+ abValue |= BIT12 + BIT3 + BIT0;\r
+ abValue &= ~(BIT9 + BIT4);\r
+ writeAlink (RC_INDXC_REG40 | (UINT32) (RCINDXC << 29), abValue);\r
+ }\r
+ }\r
+\r
+//\r
+// Configure Lock HWInit registers\r
+//\r
+ reg32Value = readAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29));\r
+//\r
+// Disable hidden register decode and serial number capability\r
+//\r
+ reg32Value = readAlink (SB_ABCFG_REG330 | (UINT32) (ABCFG << 29));\r
+ writeAlink (SB_ABCFG_REG330 | (UINT32) (ABCFG << 29), reg32Value & ~(BIT26 + BIT10));\r
+}\r
+\r
+/**\r
+ * sbGppSetAspm - Set SPP ASPM\r
+ *\r
+ *\r
+ * @param[in] pciAddress PCI Address.\r
+ * @param[in] LxState Lane State.\r
+ *\r
+ */\r
+VOID\r
+sbGppSetAspm (\r
+ IN UINT32 pciAddress,\r
+ IN UINT8 LxState\r
+ )\r
+{\r
+ UINT8 pcieCapOffset;\r
+ UINT8 value8;\r
+ UINT8 maxFuncs;\r
+ UINT32 devBDF;\r
+\r
+ maxFuncs = 1;\r
+ ReadPCI (pciAddress + 0x0E, AccWidthUint8, &value8);\r
+\r
+ if (value8 & BIT7) {\r
+ maxFuncs = 8; // multi-function device\r
+ }\r
+ while (maxFuncs != 0) {\r
+ devBDF = pciAddress + (UINT32) ((maxFuncs - 1) << 16);\r
+ pcieCapOffset = sbFindPciCap (devBDF, PCIE_CAP_ID);\r
+ if (pcieCapOffset) {\r
+ // Read link capabilities register (0x0C[11:10] - ASPM support)\r
+ ReadPCI (devBDF + pcieCapOffset + 0x0D, AccWidthUint8, &value8);\r
+ if (value8 & BIT2) {\r
+ value8 = (value8 >> 2) & (BIT1 + BIT0);\r
+ // Set ASPM state in link control register\r
+ RWPCI (devBDF + pcieCapOffset + 0x10, AccWidthUint8, 0xffffffff, LxState & value8);\r
+ }\r
+ }\r
+ maxFuncs--;\r
+ }\r
+}\r
+\r
+/**\r
+ * sbFindPciCap - Find PCI Cap\r
+ *\r
+ *\r
+ * @param[in] pciAddress PCI Address.\r
+ * @param[in] targetCapId Target Cap ID.\r
+ *\r
+ */\r
+UINT8\r
+sbFindPciCap (\r
+ IN UINT32 pciAddress,\r
+ IN UINT8 targetCapId\r
+ )\r
+{\r
+ UINT8 NextCapPtr;\r
+ UINT8 CapId;\r
+\r
+ NextCapPtr = 0x34;\r
+ while (NextCapPtr != 0) {\r
+ ReadPCI (pciAddress + NextCapPtr, AccWidthUint8, &NextCapPtr);\r
+ if (NextCapPtr == 0xff) {\r
+ return 0;\r
+ }\r
+ if (NextCapPtr != 0) {\r
+ ReadPCI (pciAddress + NextCapPtr, AccWidthUint8, &CapId);\r
+ if (CapId == targetCapId) {\r
+ break;\r
+ } else {\r
+ NextCapPtr++;\r
+ }\r
+ }\r
+ }\r
+ return NextCapPtr;\r
+}\r
+\r
+/**\r
+ * sbGppForceGen2 - Set SPP to GENII\r
+ *\r
+ *\r
+ * @param[in] portId\r
+ *\r
+ */\r
+VOID\r
+sbGppForceGen2 (\r
+ IN UINT32 portId\r
+ )\r
+{\r
+ RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x88), AccWidthUint8, 0xf0, 0x02);\r
+ rwAlink (SB_RCINDXP_REGA2 | portId << 24, ~BIT13, 0);\r
+ rwAlink (SB_RCINDXP_REGC0 | portId << 24, ~BIT15, 0);\r
+ rwAlink (SB_RCINDXP_REGA4 | portId << 24, 0xFFFFFFFF, BIT29);\r
+}\r
+\r
+/**\r
+ * sbGppForceGen1 - Set SPP to GENI\r
+ *\r
+ *\r
+ * @param[in] portId\r
+ *\r
+ */\r
+VOID\r
+sbGppForceGen1 (\r
+ IN UINT32 portId\r
+ )\r
+{\r
+ RWPCI (PCI_ADDRESS (0, GPP_DEV_NUM, portId, 0x88), AccWidthUint8, 0xf0, 0x01);\r
+ rwAlink (SB_RCINDXP_REGA4 | portId << 24, ~BIT0, 0);\r
+ rwAlink (SB_RCINDXP_REGA2 | portId << 24, 0xFFFFFFFF, BIT13);\r
+ rwAlink (SB_RCINDXP_REGC0 | portId << 24, ~BIT15, 0);\r
+ rwAlink (SB_RCINDXP_REGA4 | portId << 24, 0xFFFFFFFF, BIT29);\r
+}\r
+\r
+/**\r
+ * sbGppDisableUnusedPadMap - Return GPP Pad Map\r
+ *\r
+ *\r
+ * @param[in] pConfig\r
+ *\r
+ */\r
+VOID\r
+sbGppDisableUnusedPadMap (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT32 Data32;\r
+ UINT32 HoldData32;\r
+ SBGPPPORTCONFIG *portCfg;\r
+ UINT8 cimGppLaneReversal;\r
+ UINT8 cimAlinkPhyPllPowerDown;\r
+ UINT8 cimGppPhyPllPowerDown;\r
+\r
+ cimAlinkPhyPllPowerDown = (UINT8) pConfig->AlinkPhyPllPowerDown;\r
+ cimGppLaneReversal = (UINT8) pConfig->GppLaneReversal;\r
+ cimGppPhyPllPowerDown = (UINT8) pConfig->GppPhyPllPowerDown;\r
+#if SB_CIMx_PARAMETER == 0\r
+ cimGppLaneReversal = cimGppLaneReversalDefault;\r
+ cimAlinkPhyPllPowerDown = cimAlinkPhyPllPowerDownDefault;\r
+ cimGppPhyPllPowerDown = cimGppPhyPllPowerDownDefault;\r
+#endif\r
+\r
+ Data32 = 0;\r
+ HoldData32 = 0;\r
+ switch ( pConfig->GppLinkConfig ) {\r
+ case GPP_CFGMODE_X4000:\r
+ portCfg = &pConfig->PORTCONFIG[0].PortCfg;\r
+ if ( portCfg->PortDetected == FALSE ) {\r
+ Data32 |= 0x0f0f;\r
+ HoldData32 |= 0x1000;\r
+ }\r
+ break;\r
+ case GPP_CFGMODE_X2200:\r
+ portCfg = &pConfig->PORTCONFIG[0].PortCfg;\r
+ if ( portCfg->PortDetected == FALSE ) {\r
+ Data32 |= ( cimGppLaneReversal )? 0x0c0c:0x0303;\r
+ HoldData32 |= 0x1000;\r
+ }\r
+ portCfg = &pConfig->PORTCONFIG[1].PortCfg;\r
+ if ( portCfg->PortDetected == FALSE ) {\r
+ Data32 |= ( cimGppLaneReversal )? 0x0303:0x0c0c;\r
+ HoldData32 |= 0x2000;\r
+ }\r
+ break;\r
+ case GPP_CFGMODE_X2110:\r
+ portCfg = &pConfig->PORTCONFIG[0].PortCfg;\r
+ if ( portCfg->PortDetected == FALSE ) {\r
+ Data32 |= ( cimGppLaneReversal )? 0x0c0c:0x0303;\r
+ HoldData32 |= 0x1000;\r
+ }\r
+ portCfg = &pConfig->PORTCONFIG[1].PortCfg;\r
+ if ( portCfg->PortDetected == FALSE ) {\r
+ Data32 |= ( cimGppLaneReversal )? 0x0202:0x0404;\r
+ HoldData32 |= 0x2000;\r
+ }\r
+ portCfg = &pConfig->PORTCONFIG[2].PortCfg;\r
+ if ( portCfg->PortDetected == FALSE ) {\r
+ Data32 |= ( cimGppLaneReversal )? 0x0101:0x0808;\r
+ HoldData32 |= 0x4000;\r
+ }\r
+ break;\r
+ case GPP_CFGMODE_X1111:\r
+ portCfg = &pConfig->PORTCONFIG[0].PortCfg;\r
+ if ( portCfg->PortDetected == FALSE ) {\r
+ Data32 |= ( cimGppLaneReversal )? 0x0808:0x0101;\r
+ HoldData32 |= 0x1000;\r
+ }\r
+ portCfg = &pConfig->PORTCONFIG[1].PortCfg;\r
+ if ( portCfg->PortDetected == FALSE ) {\r
+ Data32 |= ( cimGppLaneReversal )? 0x0404:0x0202;\r
+ HoldData32 |= 0x2000;\r
+ }\r
+ portCfg = &pConfig->PORTCONFIG[2].PortCfg;\r
+ if ( portCfg->PortDetected == FALSE ) {\r
+ Data32 |= ( cimGppLaneReversal )? 0x0202:0x0404;\r
+ HoldData32 |= 0x4000;\r
+ }\r
+ portCfg = &pConfig->PORTCONFIG[3].PortCfg;\r
+ if ( portCfg->PortDetected == FALSE ) {\r
+ Data32 |= ( cimGppLaneReversal )? 0x0101:0x0808;\r
+ HoldData32 |= 0x8000;\r
+ }\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+// RPR 5.11 Power Saving With GPP Disable\r
+// ABCFG 0xC0[8] = 0x0\r
+// ABCFG 0xC0[15:12] = 0xF\r
+// Enable "Power Saving Feature for A-Link Express Lanes"\r
+// Enable "Power Saving Feature for GPP Lanes"\r
+// ABCFG 0x90[19] = 1\r
+// ABCFG 0x90[6] = 1\r
+// RCINDC_Reg 0x65 [27:0] = 0xFFFFFFF\r
+// ABCFG 0xC0[7:4] = 0x0\r
+ if ( (Data32 & 0xf) == 0xf ) Data32 |= 0x0cff0000;\r
+ if ( cimAlinkPhyPllPowerDown && cimGppPhyPllPowerDown ) {\r
+ rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), ~BIT8, 0);\r
+ rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, HoldData32);\r
+ rwAlink (SB_AX_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12));\r
+ rwAlink (RC_INDXC_REG40, ~(BIT9 + BIT4), (BIT0 + BIT3 + BIT12));\r
+ rwAlink ((SB_ABCFG_REG90 | (UINT32) (ABCFG << 29)), 0xFFFFFFFF, (BIT6 + BIT19));\r
+ rwAlink (RC_INDXC_REG65, 0xFFFFFFFF, Data32);\r
+ }\r
+}\r
--- /dev/null
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+\r
+#include "SBPLATFORM.h"\r
+\r
+\r
+VOID\r
+ReadIO (\r
+ IN UINT16 Address,\r
+ IN UINT8 OpFlag,\r
+ IN VOID* Value\r
+ )\r
+{\r
+ OpFlag = OpFlag & 0x7f;\r
+ switch ( OpFlag ) {\r
+ case AccWidthUint8:\r
+ *(UINT8*)Value = ReadIo8 (Address);\r
+ break;\r
+ case AccWidthUint16:\r
+ *(UINT16*)Value = ReadIo16 (Address);\r
+ break;\r
+ case AccWidthUint32:\r
+ *(UINT32*)Value = ReadIo32 (Address);\r
+ break;\r
+ }\r
+}\r
+\r
+VOID\r
+WriteIO (\r
+ IN UINT16 Address,\r
+ IN UINT8 OpFlag,\r
+ IN VOID* Value\r
+ )\r
+{\r
+ OpFlag = OpFlag & 0x7f;\r
+ switch ( OpFlag ) {\r
+ case AccWidthUint8:\r
+ WriteIo8 (Address, *(UINT8*)Value);\r
+ break;\r
+ case AccWidthUint16:\r
+ WriteIo16 (Address, *(UINT16*)Value);\r
+ break;\r
+ case AccWidthUint32:\r
+ WriteIo32 (Address, *(UINT32*)Value);\r
+ break;\r
+ }\r
+}\r
+\r
+VOID\r
+RWIO (\r
+ IN UINT16 Address,\r
+ IN UINT8 OpFlag,\r
+ IN UINT32 Mask,\r
+ IN UINT32 Data\r
+ )\r
+{\r
+ UINT32 Result;\r
+ ReadIO (Address, OpFlag, &Result);\r
+ Result = (Result & Mask) | Data;\r
+ WriteIO (Address, OpFlag, &Result);\r
+}\r
--- /dev/null
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+\r
+#include "SBPLATFORM.h"\r
+\r
+UINT32\r
+GetFixUp (\r
+ OUT VOID\r
+ )\r
+{\r
+ AMD_CONFIG_PARAMS* Result;\r
+ Result = (AMD_CONFIG_PARAMS*) getConfigPointer ();\r
+ if ( Result->ImageBasePtr > 0x100000 && Result->ImageBasePtr < 0xFF000000 ) {\r
+ return 0;\r
+ }\r
+ return Result->ImageBasePtr;\r
+}\r
--- /dev/null
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+\r
+#include "SBPLATFORM.h"\r
+\r
+VOID\r
+ReadMEM (\r
+ IN UINT32 Address,\r
+ IN UINT8 OpFlag,\r
+ IN VOID* Value\r
+ )\r
+{\r
+ OpFlag = OpFlag & 0x7f;\r
+ switch ( OpFlag ) {\r
+ case AccWidthUint8:\r
+ *((UINT8*)Value) = *((UINT8*) ((UINTN)Address));\r
+ break;\r
+ case AccWidthUint16:\r
+ //*((UINT16*)Value) = *((UINT16*) ((UINTN)Address)); //gcc break strict-aliasing rules\r
+ *((UINT8*)Value) = *((UINT8*) ((UINTN)Address));\r
+ *((UINT8*)Value + 1) = *((UINT8*)((UINTN)Address) + 1);\r
+ break;\r
+ case AccWidthUint32:\r
+ *((UINT32*)Value) = *((UINT32*) ((UINTN)Address));\r
+ break;\r
+ }\r
+}\r
+\r
+VOID\r
+WriteMEM (\r
+ IN UINT32 Address,\r
+ IN UINT8 OpFlag,\r
+ IN VOID* Value\r
+ )\r
+{\r
+ OpFlag = OpFlag & 0x7f;\r
+ switch ( OpFlag ) {\r
+ case AccWidthUint8 :\r
+ *((UINT8*) ((UINTN)Address)) = *((UINT8*)Value);\r
+ break;\r
+ case AccWidthUint16:\r
+ //*((UINT16*) ((UINTN)Address)) = *((UINT16*)Value); //gcc break strict-aliasing rules\r
+ *((UINT8*)((UINTN)Address)) = *((UINT8*)Value);\r
+ *((UINT8*)((UINTN)Address) + 1) = *((UINT8*)Value + 1);\r
+ break;\r
+ case AccWidthUint32:\r
+ *((UINT32*) ((UINTN)Address)) = *((UINT32*)Value);\r
+ break;\r
+ }\r
+}\r
+\r
+VOID\r
+RWMEM (\r
+ IN UINT32 Address,\r
+ IN UINT8 OpFlag,\r
+ IN UINT32 Mask,\r
+ IN UINT32 Data\r
+ )\r
+{\r
+ UINT32 Result;\r
+ ReadMEM (Address, OpFlag, &Result);\r
+ Result = (Result & Mask) | Data;\r
+ WriteMEM (Address, OpFlag, &Result);\r
+}\r
+\r
+\r
--- /dev/null
+#\r
+# This file is part of the coreboot project.\r
+#\r
+# Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+#\r
+# This program is free software; you can redistribute it and/or modify\r
+# it under the terms of the GNU General Public License as published by\r
+# the Free Software Foundation; version 2 of the License.\r
+#\r
+# This program is distributed in the hope that it will be useful,\r
+# but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+# GNU General Public License for more details.\r
+#\r
+# You should have received a copy of the GNU General Public License\r
+# along with this program; if not, write to the Free Software\r
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+#\r
+\r
+# CIMX Root directory\r
+CIMX_ROOT = src/vendorcode/amd/cimx\r
+\r
+CIMX_INC = -I$(src)/mainboard/$(MAINBOARDDIR)\r
+CIMX_INC += -I$(src)/southbridge/amd/cimx_wrapper/sb800\r
+CIMX_INC += -I$(CIMX_ROOT)/sb800\r
+#TODO merge withagesa lib functions\r
+CIMX_INC += -I$(CIMX_ROOT)/lib\r
+\r
+# CIMX LIB files\r
+romstage-y += MEMLIB.c\r
+romstage-y += PCILIB.c\r
+romstage-y += IOLIB.c\r
+romstage-y += PMIOLIB.c\r
+romstage-y += AMDLIB.c\r
+romstage-y += SBPELIB.c\r
+romstage-y += AMDSBLIB.c\r
+romstage-y += SBPOR.c\r
+romstage-y += ECLIB.c\r
+romstage-y += EC.c\r
+ramstage-y += DISPATCHER.c\r
+\r
+ramstage-y += ACPILIB.c\r
+ramstage-y += AZALIA.c\r
+ramstage-y += DISPATCHER.c\r
+ramstage-y += ECfanc.c\r
+ramstage-y += ECfanLIB.c\r
+ramstage-y += GEC.c\r
+ramstage-y += Gpp.c\r
+ramstage-y += PMIO2LIB.c\r
+ramstage-y += SATA.c\r
+ramstage-y += SBCMN.c\r
+ramstage-y += SBMAIN.c\r
+ramstage-y += SBPOR.c\r
+ramstage-y += MEMLIB.c\r
+ramstage-y += PCILIB.c\r
+ramstage-y += IOLIB.c\r
+ramstage-y += PMIOLIB.c\r
+ramstage-y += AMDLIB.c\r
+ramstage-y += SBPELIB.c\r
+ramstage-y += AMDSBLIB.c\r
+ramstage-y += ECLIB.c\r
+ramstage-y += EC.c\r
+ramstage-y += SMM.c\r
+ramstage-y += USB.c\r
+#ramstage-y += LEGACY.c\r
+#ramstage-y += SbModInf.c\r
+\r
+CIMX_CFLAGS =\r
+export CIMX_ROOT\r
+export CIMX_INC\r
+export CIMX_CFLAGS\r
+CC := $(CC) $(CIMX_INC)\r
+\r
+#######################################################################\r
+\r
--- /dev/null
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+\r
+#define BIOS_SIZE 0x04 //04 - 1MB\r
+#define LEGACY_FREE 0x00\r
+#define ACPI_SLEEP_TRAP 0x01\r
+//#define SPREAD_SPECTRUM_EPROM_LOAD 0x01\r
+\r
+/**\r
+ * Module Specific Defines for platform BIOS\r
+ *\r
+ */\r
+\r
+/**\r
+ * PCIEX_BASE_ADDRESS - Define PCIE base address\r
+ *\r
+ * @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000\r
+ */\r
+#ifdef MOVE_PCIEBAR_TO_F0000000\r
+ #define PCIEX_BASE_ADDRESS 0xF7000000\r
+#else\r
+ #define PCIEX_BASE_ADDRESS 0xE0000000\r
+#endif\r
+\r
+/**\r
+ * SMBUS0_BASE_ADDRESS - Smbus base address\r
+ *\r
+ */\r
+#ifndef SMBUS0_BASE_ADDRESS\r
+ #define SMBUS0_BASE_ADDRESS 0xB00\r
+#endif\r
+\r
+/**\r
+ * SMBUS1_BASE_ADDRESS - Smbus1 (ASF) base address\r
+ *\r
+ */\r
+#ifndef SMBUS1_BASE_ADDRESS\r
+ #define SMBUS1_BASE_ADDRESS 0xB20\r
+#endif\r
+\r
+/**\r
+ * GEC_BASE_ADDRESS - Gec Shadow ROM base address\r
+ *\r
+ */\r
+#ifndef GEC_BASE_ADDRESS\r
+ #define GEC_BASE_ADDRESS 0xFED61000\r
+#endif\r
+\r
+\r
+/**\r
+ * SIO_PME_BASE_ADDRESS - Super IO PME base address\r
+ *\r
+ */\r
+#ifndef SIO_PME_BASE_ADDRESS\r
+ #define SIO_PME_BASE_ADDRESS 0xE00\r
+#endif\r
+\r
+/**\r
+ * SPI_BASE_ADDRESS - SPI controller (ROM) base address\r
+ *\r
+ */\r
+#ifndef SPI_BASE_ADDRESS\r
+ #define SPI_BASE_ADDRESS 0xFEC10000\r
+#endif\r
+\r
+/**\r
+ * WATCHDOG_TIMER_BASE_ADDRESS - WATCHDOG timer base address\r
+ *\r
+ */\r
+#ifndef WATCHDOG_TIMER_BASE_ADDRESS\r
+ #define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 // Watchdog Timer Base Address\r
+#endif\r
+\r
+/**\r
+ * HPET_BASE_ADDRESS - HPET base address\r
+ *\r
+ */\r
+#ifndef HPET_BASE_ADDRESS\r
+ #define HPET_BASE_ADDRESS 0xFED00000 // HPET Base address\r
+#endif\r
+\r
+/**\r
+ * ALT_ADDR_400 - For some BIOS codebases which use 0x400 as ACPI base address\r
+ *\r
+ */\r
+#ifdef ALT_ADDR_400\r
+ #define ACPI_BLK_BASE 0x400\r
+#else\r
+ #define ACPI_BLK_BASE 0x800\r
+#endif\r
+\r
+#define PM1_STATUS_OFFSET 0x00\r
+#define PM1_ENABLE_OFFSET 0x02\r
+#define PM1_CONTROL_OFFSET 0x04\r
+#define PM_TIMER_OFFSET 0x08\r
+#define CPU_CONTROL_OFFSET 0x10\r
+#define EVENT_STATUS_OFFSET 0x20\r
+#define EVENT_ENABLE_OFFSET 0x24\r
+\r
+/**\r
+ * PM1_EVT_BLK_ADDRESS - ACPI power management Event Block base address\r
+ *\r
+ */\r
+#define PM1_EVT_BLK_ADDRESS ACPI_BLK_BASE + PM1_STATUS_OFFSET // AcpiPm1EvtBlkAddr\r
+\r
+/**\r
+ * PM1_CNT_BLK_ADDRESS - ACPI power management Control block base address\r
+ *\r
+ */\r
+#define PM1_CNT_BLK_ADDRESS ACPI_BLK_BASE + PM1_CONTROL_OFFSET // AcpiPm1CntBlkAddr\r
+\r
+/**\r
+ * PM1_TMR_BLK_ADDRESS - ACPI power management Timer block base address\r
+ *\r
+ */\r
+#define PM1_TMR_BLK_ADDRESS ACPI_BLK_BASE + PM_TIMER_OFFSET // AcpiPmTmrBlkAddr\r
+\r
+/**\r
+ * CPU_CNT_BLK_ADDRESS - ACPI power management CPU Control block base address\r
+ *\r
+ */\r
+#define CPU_CNT_BLK_ADDRESS ACPI_BLK_BASE + CPU_CONTROL_OFFSET // CpuControlBlkAddr\r
+\r
+/**\r
+ * GPE0_BLK_ADDRESS - ACPI power management General Purpose Event block base address\r
+ *\r
+ */\r
+#define GPE0_BLK_ADDRESS ACPI_BLK_BASE + EVENT_STATUS_OFFSET // AcpiGpe0BlkAddr\r
+\r
+/**\r
+ * SMI_CMD_PORT - ACPI SMI Command block base address\r
+ *\r
+ */\r
+#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr\r
+\r
+/**\r
+ * ACPI_PMA_CNT_BLK_ADDRESS - ACPI power management additional control block base address\r
+ *\r
+ */\r
+#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr\r
+\r
+/**\r
+ * SATA_IDE_MODE_SSID - Sata controller IDE mode SSID.\r
+ * Define value for SSID while SATA controller set to IDE mode.\r
+ */\r
+#ifndef SATA_IDE_MODE_SSID\r
+ #define SATA_IDE_MODE_SSID 0x43901002\r
+#endif\r
+\r
+/**\r
+ * SATA_RAID_MODE_SSID - Sata controller RAID mode SSID.\r
+ * Define value for SSID while SATA controller set to RAID mode.\r
+ */\r
+#ifndef SATA_RAID_MODE_SSID\r
+ #define SATA_RAID_MODE_SSID 0x43921002\r
+#endif\r
+\r
+/**\r
+ * SATA_RAID5_MODE_SSID - Sata controller RAID5 mode SSID.\r
+ * Define value for SSID while SATA controller set to RAID5 mode.\r
+ */\r
+#ifndef SATA_RAID5_MODE_SSID\r
+ #define SATA_RAID5_MODE_SSID 0x43931002\r
+#endif\r
+\r
+/**\r
+ * SATA_AHCI_MODE_SSID - Sata controller AHCI mode SSID.\r
+ * Define value for SSID while SATA controller set to AHCI mode.\r
+ */\r
+#ifndef SATA_AHCI_SSID\r
+ #define SATA_AHCI_SSID 0x43911002\r
+#endif\r
+\r
+/**\r
+ * OHCI_SSID - All SB OHCI controllers SSID value.\r
+ *\r
+ */\r
+#ifndef OHCI_SSID\r
+ #define OHCI_SSID 0x43971002\r
+#endif\r
+\r
+/**\r
+ * EHCI_SSID - All SB EHCI controllers SSID value.\r
+ *\r
+ */\r
+#ifndef EHCI_SSID\r
+ #define EHCI_SSID 0x43961002\r
+#endif\r
+\r
+/**\r
+ * OHCI4_SSID - OHCI (USB 1.1 mode *HW force) controllers SSID value.\r
+ *\r
+ */\r
+#ifndef OHCI4_SSID\r
+ #define OHCI4_SSID 0x43991002\r
+#endif\r
+\r
+/**\r
+ * SMBUS_SSID - Smbus controller (South Bridge device 0x14 function 0) SSID value.\r
+ *\r
+ */\r
+#ifndef SMBUS_SSID\r
+ #define SMBUS_SSID 0x43851002\r
+#endif\r
+\r
+/**\r
+ * IDE_SSID - SATA IDE controller (South Bridge device 0x14 function 1) SSID value.\r
+ *\r
+ */\r
+#ifndef IDE_SSID\r
+ #define IDE_SSID 0x439C1002\r
+#endif\r
+\r
+/**\r
+ * AZALIA_SSID - AZALIA controller (South Bridge device 0x14 function 2) SSID value.\r
+ *\r
+ */\r
+#ifndef AZALIA_SSID\r
+ #define AZALIA_SSID 0x43831002\r
+#endif\r
+\r
+/**\r
+ * LPC_SSID - LPC controller (South Bridge device 0x14 function 3) SSID value.\r
+ *\r
+ */\r
+#ifndef LPC_SSID\r
+ #define LPC_SSID 0x439D1002\r
+#endif\r
+\r
+/**\r
+ * PCIB_SSID - PCIB controller (South Bridge device 0x14 function 4) SSID value.\r
+ *\r
+ */\r
+#ifndef PCIB_SSID\r
+ #define PCIB_SSID 0x43841002\r
+#endif\r
+\r
+/**\r
+ * USB_PLL_Voltage - CG2 Clock voltage setting.\r
+ *\r
+ */\r
+#ifndef USB_PLL_Voltage\r
+ #define USB_PLL_Voltage 0x10\r
+#endif\r
+\r
+/**\r
+ * Spread_Spectrum_Type\r
+ *\r
+ * - 0 : Normal platform\r
+ * - 1 : Ontario platform\r
+ */\r
+#ifndef Spread_Spectrum_Type\r
+ #define Spread_Spectrum_Type 0x00\r
+#endif\r
--- /dev/null
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+\r
+\r
+#include "SBPLATFORM.h"\r
+\r
+VOID\r
+ReadPCI (\r
+ IN UINT32 Address,\r
+ IN UINT8 OpFlag,\r
+ IN VOID* Value\r
+ )\r
+{\r
+ OpFlag = OpFlag & 0x7f;\r
+\r
+ if ( (UINT16)Address < 0xff ) {\r
+ //Normal Config Access\r
+ UINT32 AddrCf8;\r
+ AddrCf8 = (1 << 31) + ((Address >> 8) & 0x0FFFF00) + (Address & 0xFC);\r
+ WriteIO (0xCf8, AccWidthUint32, &AddrCf8);\r
+ ReadIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value);\r
+ }\r
+}\r
+\r
+VOID\r
+WritePCI (\r
+ IN UINT32 Address,\r
+ IN UINT8 OpFlag,\r
+ IN VOID* Value\r
+ )\r
+{\r
+ OpFlag = OpFlag & 0x7f;\r
+ if ( (UINT16)Address < 0xff ) {\r
+ //Normal Config Access\r
+ UINT32 AddrCf8;\r
+ AddrCf8 = (1 << 31) + ((Address >> 8)&0x0FFFF00) + (Address & 0xFC);\r
+ WriteIO (0xCf8, AccWidthUint32, &AddrCf8);\r
+ WriteIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value);\r
+ }\r
+}\r
+\r
+VOID\r
+RWPCI (\r
+ IN UINT32 Address,\r
+ IN UINT8 OpFlag,\r
+ IN UINT32 Mask,\r
+ IN UINT32 Data\r
+ )\r
+{\r
+ UINT32 Result;\r
+ Result = 0;\r
+ OpFlag = OpFlag & 0x7f;\r
+ ReadPCI (Address, OpFlag, &Result);\r
+ Result = (Result & Mask) | Data;\r
+ WritePCI (Address, OpFlag, &Result);\r
+}\r
--- /dev/null
+/**\r
+ * @file\r
+ *\r
+ * Southbridge PMIO2 access common routine\r
+ *\r
+ */\r
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+\r
+#include "SBPLATFORM.h"\r
+\r
+\r
+/*----------------------------------------------------------------------------------------*/\r
+/**\r
+ * Read PMIO2\r
+ *\r
+ *\r
+ *\r
+ * @param[in] Address - PMIO2 Offset value\r
+ * @param[in] OpFlag - Access sizes\r
+ * @param[in] Value - Read Data Buffer\r
+ *\r
+ */\r
+VOID\r
+ReadPMIO2 (\r
+ IN UINT8 Address,\r
+ IN UINT8 OpFlag,\r
+ IN VOID* Value\r
+ )\r
+{\r
+ UINT8 i;\r
+ OpFlag = OpFlag & 0x7f;\r
+\r
+ if ( OpFlag == 0x02 ) {\r
+ OpFlag = 0x03;\r
+ }\r
+ for ( i = 0; i <= OpFlag; i++ ) {\r
+ WriteIO (0xCD0, AccWidthUint8, &Address); // SB_IOMAP_REGCD0\r
+ Address++;\r
+ ReadIO (0xCD1, AccWidthUint8, (UINT8 *) Value + i); // SB_IOMAP_REGCD1\r
+ }\r
+}\r
+\r
+/*----------------------------------------------------------------------------------------*/\r
+/**\r
+ * Write PMIO 2\r
+ *\r
+ *\r
+ *\r
+ * @param[in] Address - PMIO2 Offset value\r
+ * @param[in] OpFlag - Access sizes\r
+ * @param[in] Value - Write Data Buffer\r
+ *\r
+ */\r
+VOID\r
+WritePMIO2 (\r
+ IN UINT8 Address,\r
+ IN UINT8 OpFlag,\r
+ IN VOID* Value\r
+ )\r
+{\r
+ UINT8 i;\r
+ OpFlag = OpFlag & 0x7f;\r
+\r
+ if ( OpFlag == 0x02 ) {\r
+ OpFlag = 0x03;\r
+ }\r
+ for ( i = 0; i <= OpFlag; i++ ) {\r
+ WriteIO (0xCD0, AccWidthUint8, &Address); // SB_IOMAP_REGCD0\r
+ Address++;\r
+ WriteIO (0xCD1, AccWidthUint8, (UINT8 *)Value + i); // SB_IOMAP_REGCD1\r
+ }\r
+}\r
+\r
+/*----------------------------------------------------------------------------------------*/\r
+/**\r
+ * RWPMIO2 - Read/Write PMIO2\r
+ *\r
+ *\r
+ *\r
+ * @param[in] Address - PMIO2 Offset value\r
+ * @param[in] OpFlag - Access sizes\r
+ * @param[in] AndMask - Data And Mask 32 bits\r
+ * @param[in] OrMask - Data OR Mask 32 bits\r
+ *\r
+ */\r
+VOID\r
+RWPMIO2 (\r
+ IN UINT8 Address,\r
+ IN UINT8 OpFlag,\r
+ IN UINT32 AndMask,\r
+ IN UINT32 OrMask\r
+ )\r
+{\r
+ UINT32 Result;\r
+ OpFlag = OpFlag & 0x7f;\r
+ ReadPMIO2 (Address, OpFlag, &Result);\r
+ Result = (Result & AndMask) | OrMask;\r
+ WritePMIO2 (Address, OpFlag, &Result);\r
+}\r
--- /dev/null
+/**\r
+ * @file\r
+ *\r
+ * Southbridge PMIO access common routine\r
+ *\r
+ */\r
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+\r
+#include "SBPLATFORM.h"\r
+\r
+/*----------------------------------------------------------------------------------------*/\r
+/**\r
+ * Read PMIO\r
+ *\r
+ *\r
+ *\r
+ * @param[in] Address - PMIO Offset value\r
+ * @param[in] OpFlag - Access sizes\r
+ * @param[in] Value - Read Data Buffer\r
+ *\r
+ */\r
+VOID\r
+ReadPMIO (\r
+ IN UINT8 Address,\r
+ IN UINT8 OpFlag,\r
+ IN VOID* Value\r
+ )\r
+{\r
+ UINT8 i;\r
+ OpFlag = OpFlag & 0x7f;\r
+\r
+ if ( OpFlag == 0x02 ) {\r
+ OpFlag = 0x03;\r
+ }\r
+ for ( i = 0; i <= OpFlag; i++ ) {\r
+ WriteIO (0xCD6, AccWidthUint8, &Address); // SB_IOMAP_REGCD6\r
+ Address++;\r
+ ReadIO (0xCD7, AccWidthUint8, (UINT8 *)Value + i); // SB_IOMAP_REGCD7\r
+ }\r
+}\r
+\r
+/*----------------------------------------------------------------------------------------*/\r
+/**\r
+ * Write PMIO\r
+ *\r
+ *\r
+ *\r
+ * @param[in] Address - PMIO Offset value\r
+ * @param[in] OpFlag - Access sizes\r
+ * @param[in] Value - Write Data Buffer\r
+ *\r
+ */\r
+VOID\r
+WritePMIO (\r
+ IN UINT8 Address,\r
+ IN UINT8 OpFlag,\r
+ IN VOID* Value\r
+ )\r
+{\r
+ UINT8 i;\r
+ OpFlag = OpFlag & 0x7f;\r
+\r
+ if ( OpFlag == 0x02 ) {\r
+ OpFlag = 0x03;\r
+ }\r
+ for ( i = 0; i <= OpFlag; i++ ) {\r
+ WriteIO (0xCD6, AccWidthUint8, &Address); // SB_IOMAP_REGCD6\r
+ Address++;\r
+ WriteIO (0xCD7, AccWidthUint8, (UINT8 *)Value + i); // SB_IOMAP_REGCD7\r
+ }\r
+}\r
+\r
+/*----------------------------------------------------------------------------------------*/\r
+/**\r
+ * RWPMIO - Read/Write PMIO\r
+ *\r
+ *\r
+ *\r
+ * @param[in] Address - PMIO Offset value\r
+ * @param[in] OpFlag - Access sizes\r
+ * @param[in] AndMask - Data And Mask 32 bits\r
+ * @param[in] OrMask - Data OR Mask 32 bits\r
+ *\r
+ */\r
+VOID\r
+RWPMIO (\r
+ IN UINT8 Address,\r
+ IN UINT8 OpFlag,\r
+ IN UINT32 AndMask,\r
+ IN UINT32 OrMask\r
+ )\r
+{\r
+ UINT32 Result;\r
+ OpFlag = OpFlag & 0x7f;\r
+ ReadPMIO (Address, OpFlag, &Result);\r
+ Result = (Result & AndMask) | OrMask;\r
+ WritePMIO (Address, OpFlag, &Result);\r
+}\r
--- /dev/null
+\r
+/**\r
+ * @file\r
+ *\r
+ * Config Southbridge SATA controller\r
+ *\r
+ * Init SATA features.\r
+ *\r
+ * @xrefitem bom "File Content Label" "Release Content"\r
+ * @e project: CIMx-SB\r
+ * @e sub-project:\r
+ * @e \$Revision:$ @e \$Date:$\r
+ *\r
+ */\r
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+ \r
+#include "SBPLATFORM.h"\r
+\r
+//\r
+// Declaration of local functions\r
+//\r
+VOID sataSetIrqIntResource (IN AMDSBCFG* pConfig);\r
+VOID sataBar5setting (IN AMDSBCFG* pConfig, IN UINT32 *pBar5);\r
+VOID shutdownUnconnectedSataPortClock (IN AMDSBCFG* pConfig, IN UINT32 ddBar5);\r
+VOID sataDriveDetection (IN AMDSBCFG* pConfig, IN UINT32 *pBar5);\r
+\r
+/**\r
+ * sataSetIrqIntResource - Config SATA IRQ/INT# resource\r
+ *\r
+ *\r
+ * - Private function\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+sataSetIrqIntResource (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT8 dbValue;\r
+ // IRQ14/IRQ15 come from IDE or SATA\r
+ dbValue = 0x08;\r
+ WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue);\r
+ ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);\r
+ dbValue = dbValue & 0x0F;\r
+ if (pConfig->SataClass == 3) {\r
+ dbValue = dbValue | 0x50;\r
+ } else {\r
+ if (pConfig->SataIdeMode == 1) {\r
+ // Both IDE & SATA set to Native mode\r
+ dbValue = dbValue | 0xF0;\r
+ }\r
+ }\r
+ WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);\r
+}\r
+\r
+/**\r
+ * sataBar5setting - Config SATA BAR5\r
+ *\r
+ * - Private function\r
+ *\r
+ * @param[in] pConfig - Southbridge configuration structure pointer.\r
+ * @param[in] *pBar5 - SATA BAR5 buffer.\r
+ *\r
+ */\r
+VOID\r
+sataBar5setting (\r
+ IN AMDSBCFG* pConfig,\r
+ IN UINT32 *pBar5\r
+ )\r
+{\r
+ //Get BAR5 value\r
+ ReadPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, pBar5);\r
+ //Assign temporary BAR if is not already assigned\r
+ if ( (*pBar5 == 0) || (*pBar5 == - 1) ) {\r
+ //assign temporary BAR5\r
+ if ( (pConfig->TempMMIO == 0) || (pConfig->TempMMIO == - 1) ) {\r
+ *pBar5 = 0xFEC01000;\r
+ } else {\r
+ *pBar5 = pConfig->TempMMIO;\r
+ }\r
+ WritePCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, pBar5);\r
+ }\r
+ //Clear Bits 9:0\r
+ *pBar5 = *pBar5 & 0xFFFFFC00;\r
+}\r
+/**\r
+ * shutdownUnconnectedSataPortClock - Shutdown unconnected Sata port clock\r
+ *\r
+ * - Private function\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ * @param[in] ddBar5 Sata BAR5 base address.\r
+ *\r
+ */\r
+VOID\r
+shutdownUnconnectedSataPortClock (\r
+ IN AMDSBCFG* pConfig,\r
+ IN UINT32 ddBar5\r
+ )\r
+{\r
+ UINT8 dbPortNum;\r
+ UINT8 dbPortSataStatus;\r
+ UINT8 NumOfPorts;\r
+ UINT8 cimSataClkAutoOff;\r
+\r
+ cimSataClkAutoOff = (UINT8) pConfig->SataClkAutoOff;\r
+#if SB_CIMx_PARAMETER == 0\r
+ cimSataClkAutoOff = cimSataClkAutoOffDefault;\r
+#endif\r
+ NumOfPorts = 0;\r
+ if ( cimSataClkAutoOff == TRUE ) {\r
+ for ( dbPortNum = 0; dbPortNum < 6; dbPortNum++ ) {\r
+ ReadMEM (ddBar5 + SB_SATA_BAR5_REG128 + (dbPortNum * 0x80), AccWidthUint8, &dbPortSataStatus);\r
+ // Shutdown the clock for the port and do the necessary port reporting changes.\r
+ // ?? Error port status should be 1 not 3\r
+ if ( ((dbPortSataStatus & 0x0F) != 0x03) && (! ((pConfig->SataEspPort) & (1 << dbPortNum))) ) {\r
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, (1 << dbPortNum));\r
+ RWMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, ~(1 << dbPortNum), 00);\r
+ }\r
+ } //end of for (dbPortNum=0;dbPortNum<6;dbPortNum++)\r
+ ReadMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, &dbPortSataStatus);\r
+ //if all ports are in disabled state, report atleast one port\r
+ if ( (dbPortSataStatus & 0x3F) == 0) {\r
+ RWMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, (UINT32) ~(0x3F), 01);\r
+ }\r
+ ReadMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, &dbPortSataStatus);\r
+ for (dbPortNum = 0; dbPortNum < 6; dbPortNum ++) {\r
+ if (dbPortSataStatus & (1 << dbPortNum)) {\r
+ NumOfPorts++;\r
+ }\r
+ }\r
+ if ( NumOfPorts == 0) {\r
+ NumOfPorts = 0x01;\r
+ }\r
+ RWMEM (ddBar5 + SB_SATA_BAR5_REG00, AccWidthUint8, 0xE0, NumOfPorts - 1);\r
+ } //end of SataClkAuto Off option\r
+}\r
+\r
+/**\r
+ * Table for class code of SATA Controller in different modes\r
+ *\r
+ *\r
+ *\r
+ *\r
+ */\r
+UINT32 sataIfCodeTable[] =\r
+{\r
+ 0x01018F40, //sata class ID of IDE\r
+ 0x01040040, //sata class ID of RAID\r
+ 0x01060140, //sata class ID of AHCI\r
+ 0x01018A40, //sata class ID of Legacy IDE\r
+ 0x01018F40, //sata class ID of IDE to AHCI mode\r
+};\r
+\r
+/**\r
+ * Table for device id of SATA Controller in different modes\r
+ *\r
+ *\r
+ *\r
+ *\r
+ */\r
+UINT16 sataDeviceIDTable[] =\r
+{\r
+ 0x4390, //sata device ID of IDE\r
+ 0x4392, //sata device ID of RAID\r
+ 0x4391, //sata class ID of AHCI\r
+ 0x4390, //sata device ID of Legacy IDE\r
+ 0x4390, //sata device ID of IDE->AHCI mode\r
+};\r
+\r
+/**\r
+ * Table for Sata Phy Fine Setting\r
+ *\r
+ *\r
+ *\r
+ *\r
+ */\r
+SATAPHYSETTING sataPhyTable[] =\r
+{\r
+ {0x3006, 0x0056A607},\r
+ {0x2006, 0x00061400},\r
+ {0x1006, 0x00061302},\r
+\r
+ {0x3206, 0x0056A607},\r
+ {0x2206, 0x00061400},\r
+ {0x1206, 0x00061302},\r
+\r
+ {0x3406, 0x0056A607},\r
+ {0x2406, 0x00061402},\r
+ {0x1406, 0x00064300},\r
+\r
+ {0x3606, 0x0056A607},\r
+ {0x2606, 0x00061402},\r
+ {0x1606, 0x00064300},\r
+\r
+ {0x3806, 0x0056A700},\r
+ {0x2806, 0x00061502},\r
+ {0x1806, 0x00064302},\r
+\r
+ {0x3A06, 0x0056A700},\r
+ {0x2A06, 0x00061502},\r
+ {0x1A06, 0x00064302}\r
+};\r
+\r
+/**\r
+ * sataInitBeforePciEnum - Config SATA controller before PCI emulation\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+sataInitBeforePciEnum (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT32 ddTempVar;\r
+ UINT32 ddValue;\r
+ UINT32 *tempptr;\r
+ UINT16 *pDeviceIdptr;\r
+ UINT32 dwDeviceId;\r
+ UINT8 dbValue;\r
+ UINT8 pValue;\r
+ UINT16 i;\r
+ SATAPHYSETTING *pPhyTable;\r
+\r
+ ddTempVar = NULL;\r
+ // BIT0 Enable write access to PCI header (reg 08h-0Bh) by setting SATA PCI register 40h\r
+ // BIT4: Disable fast boot\r
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0 + BIT2 + BIT4);\r
+ // BIT0 Enable write access to PCI header (reg 08h-0Bh) by setting IDE PCI register 40h\r
+ RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0);\r
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8 | S3_SAVE, 0, pConfig->SataPortPower);\r
+ dbValue = (UINT8)pConfig->SataClass;\r
+ if (dbValue == AHCI_MODE_4394) {\r
+ dbValue = AHCI_MODE;\r
+ }\r
+ if (dbValue == IDE_TO_AHCI_MODE_4394) {\r
+ dbValue = IDE_TO_AHCI_MODE;\r
+ }\r
+ // Disable PATA MSI\r
+ RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG34), AccWidthUint8 | S3_SAVE, 0x00, 0x00);\r
+ RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG06), AccWidthUint8 | S3_SAVE, 0xEF, 0x00);\r
+\r
+ // Get the appropriate class code from the table and write it to PCI register 08h-0Bh\r
+ // Set the appropriate SATA class based on the input parameters\r
+ // SATA IDE Controller Class ID & SSID\r
+ tempptr = (UINT32 *) FIXUP_PTR (&sataIfCodeTable[0]);\r
+ if ( (pConfig->SataIdeMode == 1) && (pConfig->SataClass != 3) ) {\r
+ ddValue = tempptr[0];\r
+ // Write the class code to IDE PCI register 08h-0Bh\r
+ RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG08), AccWidthUint32 | S3_SAVE, 0, ddValue);\r
+ }\r
+ ddValue = tempptr[dbValue];\r
+ // Write the class code to SATA PCI register 08h-0Bh\r
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, ddValue);\r
+ if ( pConfig->SataClass == LEGACY_IDE_MODE ) {\r
+ //Set PATA controller to native mode\r
+ RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG09), AccWidthUint8 | S3_SAVE, 0x00, 0x08F);\r
+ }\r
+ if (pConfig->BuildParameters.IdeSsid != NULL ) {\r
+ RWPCI ((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.IdeSsid);\r
+ }\r
+ // SATA Controller Class ID & SSID\r
+ pDeviceIdptr = (UINT16 *) FIXUP_PTR (&sataDeviceIDTable[0]);\r
+ if ( pConfig->BuildParameters.SataIDESsid != NULL ) {\r
+ ddTempVar = pConfig->BuildParameters.SataIDESsid;\r
+ }\r
+ dwDeviceId = pDeviceIdptr[dbValue];\r
+ if ( pConfig->SataClass == RAID_MODE) {\r
+ if ( pConfig->BuildParameters.SataRAID5Ssid != NULL ) {\r
+ ddTempVar = pConfig->BuildParameters.SataRAID5Ssid;\r
+ }\r
+ dwDeviceId = V_SB_SATA_RAID5_DID;\r
+ pValue = SATA_EFUSE_LOCATION;\r
+ getEfuseStatus (&pValue);\r
+ if (( pValue & SATA_EFUSE_BIT ) || ( pConfig->SataForceRaid == 1 )) {\r
+ dwDeviceId = V_SB_SATA_RAID_DID;\r
+ if ( pConfig->BuildParameters.SataRAIDSsid != NULL ) {\r
+ ddTempVar = pConfig->BuildParameters.SataRAIDSsid;\r
+ }\r
+ }\r
+ }\r
+ if ( ((pConfig->SataClass) == AHCI_MODE) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE) ||\r
+ ((pConfig->SataClass) == AHCI_MODE_4394) || ((pConfig->SataClass) == IDE_TO_AHCI_MODE_4394) ) {\r
+ if ( pConfig->BuildParameters.SataAHCISsid != NULL ) { \r
+ ddTempVar = pConfig->BuildParameters.SataAHCISsid;\r
+ }\r
+ }\r
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, dwDeviceId);\r
+ if ( ddTempVar != NULL ) {\r
+ RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG2C, AccWidthUint32 | S3_SAVE, 0x00, ddTempVar);\r
+ }\r
+ // SATA IRQ Resource\r
+ sataSetIrqIntResource (pConfig);\r
+\r
+ // 8.4 SATA PHY Programming Sequence\r
+ pPhyTable = (SATAPHYSETTING*)FIXUP_PTR (&sataPhyTable[0]);\r
+ for (i = 0; i < (sizeof (sataPhyTable) / sizeof (SATAPHYSETTING)); i++) {\r
+ RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG84, AccWidthUint16 | S3_SAVE, ~(BIT1 + BIT2 + BIT9 + BIT10 + BIT11 + BIT12 + BIT13 + BIT14), pPhyTable->wPhyCoreControl);\r
+ RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG94, AccWidthUint32 | S3_SAVE, 0x00, pPhyTable->dwPhyFineTune);\r
+ ++pPhyTable;\r
+ }\r
+\r
+// CallBackToOEM (SATA_PHY_PROGRAMMING, NULL, pConfig);\r
+\r
+ RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0);\r
+ // Disable write access to PCI header\r
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0);\r
+}\r
+\r
+/**\r
+ * sataInitAfterPciEnum - Config SATA controller after PCI emulation\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+sataInitAfterPciEnum (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT32 ddAndMask;\r
+ UINT32 ddOrMask;\r
+ UINT32 ddBar5;\r
+ UINT8 dbVar;\r
+ UINT8 dbPortNum;\r
+ UINT8 dbEfuse;\r
+ UINT8 dbPortMode;\r
+ UINT16 SataPortMode;\r
+ UINT8 cimSataAggrLinkPmCap;\r
+ UINT8 cimSataPortMultCap;\r
+ UINT8 cimSataPscCap;\r
+ UINT8 cimSataSscCap;\r
+ UINT8 cimSataFisBasedSwitching;\r
+ UINT8 cimSataCccSupport;\r
+\r
+ cimSataAggrLinkPmCap = (UINT8) pConfig->SataAggrLinkPmCap;\r
+ cimSataPortMultCap = (UINT8) pConfig->SataPortMultCap;\r
+ cimSataPscCap = (UINT8) pConfig->SataPscCap;\r
+ cimSataSscCap = (UINT8) pConfig->SataSscCap;\r
+ cimSataFisBasedSwitching = (UINT8) pConfig->SataFisBasedSwitching;\r
+ cimSataCccSupport = (UINT8) pConfig->SataCccSupport;\r
+\r
+#if SB_CIMx_PARAMETER == 0\r
+ cimSataAggrLinkPmCap = cimSataAggrLinkPmCapDefault;\r
+ cimSataPortMultCap = cimSataPortMultCapDefault;\r
+ cimSataPscCap = cimSataPscCapDefault;\r
+ cimSataSscCap = cimSataSscCapDefault;\r
+ cimSataFisBasedSwitching = cimSataFisBasedSwitchingDefault;\r
+ cimSataCccSupport = cimSataCccSupportDefault;\r
+#endif\r
+\r
+ ddAndMask = 0;\r
+ ddOrMask = 0;\r
+ ddBar5 = 0;\r
+ if ( pConfig->SATAMODE.SataMode.SataController == 0 ) {\r
+ return; //return if SATA controller is disabled.\r
+ }\r
+\r
+ //Enable write access to pci header, pm capabilities\r
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xFF, BIT0);\r
+ //Disable AHCI Prefetch function\r
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8 | S3_SAVE, 0x7F, BIT7);\r
+\r
+ sataBar5setting (pConfig, &ddBar5);\r
+\r
+ ReadPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar);\r
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8,0xFF, 0x03); //memory and io access enable\r
+ dbEfuse = SATA_FIS_BASE_EFUSE_LOC;\r
+ getEfuseStatus (&dbEfuse);\r
+\r
+ if ( !cimSataPortMultCap ) {\r
+ ddAndMask |= BIT12;\r
+ }\r
+ if ( cimSataAggrLinkPmCap ) {\r
+ ddOrMask |= BIT11;\r
+ } else {\r
+ ddAndMask |= BIT11;\r
+ }\r
+ if ( cimSataPscCap ) {\r
+ ddOrMask |= BIT1;\r
+ }\r
+ if ( cimSataSscCap ) {\r
+ ddOrMask |= BIT26;\r
+ }\r
+ if ( cimSataFisBasedSwitching ) {\r
+ if (dbEfuse & BIT1) {\r
+ ddAndMask |= BIT10;\r
+ } else {\r
+ ddOrMask |= BIT10;\r
+ }\r
+ } else {\r
+ ddAndMask |= BIT10;\r
+ }\r
+ // RPR 8.10 Disabling CCC (Command Completion Coalescing) support.\r
+ if ( cimSataCccSupport ) {\r
+ ddOrMask |= BIT19;\r
+ } else {\r
+ ddAndMask |= BIT19;\r
+ }\r
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REGFC), AccWidthUint32 | S3_SAVE, ~ddAndMask, ddOrMask);\r
+\r
+\r
+ // SATA ESP port setting\r
+ // These config bits are set for SATA driver to identify which ports are external SATA ports and need to\r
+ // support hotplug. If a port is set as an external SATA port and need to support hotplug, then driver will\r
+ // not enable power management (HIPM & DIPM) for these ports.\r
+ if ( pConfig->SataEspPort != 0 ) {\r
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(pConfig->SataEspPort), 0);\r
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT12 + BIT13 + BIT14 + BIT15 + BIT16 + BIT17 + BIT5 + BIT4 + BIT3 + BIT2 + BIT1 + BIT0), (pConfig->SataEspPort << 12));\r
+ // RPR 8.7 External SATA Port Indication Registers\r
+ // If any of the ports was programmed as an external port, HCAP.SXS should also be set\r
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REGFC), AccWidthUint32 | S3_SAVE, ~(BIT20), BIT20);\r
+ } else {\r
+ // RPR 8.7 External SATA Port Indication Registers\r
+ // If any of the ports was programmed as an external port, HCAP.SXS should also be set (Clear for no ESP port)\r
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT5 + BIT4 + BIT3 + BIT2 + BIT1 + BIT0), 0x00);\r
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REGFC), AccWidthUint32 | S3_SAVE, ~(BIT20), 0x00);\r
+ }\r
+ if ( cimSataFisBasedSwitching ) {\r
+ if (dbEfuse & BIT1) {\r
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT22 + BIT23 + BIT24 + BIT25 + BIT26 + BIT27), 0x00);\r
+ } else {\r
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT22 + BIT23 + BIT24 + BIT25 + BIT26 + BIT27), (BIT22 + BIT23 + BIT24 + BIT25 + BIT26 + BIT27));\r
+ }\r
+ } else {\r
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REGF8), AccWidthUint32 | S3_SAVE, ~(BIT22 + BIT23 + BIT24 + BIT25 + BIT26 + BIT27), 0x00);\r
+ }\r
+\r
+ // Disabled SATA MSI and D3 Power State capability\r
+ // RPR 8.13 SATA MSI and D3 Power State Capability\r
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG34), AccWidthUint8 | S3_SAVE, 0, 0x70);\r
+\r
+ if (((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE)) {\r
+ // RIAD or AHCI\r
+ if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == DISABLED) {\r
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REG00), AccWidthUint8 | S3_SAVE, ~(BIT2 + BIT1 + BIT0), BIT2 + BIT0);\r
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REG0C), AccWidthUint8 | S3_SAVE, 0xC0, 0x3F);\r
+ // RPR 8.10 Disabling CCC (Command Completion Coalescing) support.\r
+ // 8 messages\r
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50 + 2), AccWidthUint8, ~(BIT3 + BIT2 + BIT1), BIT2 + BIT1);\r
+ } else {\r
+ // RPR 8.10 Disabling CCC (Command Completion Coalescing) support.\r
+ if ( pConfig->SataCccSupport ) {\r
+ // 8 messages\r
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50 + 2), AccWidthUint8, ~(BIT3 + BIT2 + BIT1), BIT2 + BIT1);\r
+ } else {\r
+ // 4 messages\r
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50 + 2), AccWidthUint8, ~(BIT3 + BIT2 + BIT1), BIT2);\r
+ }\r
+ }\r
+ }\r
+\r
+ if ( pConfig->BIOSOSHandoff == 1 ) {\r
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REG24), AccWidthUint8 | S3_SAVE, ~BIT0, BIT0);\r
+ } else {\r
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REG24), AccWidthUint8 | S3_SAVE, ~BIT0, 0x00);\r
+ }\r
+\r
+ SataPortMode = (UINT16)pConfig->SataPortMode;\r
+ dbPortNum = 0;\r
+ while ( dbPortNum < 6 ) {\r
+ dbPortMode = (UINT8) (SataPortMode & 3);\r
+ if ( (dbPortMode == BIT0) || (dbPortMode == BIT1) ) {\r
+ if ( dbPortMode == BIT0 ) {\r
+ // set GEN 1\r
+ RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0x0F, 0x10);\r
+ }\r
+ if ( dbPortMode == BIT1 ) {\r
+ // set GEN2 (default is GEN3)\r
+ RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0x0F, 0x20);\r
+ }\r
+ RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFF, 0x01);\r
+ }\r
+ SataPortMode >>= 2;\r
+ dbPortNum ++;\r
+ }\r
+ SbStall (1000);\r
+ SataPortMode = (UINT16)pConfig->SataPortMode;\r
+ dbPortNum = 0;\r
+ while ( dbPortNum < 6 ) {\r
+ dbPortMode = (UINT8) (SataPortMode & 3);\r
+ if ( (dbPortMode == BIT0) || (dbPortMode == BIT1) ) {\r
+ RWMEM (ddBar5 + SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFE, 0x00);\r
+ }\r
+ dbPortNum ++;\r
+ SataPortMode >>= 2;\r
+ }\r
+ WritePCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar);\r
+ //Disable write access to pci header, pm capabilities\r
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0);\r
+}\r
+\r
+\r
+/**\r
+ * sataInitMidPost - Config SATA controller in Middle POST.\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+sataInitMidPost (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT32 ddBar5;\r
+ sataBar5setting (pConfig, &ddBar5);\r
+ //If this is not S3 resume and also if SATA set to one of IDE mode, them implement drive detection workaround.\r
+ if ( ! (pConfig->S3Resume) && ( ((pConfig->SataClass) != AHCI_MODE) && ((pConfig->SataClass) != RAID_MODE) ) ) {\r
+ sataDriveDetection (pConfig, &ddBar5);\r
+ }\r
+}\r
+\r
+/**\r
+ * sataDriveDetection - Sata drive detection\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ * @param[in] *pBar5 Sata BAR5 base address.\r
+ *\r
+ */\r
+VOID\r
+sataDriveDetection (\r
+ IN AMDSBCFG* pConfig,\r
+ IN UINT32 *pBar5\r
+ )\r
+{\r
+ UINT32 ddVar0;\r
+ UINT8 dbPortNum;\r
+ UINT8 dbVar0;\r
+ UINT16 dwIoBase;\r
+ UINT16 dwVar0;\r
+ if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) ) {\r
+ for ( dbPortNum = 0; dbPortNum < 4; dbPortNum++ ) {\r
+ ReadMEM (*pBar5 + SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint32, &ddVar0);\r
+ if ( ( ddVar0 & 0x0F ) == 0x03 ) {\r
+ if ( dbPortNum & BIT0 ) {\r
+ //this port belongs to secondary channel\r
+ ReadPCI (((UINT32) (SATA_BUS_DEV_FUN << 16) + SB_SATA_REG18), AccWidthUint16, &dwIoBase);\r
+ } else {\r
+ //this port belongs to primary channel\r
+ ReadPCI (((UINT32) (SATA_BUS_DEV_FUN << 16) + SB_SATA_REG10), AccWidthUint16, &dwIoBase);\r
+ }\r
+ //if legacy ide mode, then the bar registers don't contain the correct values. So we need to hardcode them\r
+ if ( pConfig->SataClass == LEGACY_IDE_MODE ) {\r
+ dwIoBase = ( (0x170) | ((UINT16) ( (~((UINT8) (dbPortNum & BIT0) << 7)) & 0x80 )) );\r
+ }\r
+ if ( dbPortNum & BIT1 ) {\r
+ //this port is slave\r
+ dbVar0 = 0xB0;\r
+ } else {\r
+ //this port is master\r
+ dbVar0 = 0xA0;\r
+ }\r
+ dwIoBase &= 0xFFF8;\r
+ WriteIO (dwIoBase + 6, AccWidthUint8, &dbVar0);\r
+ //Wait in loop for 30s for the drive to become ready\r
+ for ( dwVar0 = 0; dwVar0 < 300000; dwVar0++ ) {\r
+ ReadIO (dwIoBase + 7, AccWidthUint8, &dbVar0);\r
+ if ( (dbVar0 & 0x88) == 0 ) {\r
+ break;\r
+ }\r
+ SbStall (100);\r
+ }\r
+ } //end of if ( ( ddVar0 & 0x0F ) == 0x03)\r
+ } //for (dbPortNum = 0; dbPortNum < 4; dbPortNum++)\r
+ } //if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE))\r
+}\r
+\r
+/**\r
+ * sataInitLatePost - Prepare SATA controller to boot to OS.\r
+ *\r
+ * - Set class ID to AHCI (if set to AHCI * Mode)\r
+ * - Enable AHCI interrupt\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+sataInitLatePost (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT32 ddBar5;\r
+ UINT8 dbVar;\r
+ UINT8 dbPortNum;\r
+\r
+ //Return immediately is sata controller is not enabled\r
+ if ( pConfig->SATAMODE.SataMode.SataController == 0 ) {\r
+ return;\r
+ }\r
+ //Enable write access to pci header, pm capabilities\r
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0);\r
+\r
+// if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == DISABLED) {\r
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 1), AccWidthUint8 | S3_SAVE, ~BIT7, BIT7);\r
+// }\r
+ sataBar5setting (pConfig, &ddBar5);\r
+\r
+ ReadPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar);\r
+ //Enable memory and io access\r
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, 0xFF, 0x03);\r
+\r
+ shutdownUnconnectedSataPortClock (pConfig, ddBar5);\r
+\r
+ if (( pConfig->SataClass == IDE_TO_AHCI_MODE) || ( pConfig->SataClass == IDE_TO_AHCI_MODE_4394 )) {\r
+ //program the AHCI class code\r
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, 0x01060100);\r
+ //Set interrupt enable bit\r
+ RWMEM ((ddBar5 + 0x04), AccWidthUint8, (UINT32)~0, BIT1);\r
+ //program the correct device id for AHCI mode\r
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, 0x4391);\r
+ }\r
+\r
+ if (( pConfig->SataClass == AHCI_MODE_4394 ) || ( pConfig->SataClass == IDE_TO_AHCI_MODE_4394 )) {\r
+ //program the correct device id for AHCI 4394 mode\r
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, 0x4394);\r
+ }\r
+\r
+ //Clear error status ?? only 4 port\r
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REG130), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);\r
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REG1B0), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);\r
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REG230), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);\r
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REG2B0), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);\r
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REG330), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);\r
+ RWMEM ((ddBar5 + SB_SATA_BAR5_REG3B0), AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);\r
+ //Restore memory and io access bits\r
+ WritePCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar );\r
+ //Disable write access to pci header and pm capabilities\r
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~BIT0, 0);\r
+ for ( dbPortNum = 0; dbPortNum < 6; dbPortNum++ ) {\r
+ RWMEM ((ddBar5 + 0x110 + (dbPortNum * 0x80)), AccWidthUint32, 0xFFFFFFFF, 0x00);\r
+ }\r
+}\r
+\r
+\r
--- /dev/null
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+\r
+#pragma pack (push, 1)\r
+\r
+#define CIMX_SB_REVISION "1.1.0.6"\r
+#define CIMX_SB_ID "SB80A13"\r
+#ifndef SBCIMx_Version\r
+ #define SBCIMx_Version 0x1106\r
+#endif //CIMx_Version\r
+\r
+\r
+/*--------------------------- Documentation Pages ---------------------------*/\r
+/**\r
+ * @page SB_POWERON_INIT_Page SB_POWERON_INIT\r
+ * @section SB_POWERON_INIT Interface Call\r
+ * Initialize structure referenced by AMDSBCFG to default recommended value.\r
+ * @subsection SB_POWERON_INIT_CallIn Call Prototype\r
+ * @par\r
+ * sbPowerOnInit ((AMDSBCFG*) pConfig) (Followed PH Interface)\r
+ * @subsection SB_BEFORE_PCI_INIT_CallID Service ID\r
+ * @par\r
+ * <TABLE border="0">\r
+ * <TR><TD class="indexkey" width=380> SB_POWERON_INIT --> 0x00010001 </TD></TR>\r
+ * </TABLE>\r
+ * @subsection SB_POWERON_INIT_CallOut Prepare for Callout\r
+ * @par\r
+ * Not Applicable (Not necessary for the current implementation)\r
+ * @subsection SB_POWERON_INIT_Config Prepare for Configuration Data.\r
+ * @par\r
+ * <TABLE border="0">\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::BiosSize </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::LegacyFree </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::EcKbd </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::Smbus0BaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::Smbus1BaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::SioPmeBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::WatchDogTimerBase </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::GecShadowRomBase </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::SpiRomBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::AcpiPm1EvtBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::AcpiPm1CntBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::AcpiPmTmrBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::CpuControlBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::AcpiGpe0BlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::SmiCmdPortAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::AcpiPmaCntBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * </TABLE>\r
+ *\r
+ */\r
+#define SB_POWERON_INIT 0x00010001\r
+#define OUTDEBUG_PORT 0x00010002\r
+/*--------------------------- Documentation Pages ---------------------------*/\r
+/**\r
+ * @page SB_BEFORE_PCI_INIT_Page SB_BEFORE_PCI_INIT\r
+ * @section SB_BEFORE_PCI_INIT Interface Call\r
+ * Initialize structure referenced by AMDSBCFG to default recommended value.\r
+ * @subsection SB_BEFORE_PCI_INIT_CallIn Call Prototype\r
+ * @par\r
+ * sbBeforePciInit ((AMDSBCFG*)pConfig) (Followed PH Interface)\r
+ * @subsection SB_BEFORE_PCI_INIT_CallID Service ID\r
+ * @par\r
+ * <TABLE border="0">\r
+ * <TR><TD class="indexkey" width=380> SB_BEFORE_PCI_INIT --> 0x00010010 </TD></TR>\r
+ * </TABLE>\r
+ * @subsection SB_BEFORE_PCI_INIT_CallOut Prepare for Callout\r
+ * @par\r
+ * <TABLE border="0">\r
+ * <TR><TD class="indexkey" width=380> @ref CB_SBGPP_RESET_ASSERT_Page "CB_SBGPP_RESET_ASSERT"</TD></TR>\r
+ * <TR><TD class="indexkey" width=380> @ref CB_SBGPP_RESET_DEASSERT_Page "CB_SBGPP_RESET_DEASSERT"</TD></TR>\r
+ * </TABLE>\r
+ * @subsection SB_BEFORE_PCI_INIT_Config Prepare for Configuration Data.\r
+ * @par\r
+ * <TABLE border="0">\r
+ * <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> AMDSBCFG::SataIdeMode </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> AMDSBCFG::USBDeviceConfig </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> AMDSBCFG::GecConfig </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaController </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> AMDSBCFG::PciClks </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::SataIDESsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::SataRAID5Ssid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::SataRAIDSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::SataAHCISsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::SmbusSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::LpcSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::PCIBSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>\r
+ * </TABLE>\r
+ *\r
+ */\r
+#define SB_BEFORE_PCI_INIT 0x00010010\r
+/*--------------------------- Documentation Pages ---------------------------*/\r
+/**\r
+ * @page SB_AFTER_PCI_INIT_Page SB_AFTER_PCI_INIT\r
+ * @section SB_AFTER_PCI_INIT Interface Call\r
+ * Initialize structure referenced by AMDSBCFG to default recommended value.\r
+ * @subsection SB_AFTER_PCI_INIT_CallIn Call Prototype\r
+ * @par\r
+ * sbAfterPciInit ((AMDSBCFG*)pConfig) (Followed PH Interface)\r
+ * @subsection SB_AFTER_PCI_INIT_CallID Service ID\r
+ * @par\r
+ * <TABLE border="0">\r
+ * <TR><TD class="indexkey" width=380> SB_AFTER_PCI_INIT --> 0x00010020 </TD></TR>\r
+ * </TABLE>\r
+ * @subsection SB_AFTER_PCI_INIT_CallOut Prepare for Callout\r
+ * @par\r
+ * Not Applicable (Not necessary for the current implementation)\r
+ * @subsection SB_AFTER_PCI_INIT_Config Prepare for Configuration Data.\r
+ * @par\r
+ * <TABLE border="0">\r
+ * <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> AMDSBCFG::SataEspPort </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaController </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaPinCfg </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaSdinPin </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::OhciSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::Ohci4Ssid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::EhciSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::AzaliaSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>\r
+ * </TABLE>\r
+ *\r
+ */\r
+#define SB_AFTER_PCI_INIT 0x00010020\r
+/*--------------------------- Documentation Pages ---------------------------*/\r
+/**\r
+ * @page SB_MID_POST_INIT_Page SB_MID_POST_INIT\r
+ * @section SB_MID_POST_INIT Interface Call\r
+ * Initialize structure referenced by AMDSBCFG to default recommended value.\r
+ * @subsection SB_MID_POST_INIT_CallIn Call Prototype\r
+ * @par\r
+ * sbMidPostInit ((AMDSBCFG*)pConfig) (Followed PH Interface)\r
+ * @subsection SB_MID_POST_INIT_CallID Service ID\r
+ * @par\r
+ * <TABLE border="0">\r
+ * <TR><TD class="indexkey" width=380> SB_MID_POST_INIT --> 0x00010021 </TD></TR>\r
+ * </TABLE>\r
+ * @subsection SB_MID_POST_INIT_CallOut Prepare for Callout\r
+ * @par\r
+ * Not Applicable (Not necessary for the current implementation)\r
+ * @subsection SB_MID_POST_INIT_Config Prepare for Configuration Data.\r
+ * @par\r
+ * <TABLE border="0">\r
+ * <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * </TABLE>\r
+ *\r
+ */\r
+#define SB_MID_POST_INIT 0x00010021\r
+/*--------------------------- Documentation Pages ---------------------------*/\r
+/**\r
+ * @page SB_LATE_POST_INIT_Page SB_LATE_POST_INIT\r
+ * @section SB_LATE_POST_INIT Interface Call\r
+ * Initialize structure referenced by AMDSBCFG to default recommended value.\r
+ * @subsection SB_LATE_POST_INIT_CallIn Call Prototype\r
+ * @par\r
+ * sbLatePost ((AMDSBCFG*)pConfig) (Followed PH Interface)\r
+ * @subsection SB_LATE_POST_INIT_CallID Service ID\r
+ * @par\r
+ * <TABLE border="0">\r
+ * <TR><TD class="indexkey" width=380> SB_LATE_POST_INIT --> 0x00010030 </TD></TR>\r
+ * </TABLE>\r
+ * @subsection SB_LATE_POST_INIT_CallOut Prepare for Callout\r
+ * @par\r
+ * Not Applicable (Not necessary for the current implementation)\r
+ * @subsection SB_LATE_POST_INIT_Config Prepare for Configuration Data.\r
+ * @par\r
+ * <TABLE border="0">\r
+ * <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * </TABLE>\r
+ *\r
+ */\r
+#define SB_LATE_POST_INIT 0x00010030\r
+/*--------------------------- Documentation Pages ---------------------------*/\r
+/**\r
+ * @page SB_BEFORE_PCI_RESTORE_INIT_Page SB_BEFORE_PCI_RESTORE_INIT\r
+ * @section SB_BEFORE_PCI_RESTORE_INIT Interface Call\r
+ * Initialize structure referenced by AMDSBCFG to default recommended value.\r
+ * @subsection SB_BEFORE_PCI_RESTORE_INIT_CallIn Call Prototype\r
+ * @par\r
+ * sbBeforePciRestoreInit ((AMDSBCFG*)pConfig) (Followed PH Interface)\r
+ * @subsection SB_BEFORE_PCI_RESTORE_INIT_CallID Service ID\r
+ * @par\r
+ * <TABLE border="0">\r
+ * <TR><TD class="indexkey" width=380> SB_BEFORE_PCI_RESTORE_INIT --> 0x00010040 </TD></TR>\r
+ * </TABLE>\r
+ * @subsection SB_BEFORE_PCI_RESTORE_INIT_CallOut Prepare for Callout\r
+ * @par\r
+ * <TABLE border="0">\r
+ * <TR><TD class="indexkey" width=380> @ref CB_SBGPP_RESET_ASSERT_Page "CB_SBGPP_RESET_ASSERT"</TD></TR>\r
+ * <TR><TD class="indexkey" width=380> @ref CB_SBGPP_RESET_DEASSERT_Page "CB_SBGPP_RESET_DEASSERT"</TD></TR>\r
+ * </TABLE>\r
+ * @subsection SB_BEFORE_PCI_RESTORE_INIT_Config Prepare for Configuration Data.\r
+ * @par\r
+ * <TABLE border="0">\r
+ * <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> AMDSBCFG::SataIdeMode </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> AMDSBCFG::USBDeviceConfig </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> AMDSBCFG::GecConfig </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaController </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> AMDSBCFG::PciClks </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::SataIDESsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::SataRAID5Ssid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::SataRAIDSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::SataAHCISsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::SmbusSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::LpcSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::PCIBSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>\r
+ * </TABLE>\r
+ *\r
+ */\r
+#define SB_BEFORE_PCI_RESTORE_INIT 0x00010040\r
+/*--------------------------- Documentation Pages ---------------------------*/\r
+/**\r
+ * @page SB_AFTER_PCI_RESTORE_INIT_Page SB_AFTER_PCI_RESTORE_INIT\r
+ * @section SB_AFTER_PCI_RESTORE_INIT Interface Call\r
+ * Initialize structure referenced by AMDSBCFG to default recommended value.\r
+ * @subsection SB_AFTER_PCI_RESTORE_INIT_CallIn Call Prototype\r
+ * @par\r
+ * sbAfterPciRestoreInit ((AMDSBCFG*)pConfig) (Followed PH Interface)\r
+ * @subsection SB_AFTER_PCI_RESTORE_INIT_CallID Service ID\r
+ * @par\r
+ * <TABLE border="0">\r
+ * <TR><TD class="indexkey" width=380> SB_AFTER_PCI_RESTORE_INIT --> 0x00010050 </TD></TR>\r
+ * </TABLE>\r
+ * @subsection SB_AFTER_PCI_RESTORE_INIT_CallOut Prepare for Callout\r
+ * @par\r
+ * Not Applicable (Not necessary for the current implementation)\r
+ * @subsection SB_AFTER_PCI_RESTORE_INIT_Config Prepare for Configuration Data.\r
+ * @par\r
+ * <TABLE border="0">\r
+ * <TR><TD class="indexkey" width=380> SATAST::SataController </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> SATAST::SataIdeCombinedMode </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> AMDSBCFG::SataClass </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> AMDSBCFG::SataEspPort </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaController </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaPinCfg </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> AMDSBCFG::AzaliaSdinPin </TD><TD class="indexvalue"><B>Required </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::OhciSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::Ohci4Ssid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::EhciSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>\r
+ * <TR><TD class="indexkey" width=380> BUILDPARAM::AzaliaSsid </TD><TD class="indexvalue"><B> Optional </B></TD></TR>\r
+ * </TABLE>\r
+ *\r
+ */\r
+#define SB_AFTER_PCI_RESTORE_INIT 0x00010050\r
+/*--------------------------- Documentation Pages ---------------------------*/\r
+/**\r
+ * @page SB_SMM_SERVICE_Page SB_SMM_SERVICE\r
+ * @section SB_SMM_SERVICE Interface Call\r
+ * Initialize structure referenced by AMDSBCFG to default recommended value.\r
+ * @subsection SB_SMM_SERVICE_CallIn Call Prototype\r
+ * @par\r
+ * sbSmmService ((AMDSBCFG*)pConfig) (Followed PH Interface)\r
+ * @subsection SB_SMM_SERVICE_CallID Service ID\r
+ * @par\r
+ * <TABLE border="0">\r
+ * <TR><TD class="indexkey" width=380> SB_SMM_SERVICE --> 0x00010060 </TD></TR>\r
+ * </TABLE>\r
+ * @subsection SB_SMM_SERVICE_CallOut Prepare for Callout\r
+ * @par\r
+ * Not Applicable (Not necessary for the current implementation)\r
+ * @subsection SB_SMM_SERVICE_Config Prepare for Configuration Data.\r
+ * @par\r
+ * Not necessary on current implementation\r
+ *\r
+ */\r
+#define SB_SMM_SERVICE 0x00010060\r
+/*--------------------------- Documentation Pages ---------------------------*/\r
+/**\r
+ * @page SB_SMM_ACPION_Page SB_SMM_ACPION\r
+ * @section SB_SMM_ACPION Interface Call\r
+ * Initialize structure referenced by AMDSBCFG to default recommended value.\r
+ * @subsection SB_SMM_ACPION_CallIn Call Prototype\r
+ * @par\r
+ * sbSmmAcpiOn ((AMDSBCFG*)pConfig) (Followed PH Interface)\r
+ * @subsection SB_SMM_ACPION_CallID Service ID\r
+ * @par\r
+ * <TABLE border="0">\r
+ * <TR><TD class="indexkey" width=380> SB_SMM_ACPION --> 0x00010061 </TD></TR>\r
+ * </TABLE>\r
+ * @subsection SB_SMM_ACPION_CallOut Prepare for Callout\r
+ * @par\r
+ * Not Applicable (Not necessary for the current implementation)\r
+ * @subsection SB_SMM_ACPION_Config Prepare for Configuration Data.\r
+ * @par\r
+ * Not necessary on current implementation\r
+ *\r
+ */\r
+#define SB_SMM_ACPION 0x00010061\r
+#define SB_EC_FANCONTROL 0x00010070\r
+\r
+#ifndef OEM_CALLBACK_BASE\r
+ #define OEM_CALLBACK_BASE 0x00010100\r
+#endif\r
+\r
+//0x00 - 0x0F callback functions are reserved for bootblock\r
+#define SATA_PHY_PROGRAMMING OEM_CALLBACK_BASE + 0x10\r
+#define PULL_UP_PULL_DOWN_SETTINGS OEM_CALLBACK_BASE + 0x20\r
+/*--------------------------- Documentation Pages ---------------------------*/\r
+/**\r
+ * @page CB_SBGPP_RESET_ASSERT_Page CB_SBGPP_RESET_ASSERT\r
+ * @section CB_SBGPP_RESET_ASSERT Interface Call\r
+ * Initialize structure referenced by AMDSBCFG to default recommended value.\r
+ * @subsection CB_SBGPP_RESET_ASSERT_CallID Service ID\r
+ * @par\r
+ * <TABLE border="0">\r
+ * <TR><TD class="indexkey" width=380> CB_SBGPP_RESET_ASSERT --> 0x00010130 </TD></TR>\r
+ * </TABLE>\r
+ * @subsection CB_SBGPP_RESET_ASSERT_Config Prepare for Configuration Data.\r
+ * @par\r
+ * Not necessary on current implementation\r
+ *\r
+ */\r
+#define CB_SBGPP_RESET_ASSERT OEM_CALLBACK_BASE + 0x30\r
+/*--------------------------- Documentation Pages ---------------------------*/\r
+/**\r
+ * @page CB_SBGPP_RESET_DEASSERT_Page CB_SBGPP_RESET_DEASSERT\r
+ * @section CB_SBGPP_RESET_DEASSERT Interface Call\r
+ * Initialize structure referenced by AMDSBCFG to default recommended value.\r
+ * @subsection CB_SBGPP_RESET_DEASSERT _CallID Service ID\r
+ * @par\r
+ * <TABLE border="0">\r
+ * <TR><TD class="indexkey" width=380> CB_SBGPP_RESET_DEASSERT --> 0x00010131 </TD></TR>\r
+ * </TABLE>\r
+ * @subsection CB_SBGPP_RESET_DEASSERT _Config Prepare for Configuration Data.\r
+ * @par\r
+ * Not necessary on current implementation\r
+ *\r
+ */\r
+#define CB_SBGPP_RESET_DEASSERT OEM_CALLBACK_BASE + 0x31\r
+\r
+#define IMC_FIRMWARE_FAIL OEM_CALLBACK_BASE + 0x40\r
+\r
+#define CFG_ADDR_PORT 0xCF8\r
+#define CFG_DATA_PORT 0xCFC\r
+\r
+#define ALINK_ACCESS_INDEX 0x0CD8\r
+#define ALINK_ACCESS_DATA ALINK_ACCESS_INDEX + 4\r
+\r
+/*------------------------------------------------------------------\r
+; I/O Base Address - Should be set by host BIOS\r
+;------------------------------------------------------------------ */\r
+#define DELAY_PORT 0x0E0\r
+\r
+/*------------------------------------------------------------------\r
+; Fuse ID and minor ID of efuse bits\r
+;------------------------------------------------------------------ */\r
+#define FUSE_ID_EFUSE_LOC 0x1F // efuse bits 248-255\r
+#define MINOR_ID_EFUSE_LOC 0x1E // efuse bits 240-247\r
+#define M1_D1_FUSE_ID 0x70\r
+#define M1_MINOR_ID 0x02\r
+\r
+/*------------------------------------------------------------------\r
+; DEBUG_PORT = 8-bit I/O Port Address for POST Code Display\r
+;------------------------------------------------------------------ */\r
+// ASIC VendorID and DeviceIDs\r
+#define AMD_SB_VID 0x1002\r
+#define SB_DEVICE_ID 0x4385 /* AMD ER SB800 */\r
+#define V_SB_SATA_VID AMD_SB_VID // dev 17 Func 0\r
+#define V_SB_SATA_DID 0x4390\r
+#define V_SB_SATA_AHCI_DID 0x4391\r
+#define V_SB_SATA_RAID_DID 0x4392\r
+#define V_SB_SATA_RAID5_DID 0x4393\r
+#define V_SB_USB_OHCI_VID AMD_SB_VID // dev 18 Func 0, dev 19 Func 0, dev 22 Func 0\r
+#define V_SB_USB_OHCI_DID 0x4397\r
+#define V_SB_USB_EHCI_VID AMD_SB_VID // dev 18 Func 2, dev 19 Func 2, dev 22 Func 2\r
+#define V_SB_USB_EHCI_DID 0x4396\r
+#define V_SB_SMBUS_VID AMD_SB_VID // dev 20 Func 0\r
+#define V_SB_SMBUS_DID 0x4385\r
+#define V_SB_IDE_VID AMD_SB_VID // dev 20 Func 1\r
+#define V_SB_IDE_DID 0x439C\r
+#define V_SB_AZALIA_VID AMD_SB_VID // dev 20 Func 2\r
+#define V_SB_AZALIA_DID 0x4383\r
+#define V_SB_LPC_VID AMD_SB_VID // dev 20 Func 3\r
+#define V_SB_LPC_DID 0x439D\r
+#define V_SB_PCIB_VID AMD_SB_VID // dev 20 Func 4\r
+#define V_SB_PCIB_DID 0x4384\r
+#define V_SB_USB_OHCIF_VID AMD_SB_VID // dev 20 Func 5\r
+#define V_SB_USB_OHCIF_DID 0x4399\r
+#define V_SB_NIC_VID 0x14E4 // dev 20 Func 6\r
+#define V_SB_NIC_DID 0x1699\r
+\r
+//Misc\r
+#define ACPI_SMI_CMD_PORT 0xB0\r
+#define ACPI_SMI_DATA_PORT 0xB1\r
+#define R_SB_ACPI_PM1_STATUS 0x00\r
+#define R_SB_ACPI_PM1_ENABLE 0x02\r
+#define R_SB_ACPI_PM_CONTROL 0x04\r
+#define R_SB_ACPI_EVENT_STATUS 0x20\r
+#define R_SB_ACPI_EVENT_ENABLE 0x24\r
+#define R_SB_PM_ACPI_PMA_CNT_BLK_LO 0x2C\r
+\r
+#define SATA_BUS_DEV_FUN ((0x11 << 3) + 0)\r
+#define SB_SATA1_BUS 0\r
+#define SB_SATA1_DEV 17\r
+#define SB_SATA1_FUNC 0\r
+\r
+#define FC_BUS_DEV_FUN ((0x11 << 3) + 1)\r
+#define USB1_OHCI_BUS_DEV_FUN ((0x12 << 3) + 0) // PORT 0-4\r
+#define SB_OHCI1_BUS 0\r
+#define SB_OHCI1_DEV 18\r
+#define SB_OHCI1_FUNC 0\r
+#define USB2_OHCI_BUS_DEV_FUN ((0x13 << 3) + 0) // PORT 5-9\r
+#define SB_OHCI2_BUS 0\r
+#define SB_OHCI2_DEV 19\r
+#define SB_OHCI2_FUNC 0\r
+#define USB3_OHCI_BUS_DEV_FUN ((0x16 << 3) + 0) // PORT 10-13\r
+#define SB_OHCI3_BUS 0\r
+#define SB_OHCI3_DEV 22\r
+#define SB_OHCI3_FUNC 0\r
+#define USB1_EHCI_BUS_DEV_FUN ((0x12 << 3) + 2) // PORT 0-4\r
+#define SB_EHCI1_BUS 0\r
+#define SB_EHCI1_DEV 18\r
+#define SB_EHCI1_FUNC 2\r
+#define USB2_EHCI_BUS_DEV_FUN ((0x13 << 3) + 2) // PORT 5-9\r
+#define SB_EHCI2_BUS 0\r
+#define SB_EHCI2_DEV 19\r
+#define SB_EHCI2_FUNC 2\r
+#define USB3_EHCI_BUS_DEV_FUN ((0x16 << 3) + 2) // PORT 10-13\r
+#define SB_EHCI3_BUS 0\r
+#define SB_EHCI3_DEV 22\r
+#define SB_EHCI3_FUNC 2\r
+\r
+#define SMBUS_BUS_DEV_FUN ((0x14 << 3) + 0)\r
+#define SB_ISA_BUS 0\r
+#define SB_ISA_DEV 20\r
+#define SB_ISA_FUNC 0\r
+#define IDE_BUS_DEV_FUN ((0x14 << 3) + 1)\r
+#define SB_IDE_BUS 0\r
+#define SB_IDE_DEV 20\r
+#define SB_IDE_FUNC 1\r
+#define AZALIA_BUS_DEV_FUN ((0x14 << 3) + 2)\r
+#define SB_AZALIA_BUS 0\r
+#define SB_AZALIA_DEV 20\r
+#define SB_AZALIA_FUNC 2\r
+#define LPC_BUS_DEV_FUN ((0x14 << 3) + 3)\r
+#define SB_LPC_BUS 0\r
+#define SB_LPC_DEV 20\r
+#define SB_LPC_FUNC 3\r
+#define PCIB_BUS_DEV_FUN ((0x14 << 3) + 4) // P2P in SB700\r
+#define SB_PCI_BUS 0\r
+#define SB_PCI_DEV 20\r
+#define SB_PCI_FUNC 4\r
+#define USB4_OHCI_BUS_DEV_FUN ((0x14 << 3) + 5) // PORT FL0 - FL1\r
+#define SB_OHCI4_BUS 0\r
+#define SB_OHCI4_DEV 20\r
+#define SB_OHCI4_FUNC 5\r
+//Gigabyte Ethernet Controller\r
+#define GEC_BUS_DEV_FUN ((0x14 << 3) + 6)\r
+#define SB_GBEC_BUS 0\r
+#define SB_GBEC_DEV 20\r
+#define SB_GBEC_FUNC 6\r
+\r
+#define SB_GPP_BUS 0\r
+#define SB_GPP_DEV 21\r
+#define SB_GPP_FUNC 0\r
+#define GPP0_BUS_DEV_FUN ((0x15 << 3) + 0) // GPP P2P bridge PORT0\r
+#define GPP1_BUS_DEV_FUN ((0x15 << 3) + 1) // GPP P2P bridge PORT1\r
+#define GPP2_BUS_DEV_FUN ((0x15 << 3) + 2) // GPP P2P bridge PORT2\r
+#define GPP3_BUS_DEV_FUN ((0x15 << 3) + 3) // GPP P2P bridge PORT3\r
+\r
+#define ACPI_MMIO_BASE 0xFED80000\r
+#define SB_CFG_BASE 0x000 // DWORD\r
+#define GPIO_BASE 0x100 // BYTE\r
+#define SMI_BASE 0x200 // DWORD\r
+#define PMIO_BASE 0x300 // DWORD\r
+#define PMIO2_BASE 0x400 // BYTE\r
+#define BIOS_RAM_BASE 0x500 // BYTE\r
+#define CMOS_RAM_BASE 0x600 // BYTE\r
+#define CMOS_BASE 0x700 // BYTE\r
+#define ASF_BASE 0x900 // DWORD\r
+#define SMBUS_BASE 0xA00 // DWORD\r
+#define WATCHDOG_BASE 0xB00 // ??\r
+#define HPET_BASE 0xC00 // DWORD\r
+#define IOMUX_BASE 0xD00 // BYTE\r
+#define MISC_BASE 0xE00\r
+\r
+#define GPP_EFUSE_LOCATION 0x14 // bit 160\r
+#define GPP_GEN2_EFUSE_BIT BIT0\r
+\r
+// RegSpace field (AB_INDEX[31:29]\r
+#define AXINDC 0 // AXINDC\r
+#define AXINDP 2 // AXINDP\r
+#define ABCFG 6 // ABCFG\r
+#define AXCFG 4 // AXCFG\r
+#define RCINDXC 1 // PCIEIND\r
+#define RCINDXP 3 // PCIEIND_P\r
+\r
+#define SBTEMP_BUS 8\r
+#define GPP_DEV_NUM 21 //?? Code style different\r
+#define MAX_GPP_PORTS 4\r
+#ifndef TRUE\r
+ #define TRUE 1\r
+#endif\r
+#ifndef FALSE\r
+ #define FALSE 0\r
+#endif\r
+//\r
+// ABCFG Registers\r
+//\r
+#define SB_ABCFG_REG00 0x00 // VENDOR ID\r
+#define SB_ABCFG_REG08 0x08 // REVISION ID\r
+#define SB_ABCFG_REG40 0x40 // BL_EVENTCNT0LO\r
+#define SB_ABCFG_REG44 0x44 // BL_EVENTCNT1LO\r
+#define SB_ABCFG_REG48 0x48 // BL_EVENTCNTSEL\r
+#define SB_ABCFG_REG4A 0x4A // BL_EVENTCNT0HI\r
+#define SB_ABCFG_REG4B 0x4B // BL_EVENTCNT1HI\r
+#define SB_ABCFG_REG4C 0x4C // BL_EVENTCNTCTL\r
+#define SB_ABCFG_REG50 0x50 // MISCCTL_50\r
+#define SB_ABCFG_REG54 0x54 // MISCCTL_54\r
+#define SB_ABCFG_REG58 0x58 // BL RAB CONTROL\r
+\r
+#define SB_ABCFG_REG60 0x60 // LINKWIDTH_CTL\r
+#define SB_ABCFG_REG64 0x64 // LINKWIDTH_UP_INTERVAL\r
+#define SB_ABCFG_REG68 0x68 // LINKWIDTH_DN_INVERVAL\r
+#define SB_ABCFG_REG6C 0x6C // LINKWIDTH_UPSTREAM_DWORDS\r
+#define SB_ABCFG_REG70 0x70 // LINKWIDTH_DOWNSTREAM_DWORDS\r
+#define SB_ABCFG_REG74 0x74 // LINKWIDTH_THRESHOLD_INCREASE\r
+#define SB_ABCFG_REG78 0x78 // LINKWIDTH_THRESHOLD_DECREASE\r
+\r
+#define SB_ABCFG_REG80 0x80 // BL DMA PREFETCH CONTROL\r
+#define SB_ABCFG_REG88 0x88 //\r
+#define SB_ABCFG_REG90 0x90 // BIF CONTROL 0\r
+#define SB_ABCFG_REG94 0x94 // MSI CONTROL\r
+#define SB_ABCFG_REG98 0x98 // BIF CONTROL 1\r
+#define SB_ABCFG_REG9C 0x9C // MISCCTL_9C\r
+#define SB_ABCFG_REGA0 0xA0 // BIF PHY CONTROL ENABLE\r
+#define SB_ABCFG_REGA4 0xA4 // BIF PHY CONTROL A4\r
+#define SB_ABCFG_REGA8 0xA8 // BIF PHY CONTROL A8\r
+#define SB_ABCFG_REGB0 0xB0 // HYPERFLASH-PCIE PORT MAPPING\r
+#define SB_ABCFG_REGC0 0xC0 // PCIE_GPP_ENABLE\r
+#define SB_ABCFG_REGC4 0xC4 // PCIE_P2P_INT_MAP\r
+#define SB_ABCFG_REGD0 0xD0 // MCTP_VDM_TX_FIFO_DATA\r
+#define SB_ABCFG_REGD4 0xD4 // MCTP_VMD_TX_CONTROL\r
+#define SB_ABCFG_REGE0 0xE0 // MCTP_VDM_RX_FIFO_DATA\r
+#define SB_ABCFG_REGE4 0xE4 // MCTP_VDM_RX_FIFO_STATUS\r
+#define SB_ABCFG_REGEC 0xEC // MCTP_VDM_CONTROL\r
+#define SB_ABCFG_REGF0 0xF0 // GPP_UPSTREAM_CONTROL\r
+#define SB_ABCFG_REGFC 0xFC // SB_TRAP_CONTROL\r
+#define SB_ABCFG_REG100 0x100 // SB_TRAP0_ADDRL\r
+#define SB_ABCFG_REG104 0x104 // SB_TRAP0_ADDRH\r
+#define SB_ABCFG_REG108 0x108 // SB_TRAP0_CMD\r
+#define SB_ABCFG_REG10C 0x10C // SB_TRAP1_DATA\r
+#define SB_ABCFG_REG110 0x110 // SB_TRAP1_ADDRL\r
+#define SB_ABCFG_REG114 0x114 // SB_TRAP1_ADDRH\r
+#define SB_ABCFG_REG118 0x118 // SB_TRAP1_CMD\r
+#define SB_ABCFG_REG11C 0x11C // SB_TRAP1_DATA\r
+#define SB_ABCFG_REG120 0x120 // SB_TRAP2_ADDRL\r
+#define SB_ABCFG_REG124 0x124 // SB_TRAP2_ADDRH\r
+#define SB_ABCFG_REG128 0x128 // SB_TRAP2_CMD\r
+#define SB_ABCFG_REG12C 0x12C // SB_TRAP2_DATA\r
+#define SB_ABCFG_REG130 0x130 // SB_TRAP3_ADDRL\r
+#define SB_ABCFG_REG134 0x134 // SB_TRAP3_ADDRH\r
+#define SB_ABCFG_REG138 0x138 // SB_TRAP3_CMD\r
+#define SB_ABCFG_REG13C 0x13C // SB_TRAP3_DATA\r
+#define SB_ABCFG_REG300 0x300 // MCTP_VDM_RX_SMI_CONTROL\r
+#define SB_ABCFG_REG310 0x310 // BIF_GPP_STRAP_SYSTEM_0\r
+#define SB_ABCFG_REG314 0x314 // BIF_GPP_STRAP_SYSTEM_1\r
+#define SB_ABCFG_REG31C 0x31C // BIF_GPP_STRAP_LINK_CONTROL_0\r
+#define SB_ABCFG_REG320 0x320 // BIF_GPP_STRAP_LINK_CONTROL_LANE_A\r
+#define SB_ABCFG_REG324 0x324 // BIF_GPP_STRAP_LINK_CONTROL_LANE_B\r
+#define SB_ABCFG_REG328 0x328 // BIF_GPP_STRAP_LINK_CONTROL_LANE_C\r
+#define SB_ABCFG_REG32C 0x32C // BIF_GPP_STRAP_LINK_CONTROL_LANE_D\r
+#define SB_ABCFG_REG330 0x330 // BIF_GPP_STRAP_BIF_0\r
+#define SB_ABCFG_REG334 0x334 // BIF_GPP_STRAP_BIF_1\r
+#define SB_ABCFG_REG338 0x338 // BIF_GPP_STRAP_BIF_2\r
+#define SB_ABCFG_REG340 0x340 // BIF_GPP_STRAP_BIF_LANE_A\r
+#define SB_ABCFG_REG344 0x344 // BIF_GPP_STRAP_BIF_LANE_B\r
+#define SB_ABCFG_REG348 0x348 // BIF_GPP_STRAP_BIF_LANE_C\r
+#define SB_ABCFG_REG34C 0x34C // BIF_GPP_STRAP_BIF_LANE_D\r
+#define SB_ABCFG_REG350 0x350 // BIF_GPP_STRAP_PHY_LOGICAL _0\r
+#define SB_ABCFG_REG354 0x354 // BIF_GPP_STRAP_PHY_LOGICAL _1\r
+#define SB_ABCFG_REG404 0x404 // GPP0_SHADOW_COMMAND\r
+#define SB_ABCFG_REG418 0x418 // GPP0_SHADOW_BUS_NUMBER\r
+#define SB_ABCFG_REG41C 0x41C // GPP0_SHADOW_IO_LIMIT_BASE\r
+#define SB_ABCFG_REG420 0x420 // GPP0_SHADOW_MEM_LIMIT_BASE\r
+#define SB_ABCFG_REG424 0x424 // GPP0_SHADOW_PREF_MEM_LIMIT_BASE\r
+#define SB_ABCFG_REG428 0x428 // GPP0_SHADOW_PREF_MEM_BASE_UPPER\r
+#define SB_ABCFG_REG42C 0x42C // GPP0_SHADOW_PREF_MEM_LIMIT_UPPER\r
+#define SB_ABCFG_REG430 0x430 // GPP0_SHADOW_IO_LIMIT_BASE_UPPER\r
+#define SB_ABCFG_REG43C 0x43C // GPP0_SHADOW_BRIDGE_CONTROL\r
+#define SB_ABCFG_REG444 0x444 // GPP1_SHADOW_COMMAND\r
+#define SB_ABCFG_REG458 0x458 // GPP1_SHADOW_BUS_NUMBER\r
+#define SB_ABCFG_REG45C 0x45C // GPP1_SHADOW_IO_LIMIT_BASE\r
+#define SB_ABCFG_REG460 0x460 // GPP1_SHADOW_MEM_LIMIT_BASE\r
+#define SB_ABCFG_REG464 0x464 // GPP1_SHADOW_PREF_MEM_LIMIT_BASE\r
+#define SB_ABCFG_REG468 0x468 // GPP1_SHADOW_PREF_MEM_BASE_UPPER\r
+#define SB_ABCFG_REG46C 0x46C // GPP1_SHADOW_PREF_MEM_LIMIT_UPPER\r
+#define SB_ABCFG_REG470 0x470 // GPP1_SHADOW_IO_LIMIT_BASE_UPPER\r
+#define SB_ABCFG_REG47C 0x47C // GPP1_SHADOW_BRIDGE_CONTROL\r
+#define SB_ABCFG_REG484 0x484 // GPP2_SHADOW_COMMAND\r
+#define SB_ABCFG_REG498 0x498 // GPP2_SHADOW_BUS_NUMBER\r
+#define SB_ABCFG_REG49C 0x49C // GPP2_SHADOW_IO_LIMIT_BASE\r
+#define SB_ABCFG_REG4A0 0x4A0 // GPP2_SHADOW_MEM_LIMIT_BASE\r
+#define SB_ABCFG_REG4A4 0x4A4 // GPP2_SHADOW_PREF_MEM_LIMIT_BASE\r
+#define SB_ABCFG_REG4A8 0x4A8 // GPP2_SHADOW_PREF_MEM_BASE_UPPER\r
+#define SB_ABCFG_REG4AC 0x4AC // GPP2_SHADOW_PREF_MEM_LIMIT_UPPER\r
+#define SB_ABCFG_REG4B0 0x4B0 // GPP2_SHADOW_IO_LIMIT_BASE_UPPER\r
+#define SB_ABCFG_REG4BC 0x4BC // GPP2_SHADOW_BRIDGE_CONTROL\r
+#define SB_ABCFG_REG4C4 0x4C4 // GPP3_SHADOW_COMMAND\r
+#define SB_ABCFG_REG4D8 0x4D8 // GPP3_SHADOW_BUS_NUMBER\r
+#define SB_ABCFG_REG4DC 0x4DC // GPP3_SHADOW_IO_LIMIT_BASE\r
+#define SB_ABCFG_REG4E0 0x4E0 // GPP3_SHADOW_MEM_LIMIT_BASE\r
+#define SB_ABCFG_REG4E4 0x4E4 // GPP3_SHADOW_PREF_MEM_LIMIT_BASE\r
+#define SB_ABCFG_REG4E8 0x4E8 // GPP3_SHADOW_PREF_MEM_BASE_UPPER\r
+#define SB_ABCFG_REG4EC 0x4EC // GPP3_SHADOW_PREF_MEM_LIMIT_UPPER\r
+#define SB_ABCFG_REG4F0 0x4F0 // GPP3_SHADOW_IO_LIMIT_BASE_UPPER\r
+#define SB_ABCFG_REG4FC 0x4FC // GPP3_SHADOW_BRIDGE_CONTROL\r
+#define SB_ABCFG_REG10040 0x10040 // AL_EVENTCNT0LO\r
+#define SB_ABCFG_REG10044 0x10044 // AL_EVENTCNT1LO\r
+#define SB_ABCFG_REG10048 0x10048 // AL_EVENTCNTSEL\r
+#define SB_ABCFG_REG1004A 0x1004A // AL_EVENTCNT0HI\r
+#define SB_ABCFG_REG1004B 0x1004B // AL_EVENTCNT1HI\r
+#define SB_ABCFG_REG1004C 0x1004C // AL_EVENTCNTCTL\r
+#define SB_ABCFG_REG10050 0x10050 // MISCCTL_10050\r
+#define SB_ABCFG_REG10054 0x10054 // AL_ARB_CTL\r
+#define SB_ABCFG_REG10056 0x10056 // AL_CLK_CTL\r
+#define SB_ABCFG_REG10058 0x10058 // AL RAB CONTROL\r
+#define SB_ABCFG_REG1005C 0x1005C // AL MLT CONTROL\r
+#define SB_ABCFG_REG10060 0x10060 // AL DMA PREFETCH ENABLE\r
+#define SB_ABCFG_REG10064 0x10064 // AL DMA PREFETCH FLUSH CONTROL\r
+#define SB_ABCFG_REG10068 0x10068 // AL PREFETCH LIMIT\r
+#define SB_ABCFG_REG1006C 0x1006C // AL DMA PREFETCH CONTROL\r
+#define SB_ABCFG_REG10070 0x10070 // MISCCTL_10070\r
+#define SB_ABCFG_REG10080 0x10080 // CLKMUXSTATUS\r
+#define SB_ABCFG_REG10090 0x10090 // BIF CONTROL 0\r
+#define SB_ABCFG_REG1009C 0x1009C // MISCCTL_1009C\r
+\r
+//\r
+// RCINDX_P Registers\r
+//\r
+#define SB_RCINDXP_REG01 0x01 | RCINDXP << 29 // PCIEP_SCRATCH\r
+#define SB_RCINDXP_REG10 0x10 | RCINDXP << 29 //\r
+#define SB_RCINDXP_REG20 0x20 | RCINDXP << 29 // PCIE_TX_CNTL\r
+#define SB_RCINDXP_REG50 0x50 | RCINDXP << 29 // PCIE_P_PORT_LANE_STATUS\r
+#define SB_RCINDXP_REG70 0x70 | RCINDXP << 29 // PCIE_RX_CNTL\r
+#define SB_RCINDXP_REGA0 0xA0 | RCINDXP << 29 // PCIE_LC_CNTL\r
+#define SB_RCINDXP_REGA1 0xA1 | RCINDXP << 29 // PCIE_LC_TRAINING_CNTL\r
+#define SB_RCINDXP_REGA2 0xA2 | RCINDXP << 29 //\r
+#define SB_RCINDXP_REGA4 0xA4 | RCINDXP << 29 //\r
+#define SB_RCINDXP_REGA5 0xA5 | RCINDXP << 29 // PCIE_LC_STATE0\r
+#define SB_RCINDXP_REGC0 0xC0 | RCINDXP << 29 //\r
+\r
+//\r
+// RCINDX_C Registers\r
+//\r
+#define SB_RCINDXC_REG02 0x02 | RCINDXC << 29 // PCIE_HW_DEBUG\r
+#define SB_RCINDXC_REG10 0x10 | RCINDXC << 29 // PCIE_CNTL\r
+#define SB_RCINDXC_REGC1 0xC1 | RCINDXC << 29 //\r
+\r
+//\r
+// AXINDC Registers\r
+//\r
+#define SB_AX_INDXC_REG02 0x02 // PCIEP_HW_DEBUG\r
+#define SB_AX_INDXC_REG10 0x10\r
+#define SB_AX_INDXC_REG30 0x30\r
+#define SB_AX_DATAC_REG34 0x34\r
+#define SB_AX_INDXP_REG38 0x38\r
+#define SB_AX_DATAP_REG3C 0x3C\r
+#define SB_AX_INDXC_REG40 0x40 | AXINDC << 29\r
+#define SB_AX_INDXC_REGA4 0xA4 | AXINDC << 29\r
+\r
+#define SB_AX_INDXP_REGA0 0xA0 | AXINDP << 29\r
+#define SB_AX_INDXP_REGA4 0xA4 | AXINDP << 29\r
+#define SB_AX_INDXP_REGB1 0xB1 | AXINDP << 29\r
+\r
+#define SB_AX_CFG_REG88 0x88 | AXCFG << 29\r
+\r
+#define AX_INDXC 0\r
+#define AX_INDXP 1\r
+#define SB_AB_REG04 0x04\r
+#define SB_AB_REG40 0x40\r
+\r
+#define RC_INDXC_REG40 0x40 | RCINDXC << 29\r
+#define RC_INDXC_REG65 0x65 | RCINDXC << 29\r
+\r
+//\r
+// SATA Device 0x4390 (IDE)\r
+// 0x4391 (AHCI)\r
+// 0x4392 (AHCI/RAID Promise with RAID driver)\r
+// 0x4393 (RAID5)\r
+// 0x4394/0x4395 (SATA HyperFlash OneNand support/SATA HyperFlash-PCIe support)\r
+// Device 17 (0x11) Func 0\r
+//\r
+//Sata Controller Mode\r
+#define NATIVE_IDE_MODE 0\r
+#define RAID_MODE 1\r
+#define AHCI_MODE 2\r
+#define LEGACY_IDE_MODE 3\r
+#define IDE_TO_AHCI_MODE 4\r
+#define AHCI_MODE_4394 5\r
+#define IDE_TO_AHCI_MODE_4394 6\r
+\r
+//Sata Port Configuration\r
+#define SIX_PORTS 0\r
+#define FOUR_PORTS 1\r
+\r
+#define SATA_EFUSE_LOCATION 0x10 // EFUSE bit 133\r
+#define SATA_FIS_BASE_EFUSE_LOC 0x15 // EFUSE bit 169\r
+#define SATA_EFUSE_BIT 0x20 //\r
+#define SB_SATA_REG00 0x000 // Vendor ID - R- 16 bits\r
+#define SB_SATA_REG02 0x002 // Device ID - RW -16 bits\r
+#define SB_SATA_REG04 0x004 // PCI Command - RW - 16 bits\r
+#define SB_SATA_REG06 0x006 // PCI Status - RW - 16 bits\r
+#define SB_SATA_REG08 0x008 // Revision ID/PCI Class Code - R - 32 bits - Offset: 08\r
+#define SB_SATA_REG0C 0x00C // Cache Line Size - R/W - 8bits\r
+#define SB_SATA_REG0D 0x00D // Latency Timer - RW - 8 bits\r
+#define SB_SATA_REG0E 0x00E // Header Type - R - 8 bits\r
+#define SB_SATA_REG0F 0x00F // BIST - R - 8 bits\r
+#define SB_SATA_REG10 0x010 // Base Address Register 0 - RW - 32 bits\r
+#define SB_SATA_REG14 0x014 // Base Address Register 1 - RW- 32 bits\r
+#define SB_SATA_REG18 0x018 // Base Address Register 2 - RW - 32 bits\r
+#define SB_SATA_REG1C 0x01C // Base Address Register 3 - RW - 32 bits\r
+#define SB_SATA_REG20 0x020 // Base Address Register 4 - RW - 32 bits\r
+#define SB_SATA_REG24 0x024 // Base Address Register 5 - RW - 32 bits\r
+#define SB_SATA_REG2C 0x02C // Subsystem Vendor ID - R - 16 bits\r
+#define SB_SATA_REG2D 0x02D // Subsystem ID - R - 16 bits\r
+#define SB_SATA_REG30 0x030 // Expansion ROM Base Address - 32 bits\r
+#define SB_SATA_REG34 0x034 // Capabilities Pointer - R - 32 bits\r
+#define SB_SATA_REG3C 0x03C // Interrupt Line - RW - 8 bits\r
+#define SB_SATA_REG3D 0x03D // Interrupt Pin - R - 8 bits\r
+#define SB_SATA_REG3E 0x03E // Min Grant - R - 8 bits\r
+#define SB_SATA_REG3F 0x03F // Max Latency - R - 8 bits\r
+#define SB_SATA_REG40 0x040 // Configuration - RW - 32 bits\r
+#define SB_SATA_REG44 0x044 // Software Data Register - RW - 32 bits\r
+#define SB_SATA_REG48 0x048\r
+#define SB_SATA_REG50 0x050 // Message Capability - R - 16 bits\r
+#define SB_SATA_REG52 0x052 // Message Control - R/W - 16 bits\r
+#define SB_SATA_REG54 0x054 // Message Address - R/W - 32 bits\r
+#define SB_SATA_REG58 0x058 // Message Data - R/W - 16 bits\r
+#define SB_SATA_REG5C 0x05C // RAMBIST Control Register - R/W - 8 bits\r
+#define SB_SATA_REG5D 0x05D // RAMBIST Status0 Register - R - 8 bits\r
+#define SB_SATA_REG5E 0x05E // RAMBIST Status1 Register - R - 8 bits\r
+#define SB_SATA_REG60 0x060 // Power Management Capabilities - R - 32 bits\r
+#define SB_SATA_REG64 0x064 // Power Management Control + Status - RW - 32 bits\r
+#define SB_SATA_REG68 0x068 // MSI Program - R/W - 8 bits\r
+#define SB_SATA_REG69 0x069 // PCI Burst Timer - R/W - 8 bits\r
+#define SB_SATA_REG70 0x070 // PCI Bus Master - IDE0 - RW - 32 bits\r
+#define SB_SATA_REG74 0x074 // PRD Table Address - IDE0 - RW - 32 bits\r
+#define SB_SATA_REG78 0x078 // PCI Bus Master - IDE1 - RW - 32 bits\r
+#define SB_SATA_REG7C 0x07C // PRD Table Address - IDE1 - RW - 32 bits\r
+#define SB_SATA_REG80 0x080 // Data Transfer Mode - IDE0 - RW - 32 bits\r
+#define SB_SATA_REG84 0x084 // Data Transfer Mode - IDE1 - RW - 32 bits\r
+#define SB_SATA_REG86 0x086 // PY Global Control\r
+#define SB_SATA_REG87 0x087\r
+#define SB_SATA_REG88 0x088 // PHY Port0 Control - Port0 PY fine tune (0:23)\r
+#define SB_SATA_REG8A 0x08A\r
+#define SB_SATA_REG8C 0x08C // PHY Port1 Control - Port0 PY fine tune (0:23)\r
+#define SB_SATA_REG8E 0x08E\r
+#define SB_SATA_REG90 0x090 // PHY Port2 Control - Port0 PY fine tune (0:23)\r
+#define SB_SATA_REG92 0x092\r
+#define SB_SATA_REG94 0x094 // PHY Port3 Control - Port0 PY fine tune (0:23)\r
+#define SB_SATA_REG96 0x096\r
+#define SB_SATA_REG98 0x098 // EEPROM Memory Address - Command + Status - RW - 32 bits\r
+#define SB_SATA_REG9C 0x09C // EEPROM Memory Data - RW - 32 bits\r
+#define SB_SATA_REGA0 0x0A0 //\r
+#define SB_SATA_REGA4 0x0A4 //\r
+#define SB_SATA_REGA5 0x0A5 //;\r
+#define SB_SATA_REGA8 0x0A8 //\r
+#define SB_SATA_REGAD 0x0AD //;\r
+#define SB_SATA_REGB0 0x0B0 // IDE1 Task File Configuration + Status - RW - 32 bits\r
+#define SB_SATA_REGB5 0x0B5 //;\r
+#define SB_SATA_REGBD 0x0BD //;\r
+#define SB_SATA_REGC0 0x0C0 // BA5 Indirect Address - RW - 32 bits\r
+#define SB_SATA_REGC4 0x0C4 // BA5 Indirect Access - RW - 32 bits\r
+\r
+#define SB_SATA_BAR5_REG00 0x000 // PCI Bus Master - IDE0 - RW - 32 bits\r
+#define SB_SATA_BAR5_REG04 0x004 // PRD Table Address - IDE0 - RW - 32 bits\r
+#define SB_SATA_BAR5_REG08 0x008 // PCI Bus Master - IDE1 - RW - 32 bits\r
+#define SB_SATA_BAR5_REG0C 0x00C // PRD Table Address - IDE1 - RW - 32 bits\r
+#define SB_SATA_BAR5_REG10 0x010 // PCI Bus Master2 - IDE0 - RW - 32 bits\r
+#define SB_SATA_BAR5_REG18 0x018 // PCI Bus Master2 - IDE1 - RW - 32 bits\r
+#define SB_SATA_BAR5_REG20 0x020 // PRD Address - IDE0 - RW - 32 bits\r
+#define SB_SATA_BAR5_REG24 0x024 // PCI Bus Master Byte Count - IDE0- RW - 32 bits\r
+#define SB_SATA_BAR5_REG28 0x028 // PRD Address - IDE1 - RW - 32 bits\r
+#define SB_SATA_BAR5_REG2C 0x02C // PCI Bus Master Byte Count - IDE1 - RW - 32 bits\r
+#define SB_SATA_BAR5_REG40 0x040 // FIFO Valid Byte Count and Control - IDE0 - RW - 32 bits\r
+#define SB_SATA_BAR5_REG44 0x044 // FIFO Valid Byte Count and Control - IDE1 - RW - 32 bits\r
+#define SB_SATA_BAR5_REG48 0x048 // System Configuration Status - Command - RW - 32 bits\r
+#define SB_SATA_BAR5_REG4C 0x04C // System Software Data Register - RW - 32 bits\r
+#define SB_SATA_BAR5_REG50 0x050 // FLAS Memory Address - Command + Status - RW - 32 bits\r
+#define SB_SATA_BAR5_REG54 0x054 // FLAS Memory Data - RW - 32 bits\r
+#define SB_SATA_BAR5_REG58 0x058 // EEPROM Memory Address - Command + Status - RW - 32 bits\r
+#define SB_SATA_BAR5_REG5C 0x05C // EEPROM Memory Data - RW - 32 bits\r
+#define SB_SATA_BAR5_REG60 0x060 // FIFO Port - IDE0 - RW - 32 bits\r
+#define SB_SATA_BAR5_REG68 0x068 // FIFO Pointers1- IDE0 - RW - 32 bits\r
+#define SB_SATA_BAR5_REG6C 0x06C // FIFO Pointers2- IDE0 - RW - 32 bits\r
+#define SB_SATA_BAR5_REG70 0x070 // FIFO Port - IDE1- RW - 32 bits\r
+#define SB_SATA_BAR5_REG78 0x078 // FIFO Pointers1- IDE1- RW - 32 bits\r
+#define SB_SATA_BAR5_REG7C 0x07C // FIFO Pointers2- IDE1- RW - 32 bits\r
+#define SB_SATA_BAR5_REG80 0x080 // IDE0 Task File Register 0- RW - 32 bits\r
+#define SB_SATA_BAR5_REG84 0x084 // IDE0 Task File Register 1- RW - 32 bits\r
+#define SB_SATA_BAR5_REG88 0x088 // IDE0 Task File Register 2- RW - 32 bits\r
+#define SB_SATA_BAR5_REG8C 0x08C // IDE0 Read Data - RW - 32 bits\r
+#define SB_SATA_BAR5_REG90 0x090 // IDE0 Task File Register 0 - Command Buffering - RW - 32 bits\r
+#define SB_SATA_BAR5_REG94 0x094 // IDE0 Task File Register 1 - Command Buffering - RW - 32 bits\r
+#define SB_SATA_BAR5_REG9C 0x09C // IDE0 Virtual DMA/PIO Read Byte Count - RW - 32 bits\r
+#define SB_SATA_BAR5_REGA0 0x0A0 // IDE0 Task File Configuration + Status - RW - 32 bits\r
+#define SB_SATA_BAR5_REGB4 0x0B4 // Data Transfer Mode -IDE0 - RW - 32 bits\r
+#define SB_SATA_BAR5_REGC0 0x0C0 // IDE1 Task File Register 0 - RW - 32 bits\r
+#define SB_SATA_BAR5_REGC4 0x0C4 // IDE1 Task File Register 1 - RW - 32 bits\r
+#define SB_SATA_BAR5_REGC8 0x0C8 // IDE1 Task File Register 2 - RW - 32 bits\r
+#define SB_SATA_BAR5_REGCC 0x0CC // Read/Write Data - RW - 32 bits\r
+#define SB_SATA_BAR5_REGD0 0x0D0 // IDE1 Task File Register 0 - Command Buffering - RW - 32 bits\r
+#define SB_SATA_BAR5_REGD4 0x0D4 // IDE1 Task File Register 1 - Command Buffering - RW - 32 bits\r
+#define SB_SATA_BAR5_REGDC 0x0DC // IDE1 Virtual DMA/PIO Read Byte Count - RW - 32 bits\r
+#define SB_SATA_BAR5_REGE0 0x0E0 // IDE1 Task File Configuration + Status - RW - 32 bits\r
+#define SB_SATA_BAR5_REGF4 0x0F4 // Data Transfer Mode - IDE1 - RW - 32 bits\r
+#define SB_SATA_BAR5_REGF8 0x0F8 // PORT Configuration\r
+#define SB_SATA_BAR5_REGFC 0x0FC\r
+#define SB_SATA_BAR5_REG100 0x0100 // Serial ATA SControl - RW - 32 bits - [Offset: 100h (channel 1) / 180\r
+#define SB_SATA_BAR5_REG104 0x0104 // Serial ATA Sstatus - RW - 32 bits - [Offset: 104h (channel 1) / 184h (cannel\r
+#define SB_SATA_BAR5_REG108 0x0108 // Serial ATA Serror - RW - 32 bits - [Offset: 108h (channel 1) / 188h (cannel\r
+#define SB_SATA_BAR5_REG10C 0x010C // Serial ATA Sdevice - RW - 32 bits - [Offset: 10Ch (channel 1) / 18Ch (cannel\r
+#define SB_SATA_BAR5_REG144 0x0144 // Serial ATA PY Configuration - RW - 32 bits\r
+#define SB_SATA_BAR5_REG148 0x0148 // SIEN - RW - 32 bits - [Offset: 148 (channel 1) / 1C8 (cannel 2)]\r
+#define SB_SATA_BAR5_REG14C 0x014C // SFISCfg - RW - 32 bits - [Offset: 14C (channel 1) / 1CC (cannel 2)]\r
+#define SB_SATA_BAR5_REG120 0x0120 //\r
+#define SB_SATA_BAR5_REG128 0x0128 // Port Serial ATA Status\r
+#define SB_SATA_BAR5_REG12C 0x012C // Port Serial ATA Control\r
+#define SB_SATA_BAR5_REG130 0x0130\r
+#define SB_SATA_BAR5_REG1B0 0x01B0\r
+#define SB_SATA_BAR5_REG230 0x0230\r
+#define SB_SATA_BAR5_REG2B0 0x02B0\r
+#define SB_SATA_BAR5_REG330 0x0330\r
+#define SB_SATA_BAR5_REG3B0 0x03B0\r
+\r
+//\r
+// FC Device 0x439B\r
+// Device 17 (0x11) Func 1\r
+//\r
+#define SB_FC_REG00 0x00 // Device/Vendor ID - R\r
+#define SB_FC_REG04 0x04 // Command - RW\r
+#define SB_FC_REG10 0x10 // BAR\r
+\r
+#define SB_FC_MMIO_REG70 0x070\r
+#define SB_FC_MMIO_REG200 0x200\r
+\r
+//\r
+// USB OHCI Device 0x4397\r
+// Device 18 (0x11)/Device 19 (0x12)/Device 22 (0x16) Func 0\r
+// Device 20 (0x14) Func 5 (FL)\r
+//\r
+#define SB_OHCI_REG00 0x00 // Device/Vendor ID - R (0x43971002)\r
+#define SB_OHCI_REG04 0x04 // Command - RW\r
+#define SB_OHCI_REG06 0x06 // Status - R\r
+#define SB_OHCI_REG08 0x08 // Revision ID/Class Code - R\r
+#define SB_OHCI_REG0C 0x0C // Miscellaneous - RW\r
+#define SB_OHCI_REG10 0x10 // Bar_OCI - RW\r
+#define SB_OHCI_REG2C 0x2C // Subsystem Vendor ID/ Subsystem ID - RW\r
+#define SB_OHCI_REG34 0x34 // Capability Pointer - R\r
+#define SB_OHCI_REG3C 0x3C // Interrupt Line - RW\r
+#define SB_OHCI_REG3D 0x3D // Interrupt Line - RW\r
+#define SB_OHCI_REG40 0x40 // Config Timers - RW\r
+#define SB_OHCI_REG42 0x42 // Port Disable Control - RW (800)\r
+#define SB_OHCI_REG46 0x46 // USB PHY Battery Charger - RW (800)\r
+#define SB_OHCI_REG48 0x48 // Port Force Reset - RW (800)\r
+#define SB_OHCI_REG4C 0x4C // MSI - RW (800)\r
+#define SB_OHCI_REG50 0x50 // Misc Control - RW\r
+#define SB_OHCI_REG51 0x51\r
+#define SB_OHCI_REG52 0x52\r
+#define SB_OHCI_REG58 0x58 // Over Current Control - RW\r
+#define SB_OHCI_REG5C 0x5C // Over Current Control - RW (800)??\r
+#define SB_OHCI_REG60 0x60 // Serial Bus Release Number - R (800)??\r
+#define SB_OHCI_REG68 0x68 // Over Current PME Enable - RW\r
+#define SB_OHCI_REG74 0x74 // Target Timeout Control - RW (800)\r
+#define SB_OHCI_REGD0 0x0D0 // MSI Control - RW\r
+#define SB_OHCI_REGD4 0x0D4 // MSI Address - RW\r
+#define SB_OHCI_REGD8 0x0D8 // MSI Data - RW\r
+#define SB_OHCI_REGE4 0x0E4 // HT MSI Support\r
+#define SB_OHCI_REGF0 0x0F0 // Function Level Reset Capability\r
+#define SB_OHCI_REGF4 0x0F4 // Function Level Reset Control\r
+\r
+#define SB_OHCI_BAR_REG00 0x00 // cRevision - R\r
+#define SB_OHCI_BAR_REG04 0x04 // cControl\r
+#define SB_OHCI_BAR_REG08 0x08 // cCommandStatus\r
+#define SB_OHCI_BAR_REG0C 0x0C // cInterruptStatus RW\r
+#define SB_OHCI_BAR_REG10 0x10 // cInterruptEnable\r
+#define SB_OHCI_BAR_REG14 0x14 // cInterruptDisable\r
+#define SB_OHCI_BAR_REG18 0x18 // HcCCA\r
+#define SB_OHCI_BAR_REG1C 0x1C // cPeriodCurrentED\r
+#define SB_OHCI_BAR_REG20 0x20 // HcControleadED\r
+#define SB_OHCI_BAR_REG24 0x24 // cControlCurrentED RW\r
+#define SB_OHCI_BAR_REG28 0x28 // HcBulkeadED\r
+#define SB_OHCI_BAR_REG2C 0x2C // cBulkCurrentED- RW\r
+#define SB_OHCI_BAR_REG30 0x30 // HcDoneead\r
+#define SB_OHCI_BAR_REG34 0x34 // cFmInterval\r
+#define SB_OHCI_BAR_REG38 0x38 // cFmRemaining\r
+#define SB_OHCI_BAR_REG3C 0x3C // cFmNumber\r
+#define SB_OHCI_BAR_REG40 0x40 // cPeriodicStart\r
+#define SB_OHCI_BAR_REG44 0x44 // HcLSThresold\r
+#define SB_OHCI_BAR_REG48 0x48 // HcRDescriptorA\r
+#define SB_OHCI_BAR_REG4C 0x4C // HcRDescriptorB\r
+#define SB_OHCI_BAR_REG50 0x50 // HcRStatus\r
+#define SB_OHCI_BAR_REG54 0x54 // HcRhPortStatus (800)\r
+#define SB_OHCI_BAR_REG58 0x58 // HcRhPortStatus NPD (800)\r
+#define SB_OHCI_BAR_REGF0 0xF0 // OHCI Loop Back feature Support (800)\r
+\r
+//\r
+// USB EHCI Device 0x4396\r
+// Device 18 (0x11)/Device 19 (0x12)/Device 22 (0x16) Func 2\r
+//\r
+#define SB_EHCI_REG00 0x00 // DEVICE/VENDOR ID - R\r
+#define SB_EHCI_REG04 0x04 // Command - RW\r
+#define SB_EHCI_REG06 0x06 // Status - R\r
+#define SB_EHCI_REG08 0x08 // Revision ID/Class Code - R\r
+#define SB_EHCI_REG0C 0x0C // Miscellaneous - RW\r
+#define SB_EHCI_REG10 0x10 // BAR - RW\r
+#define SB_EHCI_REG2C 0x2C // Subsystem ID/Subsystem Vendor ID - RW\r
+#define SB_EHCI_REG34 0x34 // Capability Pointer - R\r
+#define SB_EHCI_REG3C 0x3C // Interrupt Line - RW\r
+#define SB_EHCI_REG3D 0x3D // Interrupt Line - RW ??\r
+#define SB_EHCI_REG40 0x40 // Config Timers - RW ??\r
+#define SB_EHCI_REG4C 0x4C // MSI - RW\r
+#define SB_EHCI_REG50 0x50 // EHCI Misc Control - RW\r
+#define SB_EHCI_REG54 0x54 // EHCI Misc Control - RW\r
+#define SB_EHCI_REG60 0x60 // SBRN - R\r
+#define SB_EHCI_REG61 0x61 // FLADJ - RW\r
+#define SB_EHCI_REG62 0x62 // PORTWAKECAP - RW\r
+#define SB_EHCI_REGC0 0x0C0 // PME control - RW (800)\r
+#define SB_EHCI_REGC4 0x0C4 // PME Data /Status - RW (800)\r
+#define SB_EHCI_REGD0 0x0D0 // MSI Control - RW\r
+#define SB_EHCI_REGD4 0x0D4 // MSI Address - RW\r
+#define SB_EHCI_REGD8 0x0D8 // MSI Data - RW\r
+#define SB_EHCI_REGE4 0x0E4 // EHCI Debug Port Support - RW (800)\r
+#define SB_EHCI_REGF0 0x0F0 // Function Level Reset Capability - R (800)\r
+#define SB_EHCI_REGF4 0x0F4 // Function Level Reset Capability - R (800)\r
+\r
+#define SB_EHCI_BAR_REG00 0x00 // CAPLENGT - R\r
+#define SB_EHCI_BAR_REG02 0x002 // CIVERSION- R\r
+#define SB_EHCI_BAR_REG04 0x004 // CSPARAMS - R\r
+#define SB_EHCI_BAR_REG08 0x008 // CCPARAMS - R\r
+#define SB_EHCI_BAR_REG0C 0x00C // CSP-PORTROUTE - R\r
+\r
+#define SB_EHCI_BAR_REG20 0x020 // USBCMD - RW - 32 bits\r
+#define SB_EHCI_BAR_REG24 0x024 // USBSTS - RW - 32 bits\r
+#define SB_EHCI_BAR_REG28 0x028 // USBINTR -RW - 32 bits\r
+#define SB_EHCI_BAR_REG2C 0x02C // FRINDEX -RW - 32 bits\r
+#define SB_EHCI_BAR_REG30 0x030 // CTRLDSSEGMENT -RW - 32 bits\r
+#define SB_EHCI_BAR_REG34 0x034 // PERIODICLISTBASE -RW - 32 bits\r
+#define SB_EHCI_BAR_REG38 0x038 // ASYNCLISTADDR -RW - 32 bits\r
+#define SB_EHCI_BAR_REG60 0x060 // CONFIGFLAG -RW - 32 bits\r
+#define SB_EHCI_BAR_REG64 0x064 // PORTSC (1-N_PORTS) -RW - 32 bits\r
+#define SB_EHCI_BAR_REGA0 0x0A0 // DebugPort MISC Control - RW - 32 bits (800)\r
+#define SB_EHCI_BAR_REGA4 0x0A4 // Packet Buffer Threshold Values - RW - 32 bits\r
+#define SB_EHCI_BAR_REGA8 0x0A8 // USB PHY Status 0 - R\r
+#define SB_EHCI_BAR_REGAC 0x0AC // USB PHY Status 1 - R\r
+#define SB_EHCI_BAR_REGB0 0x0B0 // USB PHY Status 2 - R\r
+#define SB_EHCI_BAR_REGB4 0x0B4 // UTMI Control - RW (800)\r
+#define SB_EHCI_BAR_REGB8 0x0B8 // Loopback Test\r
+#define SB_EHCI_BAR_REGBC 0x0BC // EHCI MISC Control\r
+#define SB_EHCI_BAR_REGC0 0x0C0 // USB PHY Calibration\r
+#define SB_EHCI_BAR_REGC4 0x0C4 // USB Common PHY Control\r
+#define SB_EHCI_BAR_REGC8 0x0C8 // EHCI Debug Purpose\r
+#define SB_EHCI_BAR_REGCC 0x0CC // Ehci Spare 1 (800) **\r
+#define SB_EHCI_BAR_REG100 0x100 // USB debug port\r
+\r
+//\r
+// SB800 SB CFG device 0x4385\r
+// Device 20 (0x14) Func 0\r
+//\r
+#define SB_CFG_REG00 0x000 // VendorID - R\r
+#define SB_CFG_REG02 0x002 // DeviceID - R\r
+#define SB_CFG_REG04 0x004 // Command- RW\r
+#define SB_CFG_REG05 0x005 // Command- RW\r
+#define SB_CFG_REG06 0x006 // STATUS- RW\r
+#define SB_CFG_REG08 0x008 // Revision ID/Class Code- R\r
+#define SB_CFG_REG0A 0x00A //\r
+#define SB_CFG_REG0B 0x00B //\r
+#define SB_CFG_REG0C 0x00C // Cache Line Size- R\r
+#define SB_CFG_REG0D 0x00D // Latency Timer- R\r
+#define SB_CFG_REG0E 0x00E // Header Type- R\r
+#define SB_CFG_REG0F 0x00F // BIST- R\r
+#define SB_CFG_REG10 0x010 // Base Address 0- R\r
+#define SB_CFG_REG11 0x011 //;\r
+#define SB_CFG_REG12 0x012 //;\r
+#define SB_CFG_REG13 0x013 //;\r
+#define SB_CFG_REG14 0x014 // Base Address 1- R\r
+#define SB_CFG_REG18 0x018 // Base Address 2- R\r
+#define SB_CFG_REG1C 0x01C // Base Address 3- R\r
+#define SB_CFG_REG20 0x020 // Base Address 4- R\r
+#define SB_CFG_REG24 0x024 // Base Address 5- R\r
+#define SB_CFG_REG28 0x028 // Cardbus CIS Pointer- R\r
+#define SB_CFG_REG2C 0x02C // Subsystem Vendor ID- W\r
+#define SB_CFG_REG2E 0x02E // Subsystem ID- W\r
+#define SB_CFG_REG30 0x030 // Expansion ROM Base Address - R\r
+#define SB_CFG_REG34 0x034 // Capability Pointer - R (800) default changed as 0x00\r
+#define SB_CFG_REG3C 0x03C // Interrupt Line - R\r
+#define SB_CFG_REG3D 0x03D // Interrupt Pin - R\r
+#define SB_CFG_REG3E 0x03E // Min_Gnt - R\r
+#define SB_CFG_REG3F 0x03F // Max_Lat - R\r
+#define SB_CFG_REG90 0x090 // Smbus Base Address - R\r
+#define SB_CFG_REG9C 0x09C // SBResourceMMIO_BASE\r
+\r
+//\r
+// SB800 SATA IDE device 0x439C\r
+// Device 20 (0x14) Func 1\r
+//\r
+\r
+#define SB_IDE_REG00 0x00 // Vendor ID\r
+#define SB_IDE_REG02 0x02 // Device ID\r
+#define SB_IDE_REG04 0x04 // Command\r
+#define SB_IDE_REG06 0x06 // Status\r
+#define SB_IDE_REG08 0x08 // Revision ID/Class Code\r
+#define SB_IDE_REG09 0x09 // Class Code\r
+#define SB_IDE_REG2C 0x2C // Subsystem ID and Subsystem Vendor ID\r
+#define SB_IDE_REG34 0x34\r
+#define SB_IDE_REG40 0x40 // Configuration - RW - 32 bits\r
+#define SB_IDE_REG62 0x62 // IDE Internal Control\r
+#define SB_IDE_REG63 0x63 // IDE Internal Control\r
+//\r
+// SB800 AZALIA device 0x4383\r
+// Device 20 (0x14) Func 2\r
+//\r
+#define ATI_AZALIA_ExtBlk_Addr 0x0F8\r
+#define ATI_AZALIA_ExtBlk_DATA 0x0FC\r
+\r
+#define SB_AZ_REG00 0x00 // Vendor ID - R\r
+#define SB_AZ_REG02 0x02 // Device ID - R/W\r
+#define SB_AZ_REG04 0x04 // PCI Command\r
+#define SB_AZ_REG06 0x06 // PCI Status - R/W\r
+#define SB_AZ_REG08 0x08 // Revision ID\r
+#define SB_AZ_REG09 0x09 // Programming Interface\r
+#define SB_AZ_REG0A 0x0A // Sub Class Code\r
+#define SB_AZ_REG0B 0x0B // Base Class Code\r
+#define SB_AZ_REG0C 0x0C // Cache Line Size - R/W\r
+#define SB_AZ_REG0D 0x0D // Latency Timer\r
+#define SB_AZ_REG0E 0x0E // Header Type\r
+#define SB_AZ_REG0F 0x0F // BIST\r
+#define SB_AZ_REG10 0x10 // Lower Base Address Register\r
+#define SB_AZ_REG14 0x14 // Upper Base Address Register\r
+#define SB_AZ_REG2C 0x2C // Subsystem Vendor ID\r
+#define SB_AZ_REG2D 0x2D // Subsystem ID\r
+#define SB_AZ_REG34 0x34 // Capabilities Pointer\r
+#define SB_AZ_REG3C 0x3C // Interrupt Line\r
+#define SB_AZ_REG3D 0x3D // Interrupt Pin\r
+#define SB_AZ_REG3E 0x3E // Minimum Grant\r
+#define SB_AZ_REG3F 0x3F // Maximum Latency\r
+#define SB_AZ_REG40 0x40 // Misc Control 1\r
+#define SB_AZ_REG42 0x42 // Misc Control 2 Register\r
+#define SB_AZ_REG43 0x43 // Misc Control 3 Register\r
+#define SB_AZ_REG44 0x44 // Interrupt Pin Control Register\r
+#define SB_AZ_REG46 0x46 // Debug Control Register\r
+#define SB_AZ_REG4C 0x4C\r
+#define SB_AZ_REG50 0x50 // Power Management Capability ID\r
+#define SB_AZ_REG52 0x52 // Power Management Capabilities\r
+#define SB_AZ_REG54 0x54 // Power Management Control/Status\r
+#define SB_AZ_REG60 0x60 // MSI Capability ID\r
+#define SB_AZ_REG62 0x62 // MSI Message Control\r
+#define SB_AZ_REG64 0x64 // MSI Message Lower Address\r
+#define SB_AZ_REG68 0x68 // MSI Message Upper Address\r
+#define SB_AZ_REG6C 0x6C // MSI Message Data\r
+\r
+#define SB_AZ_BAR_REG00 0x00 // Global Capabilities - R\r
+#define SB_AZ_BAR_REG02 0x02 // Minor Version - R\r
+#define SB_AZ_BAR_REG03 0x03 // Major Version - R\r
+#define SB_AZ_BAR_REG04 0x04 // Output Payload Capability - R\r
+#define SB_AZ_BAR_REG06 0x06 // Input Payload Capability - R\r
+#define SB_AZ_BAR_REG08 0x08 // Global Control - R/W\r
+#define SB_AZ_BAR_REG0C 0x0C // Wake Enable - R/W\r
+#define SB_AZ_BAR_REG0E 0x0E // State Change Status - R/W\r
+#define SB_AZ_BAR_REG10 0x10 // Global Status - R/W\r
+#define SB_AZ_BAR_REG18 0x18 // Output Stream Payload Capability - R\r
+#define SB_AZ_BAR_REG1A 0x1A // Input Stream Payload Capability - R\r
+#define SB_AZ_BAR_REG20 0x20 // Interrupt Control - R/W\r
+#define SB_AZ_BAR_REG24 0x24 // Interrupt Status - R/W\r
+#define SB_AZ_BAR_REG30 0x30 // Wall Clock Counter - R\r
+#define SB_AZ_BAR_REG38 0x38 // Stream Synchronization - R/W\r
+#define SB_AZ_BAR_REG40 0x40 // CORB Lower Base Address - R/W\r
+#define SB_AZ_BAR_REG44 0x44 // CORB Upper Base Address - RW\r
+#define SB_AZ_BAR_REG48 0x48 // CORB Write Pointer - R/W\r
+#define SB_AZ_BAR_REG4A 0x4A // CORB Read Pointer - R/W\r
+#define SB_AZ_BAR_REG4C 0x4C // CORB Control - R/W\r
+#define SB_AZ_BAR_REG4D 0x4D // CORB Status - R/W\r
+#define SB_AZ_BAR_REG4E 0x4E // CORB Size - R/W\r
+#define SB_AZ_BAR_REG50 0x50 // RIRB Lower Base Address - RW\r
+#define SB_AZ_BAR_REG54 0x54 // RIRB Upper Address - RW\r
+#define SB_AZ_BAR_REG58 0x58 // RIRB Write Pointer - RW\r
+#define SB_AZ_BAR_REG5A 0x5A // RIRB Response Interrupt Count - R/W\r
+#define SB_AZ_BAR_REG5C 0x5C // RIRB Control - R/W\r
+#define SB_AZ_BAR_REG5D 0x5D // RIRB Status - R/W\r
+#define SB_AZ_BAR_REG5E 0x5E // RIRB Size - R/W\r
+#define SB_AZ_BAR_REG60 0x60 // Immediate Command Output Interface - R/W\r
+#define SB_AZ_BAR_REG64 0x64 // Immediate Command Input Interface - R/W\r
+#define SB_AZ_BAR_REG68 0x68 // Immediate Command Input Interface - R/W\r
+#define SB_AZ_BAR_REG70 0x70 // DMA Position Lower Base Address - R/W\r
+#define SB_AZ_BAR_REG74 0x74 // DMA Position Upper Base Address - R/W\r
+#define SB_AZ_BAR_REG2030 0x2030 // Wall Clock Counter Alias - R\r
+\r
+//\r
+// SB800 LPC Device 0x439D\r
+// Device 20 (0x14) Func 3\r
+//\r
+#define SB_LPC_REG00 0x00 // VID- R\r
+#define SB_LPC_REG02 0x02 // DID- R\r
+#define SB_LPC_REG04 0x04 // CMD- RW\r
+#define SB_LPC_REG06 0x06 // STATUS- RW\r
+#define SB_LPC_REG08 0x08 // Revision ID/Class Code - R\r
+#define SB_LPC_REG0C 0x0C // Cache Line Size - R\r
+#define SB_LPC_REG0D 0x0D // Latency Timer - R\r
+#define SB_LPC_REG0E 0x0E // Header Type - R\r
+#define SB_LPC_REG0F 0x0F // BIST- R\r
+#define SB_LPC_REG10 0x10 // Base Address Reg 0- RW*\r
+#define SB_LPC_REG2C 0x2C // Subsystem ID & Subsystem Vendor ID - Wo/Ro\r
+#define SB_LPC_REG34 0x34 // Capabilities Pointer - Ro\r
+#define SB_LPC_REG40 0x40 // PCI Control - RW\r
+#define SB_LPC_REG44 0x44 // IO Port Decode Enable Register 1- RW\r
+#define SB_LPC_REG45 0x45 // IO Port Decode Enable Register 2- RW\r
+#define SB_LPC_REG46 0x46 // IO Port Decode Enable Register 3- RW\r
+#define SB_LPC_REG47 0x47 // IO Port Decode Enable Register 4- RW\r
+#define SB_LPC_REG48 0x48 // IO/Mem Port Decode Enable Register 5- RW\r
+#define SB_LPC_REG49 0x49 // LPC Sync Timeout Count - RW\r
+#define SB_LPC_REG4A 0x4A // IO/Mem Port Decode Enable Register 6- RW\r
+#define SB_LPC_REG4C 0x4C // Memory Range Register - RW\r
+#define SB_LPC_REG50 0x50 // Rom Protect 0 - RW\r
+#define SB_LPC_REG54 0x54 // Rom Protect 1 - RW\r
+#define SB_LPC_REG58 0x58 // Rom Protect 2 - RW\r
+#define SB_LPC_REG5C 0x5C // Rom Protect 3 - RW\r
+#define SB_LPC_REG60 0x60 // PCI Memory Start Address of LPC Target Cycles -\r
+#define SB_LPC_REG62 0x62 // PCI Memory End Address of LPC Target Cycles -\r
+#define SB_LPC_REG64 0x64 // PCI IO base Address of Wide Generic Port - RW\r
+#define SB_LPC_REG65 0x65\r
+#define SB_LPC_REG66 0x66\r
+#define SB_LPC_REG67 0x67\r
+#define SB_LPC_REG68 0x68 // LPC ROM Address Range 1 (Start Address) - RW\r
+#define SB_LPC_REG69 0x69\r
+#define SB_LPC_REG6A 0x6A // LPC ROM Address Range 1 (End Address) - RW\r
+#define SB_LPC_REG6B 0x6B\r
+#define SB_LPC_REG6C 0x6C // LPC ROM Address Range 2 (Start Address)- RW\r
+#define SB_LPC_REG6D 0x6D\r
+#define SB_LPC_REG6E 0x6E // LPC ROM Address Range 2 (End Address) - RW\r
+#define SB_LPC_REG6F 0x6F\r
+#define SB_LPC_REG70 0x70 // Firmware ub Select - RW*\r
+#define SB_LPC_REG71 0x71\r
+#define SB_LPC_REG72 0x72\r
+#define SB_LPC_REG73 0x73\r
+#define SB_LPC_REG74 0x74 // Alternative Wide IO Range Enable- W/R\r
+#define SB_LPC_REG78 0x78 // Miscellaneous Control Bits- W/R\r
+#define SB_LPC_REG7C 0x7C // TPM (trusted plant form module) reg- W/R\r
+#define SB_LPC_REG9C 0x9C\r
+#define SB_LPC_REG80 0x80 // MSI Capability Register- R\r
+#define SB_LPC_REGA0 0x0A0 // SPI base address\r
+#define SB_LPC_REGA1 0x0A1 // SPI base address\r
+#define SB_LPC_REGA2 0x0A2 // SPI base address\r
+#define SB_LPC_REGA3 0x0A3 // SPI base address\r
+#define SB_LPC_REGA4 0x0A4\r
+#define SB_LPC_REGBA 0x0BA // EcControl\r
+#define SB_LPC_REGBB 0x0BB // HostControl\r
+\r
+//\r
+// SB800 PCIB 0x4384\r
+// Device 20 (0x14) Func 4\r
+//\r
+#define SB_PCIB_REG04 0x04 // Command\r
+#define SB_PCIB_REG0D 0x0D // Primary Master Latency Timer\r
+#define SB_PCIB_REG1B 0x1B // Secondary Latency Timer\r
+#define SB_PCIB_REG1C 0x1C // IO Base\r
+#define SB_PCIB_REG1D 0x1D // IO Limit\r
+#define SB_PCIB_REG40 0x40 // CPCTRL\r
+#define SB_PCIB_REG42 0x42 // CLKCTRL\r
+#define SB_PCIB_REG48 0x48 //\r
+#define SB_PCIB_REG4A 0x4A // PCICLK Enable Bits\r
+#define SB_PCIB_REG4B 0x4B // Misc Control\r
+#define SB_PCIB_REG4C 0x4C // AutoClockRun Control\r
+#define SB_PCIB_REG50 0x50 // Dual Address Cycle Enable and PCIB_CLK_Stop Override\r
+#define SB_PCIB_REG65 0x65 // Misc Control\r
+#define SB_PCIB_REG66 0x66 // Misc Control\r
+//\r
+// SB800 NIC 0x4384\r
+// Device 20 (0x14) Func 6 (Func5 OHCI FL device)\r
+//\r
+#define SB_GEC_REG04 0x04 // Command\r
+#define SB_GEC_REG10 0x10 // GEC BAR\r
+\r
+//\r
+// SB800 SB MMIO Base (SMI)\r
+// offset : 0x200\r
+//\r
+#define SB_SMI_REG00 0x00 // EventStatus\r
+#define SB_SMI_REG04 0x04 // EventEnable\r
+#define SB_SMI_REG08 0x08 // SciTrig\r
+#define SB_SMI_REG0C 0x0C // SciLevl\r
+#define SB_SMI_REG10 0x10 // SmiSciStatus\r
+#define SB_SMI_REG14 0x14 // SmiSciEn\r
+#define SB_SMI_REG18 0x18 // ForceSciEn\r
+#define SB_SMI_REG1C 0x1C // SciRwData\r
+#define SB_SMI_REG20 0x20 // SciS0En\r
+#define SB_SMI_Gevent0 0x40 // SciMap0\r
+#define SB_SMI_Gevent1 0x41 // SciMap1\r
+#define SB_SMI_Gevent2 0x42 // SciMap2\r
+#define SB_SMI_Gevent3 0x43 // SciMap3\r
+#define SB_SMI_Gevent4 0x44 // SciMap4\r
+#define SB_SMI_Gevent5 0x45 // SciMap5\r
+#define SB_SMI_Gevent6 0x46 // SciMap6\r
+#define SB_SMI_Gevent7 0x47 // SciMap7\r
+#define SB_SMI_Gevent8 0x48 // SciMap8\r
+#define SB_SMI_Gevent9 0x49 // SciMap9\r
+#define SB_SMI_Gevent10 0x4A // SciMap10\r
+#define SB_SMI_Gevent11 0x4B // SciMap11\r
+#define SB_SMI_Gevent12 0x4C // SciMap12\r
+#define SB_SMI_Gevent13 0x4D // SciMap13\r
+#define SB_SMI_Gevent14 0x4E // SciMap14\r
+#define SB_SMI_Gevent15 0x4F // SciMap15\r
+#define SB_SMI_Gevent16 0x50 // SciMap16\r
+#define SB_SMI_Gevent17 0x51 // SciMap17\r
+#define SB_SMI_Gevent18 0x52 // SciMap18\r
+#define SB_SMI_Gevent19 0x53 // SciMap19\r
+#define SB_SMI_Gevent20 0x54 // SciMap20\r
+#define SB_SMI_Gevent21 0x55 // SciMap21\r
+#define SB_SMI_Gevent22 0x56 // SciMap22\r
+#define SB_SMI_Gevent23 0x57 // SciMap23\r
+#define SB_SMI_Usbwakup0 0x58 // SciMap24\r
+#define SB_SMI_Usbwakup1 0x59 // SciMap25\r
+#define SB_SMI_Usbwakup2 0x5A // SciMap26\r
+#define SB_SMI_Usbwakup3 0x5B // SciMap27\r
+#define SB_SMI_SBGppPme0 0x5C // SciMap28\r
+#define SB_SMI_SBGppPme1 0x5D // SciMap29\r
+#define SB_SMI_SBGppPme2 0x5E // SciMap30\r
+#define SB_SMI_SBGppPme3 0x5F // SciMap31\r
+#define SB_SMI_SBGppHp0 0x60 // SciMap32\r
+#define SB_SMI_SBGppHp1 0x61 // SciMap33\r
+#define SB_SMI_SBGppHp2 0x62 // SciMap34\r
+#define SB_SMI_SBGppHp3 0x63 // SciMap35\r
+#define SB_SMI_AzaliaPme 0x64 // SciMap36\r
+#define SB_SMI_SataGevent0 0x65 // SciMap37\r
+#define SB_SMI_SataGevent1 0x66 // SciMap38\r
+#define SB_SMI_GecPme 0x67 // SciMap39\r
+#define SB_SMI_IMCGevent0 0x68 // SciMap40\r
+#define SB_SMI_IMCGevent1 0x69 // SciMap41\r
+#define SB_SMI_CIRPme 0x6A // SciMap42\r
+#define SB_SMI_WakePinGevent 0x6B // SciMap43\r
+#define SB_SMI_FanThGevent 0x6C // SciMap44 //FanThermalGevent\r
+#define SB_SMI_ASFMasterIntr 0x6D // SciMap45\r
+#define SB_SMI_ASFSlaveIntr 0x6E // SciMap46\r
+#define SB_SMI_SMBUS0 0x6F // SciMap47\r
+#define SB_SMI_TWARN 0x70 // SciMap48\r
+#define SB_SMI_TMI 0x71 // SciMap49 // TrafficMonitorIntr\r
+\r
+// Empty from 0x72-0x7F\r
+//#Define SB_SMI_REG7C 0x7F // SciMap63 ***\r
+\r
+#define SB_SMI_REG80 0x80 // SmiStatus0\r
+#define SB_SMI_REG84 0x84 // SmiStatus1\r
+#define SB_SMI_REG88 0x88 // SmiStatus2\r
+#define SB_SMI_REG8C 0x8C // SmiStatus3\r
+#define SB_SMI_REG90 0x90 // SmiStatus4\r
+#define SB_SMI_REG94 0x94 // SmiPointer\r
+#define SB_SMI_REG96 0x96 // SmiTimer\r
+#define SB_SMI_REG98 0x98 // SmiTrig\r
+#define SB_SMI_REG9C 0x9C // SmiTrig\r
+#define SB_SMI_REGA0 0xA0\r
+#define SB_SMI_REGA1 0xA1\r
+#define SB_SMI_REGA2 0xA2\r
+#define SB_SMI_REGA3 0xA3\r
+#define SB_SMI_REGA4 0xA4\r
+#define SB_SMI_REGA5 0xA5\r
+#define SB_SMI_REGA6 0xA6\r
+#define SB_SMI_REGA7 0xA7\r
+#define SB_SMI_REGA8 0xA8\r
+#define SB_SMI_REGA9 0xA9\r
+#define SB_SMI_REGAA 0xAA\r
+#define SB_SMI_REGAB 0xAB\r
+#define SB_SMI_REGAC 0xAC\r
+#define SB_SMI_REGAD 0xAD\r
+#define SB_SMI_REGAE 0xAE\r
+#define SB_SMI_REGAF 0xAF\r
+#define SB_SMI_REGB0 0xB0\r
+#define SB_SMI_REGB1 0xB1\r
+#define SB_SMI_REGB2 0xB2\r
+#define SB_SMI_REGB3 0xB3\r
+#define SB_SMI_REGB4 0xB4\r
+#define SB_SMI_REGB5 0xB5\r
+#define SB_SMI_REGB6 0xB6\r
+#define SB_SMI_REGB7 0xB7\r
+#define SB_SMI_REGB8 0xB8\r
+#define SB_SMI_REGB9 0xB9\r
+#define SB_SMI_REGBA 0xBA\r
+#define SB_SMI_REGBB 0xBB\r
+#define SB_SMI_REGBC 0xBC\r
+#define SB_SMI_REGBD 0xBD\r
+#define SB_SMI_REGBE 0xBE\r
+#define SB_SMI_REGBF 0xBF\r
+#define SB_SMI_REGC0 0xC0\r
+#define SB_SMI_REGC1 0xC1\r
+#define SB_SMI_REGC2 0xC2\r
+#define SB_SMI_REGC3 0xC3\r
+#define SB_SMI_REGC4 0xC4\r
+#define SB_SMI_REGC5 0xC5\r
+#define SB_SMI_REGC6 0xC6\r
+#define SB_SMI_REGC7 0xC7\r
+#define SB_SMI_REGC8 0xC8\r
+#define SB_SMI_REGCA 0xCA // IoTrapping1\r
+#define SB_SMI_REGCC 0xCC // IoTrapping2\r
+#define SB_SMI_REGCE 0xCE // IoTrapping3\r
+#define SB_SMI_REGD0 0xD0 // MemTrapping0\r
+#define SB_SMI_REGD4 0xD4 // MemRdOvrData0\r
+#define SB_SMI_REGD8 0xD8 // MemTrapping1\r
+#define SB_SMI_REGDC 0xDC // MemRdOvrData1\r
+#define SB_SMI_REGE0 0xE0 // MemTrapping2\r
+#define SB_SMI_REGE4 0xE4 // MemRdOvrData2\r
+#define SB_SMI_REGE8 0xE8 // MemTrapping3\r
+#define SB_SMI_REGEC 0xEC // MemRdOvrData3\r
+#define SB_SMI_REGF0 0xF0 // CfgTrapping0\r
+#define SB_SMI_REGF4 0xF4 // CfgTrapping1\r
+#define SB_SMI_REGF8 0xF8 // CfgTrapping2\r
+#define SB_SMI_REGFC 0xFC // CfgTrapping3\r
+\r
+//\r
+// SB800 SB MMIO Base (PMIO)\r
+// offset : 0x300\r
+//\r
+#define SB_PMIOA_REG00 0x00 // ISA Decode\r
+#define SB_PMIOA_REG04 0x04 // ISA Control\r
+#define SB_PMIOA_REG08 0x08 // PCI Control\r
+#define SB_PMIOA_REG0C 0x0C // StpClkSmaf\r
+#define SB_PMIOA_REG10 0x10 // RetryDetect\r
+#define SB_PMIOA_REG14 0x14 // StuckDetect\r
+#define SB_PMIOA_REG20 0x20 // BiosRamEn\r
+#define SB_PMIOA_REG24 0x24 // AcpiMmioEn\r
+#define SB_PMIOA_REG28 0x28 // AsfEn\r
+#define SB_PMIOA_REG2C 0x2C // Smbus0En\r
+#define SB_PMIOA_REG34 0x34 // IoApicEn\r
+#define SB_PMIOA_REG3C 0x3C // SmartVoltEn\r
+#define SB_PMIOA_REG40 0x40 // SmartVolt2En\r
+#define SB_PMIOA_REG44 0x44 // BootTimerEn\r
+#define SB_PMIOA_REG48 0x48 // WatchDogTimerEn\r
+#define SB_PMIOA_REG4C 0x4C // WatchDogTimerConfig\r
+#define SB_PMIOA_REG50 0x50 // HPETEn\r
+#define SB_PMIOA_REG54 0x54 // SerialIrqConfig\r
+#define SB_PMIOA_REG56 0x56 // RtcControl\r
+#define SB_PMIOA_REG58 0x58 // VRT_T1\r
+#define SB_PMIOA_REG59 0x59 // VRT_T2\r
+#define SB_PMIOA_REG5A 0x5A // IntruderControl\r
+#define SB_PMIOA_REG5B 0x5B // RtcShadow\r
+#define SB_PMIOA_REG5C 0x5C\r
+#define SB_PMIOA_REG5D 0x5D\r
+#define SB_PMIOA_REG5E 0x5E // RtcExtIndex\r
+#define SB_PMIOA_REG5F 0x5F // RtcExtData\r
+#define SB_PMIOA_REG60 0x60 // AcpiPm1EvtBlk\r
+#define SB_PMIOA_REG62 0x62 // AcpiPm1CntBlk\r
+#define SB_PMIOA_REG64 0x64 // AcpiPmTmrBlk\r
+#define SB_PMIOA_REG66 0x66 // P_CNTBlk\r
+#define SB_PMIOA_REG68 0x68 // AcpiGpe0Blk\r
+#define SB_PMIOA_REG6A 0x6A // AcpiSmiCmd\r
+#define SB_PMIOA_REG6C 0x6C // AcpiPm2CntBlk\r
+#define SB_PMIOA_REG6E 0x6E // AcpiPmaCntBlk\r
+#define SB_PMIOA_REG74 0x74 // AcpiConfig\r
+#define SB_PMIOA_REG78 0x78 // WakeIoAddr\r
+#define SB_PMIOA_REG7A 0x7A // HaltCountEn\r
+#define SB_PMIOA_REG7C 0x7C // C1eWrPortAdr\r
+#define SB_PMIOA_REG7E 0x7E // CStateEn\r
+#define SB_PMIOA_REG80 0x80 // BreakEvent\r
+#define SB_PMIOA_REG84 0x84 // AutoArbEn\r
+#define SB_PMIOA_REG88 0x88 // CStateControl\r
+#define SB_PMIOA_REG8C 0x8C // StpClkHoldTime\r
+#define SB_PMIOA_REG8E 0x8E // PopUpEndTime\r
+#define SB_PMIOA_REG90 0x90 // C4Control\r
+#define SB_PMIOA_REG94 0x94 // CStateTiming0\r
+#define SB_PMIOA_REG98 0x98 // CStateTiming1\r
+#define SB_PMIOA_REG9C 0x9C // C2Count\r
+#define SB_PMIOA_REG9D 0x9D // C3Count\r
+#define SB_PMIOA_REG9E 0x9E // C4Count\r
+#define SB_PMIOA_REGA0 0xA0 // MessageCState\r
+#define SB_PMIOA_REGA4 0xA4 //\r
+#define SB_PMIOA_REGA8 0xA8 // TrafficMonitorIdleTime\r
+#define SB_PMIOA_REGAA 0xAA // TrafficMonitorIntTime\r
+#define SB_PMIOA_REGAC 0xAC // TrafficMonitorTrafficCount\r
+#define SB_PMIOA_REGAE 0xAE // TrafficMonitorIntrCount\r
+#define SB_PMIOA_REGB0 0xB0 // TrafficMonitorTimeTick\r
+#define SB_PMIOA_REGB4 0xB4 // FidVidControl\r
+#define SB_PMIOA_REGB6 0xB6 // TPRESET1\r
+#define SB_PMIOA_REGB7 0xB7 // Tpreset1b\r
+#define SB_PMIOA_REGB8 0xB8 // TPRESET2\r
+#define SB_PMIOA_REGB9 0xB9 // Test0\r
+#define SB_PMIOA_REGBA 0xBA // S_StateControl\r
+#define SB_PMIOA_REGBC 0xBC // ThrottlingControl\r
+#define SB_PMIOA_REGBE 0xBE // ResetControl\r
+#define SB_PMIOA_REGBF 0xBF // ResetControl\r
+#define SB_PMIOA_REGC0 0xC0 // S5Status\r
+#define SB_PMIOA_REGC2 0xC2 // ResetStatus\r
+#define SB_PMIOA_REGC4 0xC4 // ResetCommand\r
+#define SB_PMIOA_REGC5 0xC5 // CF9Shadow\r
+#define SB_PMIOA_REGC6 0xC6 // HTControl\r
+#define SB_PMIOA_REGC8 0xC8 // Misc\r
+#define SB_PMIOA_REGCC 0xCC // IoDrvSth\r
+#define SB_PMIOA_REGD0 0xD0 // CLKRunEn\r
+#define SB_PMIOA_REGD2 0xD2 // PmioDebug\r
+#define SB_PMIOA_REGD6 0xD6 // IMCGating\r
+#define SB_PMIOA_REGD8 0xD8 // MiscIndex\r
+#define SB_PMIOA_REGD9 0xD9 // MiscData\r
+#define SB_PMIOA_REGDA 0xDA // SataConfig\r
+#define SB_PMIOA_REGDC 0xDC // HyperFlashConfig\r
+#define SB_PMIOA_REGDE 0xDE // ABConfig\r
+#define SB_PMIOA_REGE0 0xE0 // ABRegBar\r
+#define SB_PMIOA_REGE6 0xE6 // FcEn\r
+#define SB_PMIOA_REGEA 0xEA // PcibConfig\r
+#define SB_PMIOA_REGEB 0xEB // AzEn\r
+#define SB_PMIOA_REGEC 0xEC // LpcGating\r
+#define SB_PMIOA_REGED 0xED // UsbGating\r
+#define SB_PMIOA_REGEF 0xEF // UsbEnable\r
+#define SB_PMIOA_REGF0 0xF0 // UsbControl\r
+#define SB_PMIOA_REGF3 0xF3 // UsbDebug\r
+#define SB_PMIOA_REGF6 0xF6 // GecEn\r
+#define SB_PMIOA_REGF8 0xF8 // GecConfig\r
+#define SB_PMIOA_REGFC 0xFC // TraceMemoryEn\r
+\r
+//\r
+// SB800 SB MMIO Base (PMIO2)\r
+// offset : 0x400\r
+//\r
+#define SB_PMIO2_REG00 0x00 // Fan0InputControl\r
+#define SB_PMIO2_REG01 0x01 // Fan0Control\r
+#define SB_PMIO2_REG02 0x02 // Fan0Freq\r
+#define SB_PMIO2_REG03 0x03 // LowDuty0\r
+#define SB_PMIO2_REG04 0x04 // MidDuty0\r
+\r
+#define SB_PMIO2_REG10 0x00 // Fan1InputControl\r
+#define SB_PMIO2_REG11 0x01 // Fan1Control\r
+#define SB_PMIO2_REG12 0x02 // Fan1Freq\r
+#define SB_PMIO2_REG13 0x03 // LowDuty1\r
+#define SB_PMIO2_REG14 0x04 // MidDuty1\r
+\r
+#define SB_PMIO2_REG 0xFC // TraceMemoryEn\r
+\r
+\r
+//\r
+// SB800 SB MMIO Base (GPIO/IoMux)\r
+// offset : 0x100/0xD00\r
+//\r
+/*\r
+GPIO from 0 ~ 67, (GEVENT 0-23) 128 ~ 150, 160 ~ 226.\r
+*/\r
+#define SB_GPIO_REG00 0x00\r
+#define SB_GPIO_REG32 0x20\r
+#define SB_GPIO_REG33 0x21\r
+#define SB_GPIO_REG34 0x22\r
+#define SB_GPIO_REG35 0x23\r
+#define SB_GPIO_REG36 0x24\r
+#define SB_GPIO_REG37 0x25\r
+#define SB_GPIO_REG38 0x26\r
+#define SB_GPIO_REG39 0x27\r
+#define SB_GPIO_REG40 0x28\r
+#define SB_GPIO_REG41 0x29\r
+#define SB_GPIO_REG42 0x2A\r
+#define SB_GPIO_REG43 0x2B\r
+#define SB_GPIO_REG44 0x2C\r
+#define SB_GPIO_REG45 0x2D\r
+#define SB_GPIO_REG46 0x2E\r
+#define SB_GPIO_REG47 0x2F\r
+#define SB_GPIO_REG48 0x30\r
+#define SB_GPIO_REG49 0x31\r
+#define SB_GPIO_REG50 0x32\r
+#define SB_GPIO_REG51 0x33\r
+#define SB_GPIO_REG52 0x34\r
+#define SB_GPIO_REG53 0x35\r
+#define SB_GPIO_REG54 0x36\r
+#define SB_GPIO_REG55 0x37\r
+#define SB_GPIO_REG56 0x38\r
+#define SB_GPIO_REG57 0x39\r
+#define SB_GPIO_REG58 0x3A\r
+#define SB_GPIO_REG59 0x3B\r
+#define SB_GPIO_REG60 0x3C\r
+#define SB_GPIO_REG61 0x3D\r
+#define SB_GPIO_REG62 0x3E\r
+#define SB_GPIO_REG63 0x3F\r
+#define SB_GPIO_REG64 0x40\r
+#define SB_GPIO_REG65 0x41\r
+#define SB_GPIO_REG66 0x42\r
+#define SB_GPIO_REG67 0x43\r
+\r
+#define SB_GEVENT_REG00 0x60\r
+#define SB_GEVENT_REG01 0x61\r
+#define SB_GEVENT_REG02 0x62\r
+#define SB_GEVENT_REG03 0x63\r
+#define SB_GEVENT_REG04 0x64\r
+#define SB_GEVENT_REG05 0x65\r
+#define SB_GEVENT_REG06 0x66\r
+#define SB_GEVENT_REG07 0x67\r
+#define SB_GEVENT_REG08 0x68\r
+#define SB_GEVENT_REG09 0x69\r
+#define SB_GEVENT_REG10 0x6A\r
+#define SB_GEVENT_REG11 0x6B\r
+#define SB_GEVENT_REG12 0x6C\r
+#define SB_GEVENT_REG13 0x6D\r
+#define SB_GEVENT_REG14 0x6E\r
+#define SB_GEVENT_REG15 0x6F\r
+#define SB_GEVENT_REG16 0x70\r
+#define SB_GEVENT_REG17 0x71\r
+#define SB_GEVENT_REG18 0x72\r
+#define SB_GEVENT_REG19 0x73\r
+#define SB_GEVENT_REG20 0x74\r
+#define SB_GEVENT_REG21 0x75\r
+#define SB_GEVENT_REG22 0x76\r
+#define SB_GEVENT_REG23 0x77\r
+// S5-DOMAIN GPIO\r
+#define SB_GPIO_REG160 0xA0\r
+#define SB_GPIO_REG161 0xA1\r
+#define SB_GPIO_REG162 0xA2\r
+#define SB_GPIO_REG163 0xA3\r
+#define SB_GPIO_REG164 0xA4\r
+#define SB_GPIO_REG165 0xA5\r
+#define SB_GPIO_REG166 0xA6\r
+#define SB_GPIO_REG167 0xA7\r
+#define SB_GPIO_REG168 0xA8\r
+#define SB_GPIO_REG169 0xA9\r
+#define SB_GPIO_REG170 0xAA\r
+#define SB_GPIO_REG171 0xAB\r
+#define SB_GPIO_REG172 0xAC\r
+#define SB_GPIO_REG173 0xAD\r
+#define SB_GPIO_REG174 0xAE\r
+#define SB_GPIO_REG175 0xAF\r
+#define SB_GPIO_REG176 0xB0\r
+#define SB_GPIO_REG177 0xB1\r
+#define SB_GPIO_REG178 0xB2\r
+#define SB_GPIO_REG179 0xB3\r
+#define SB_GPIO_REG180 0xB4\r
+#define SB_GPIO_REG181 0xB5\r
+#define SB_GPIO_REG182 0xB6\r
+#define SB_GPIO_REG183 0xB7\r
+#define SB_GPIO_REG184 0xB8\r
+#define SB_GPIO_REG185 0xB9\r
+#define SB_GPIO_REG186 0xBA\r
+#define SB_GPIO_REG187 0xBB\r
+#define SB_GPIO_REG188 0xBC\r
+#define SB_GPIO_REG189 0xBD\r
+#define SB_GPIO_REG190 0xBE\r
+#define SB_GPIO_REG191 0xBF\r
+#define SB_GPIO_REG192 0xC0\r
+#define SB_GPIO_REG193 0xC1\r
+#define SB_GPIO_REG194 0xC2\r
+#define SB_GPIO_REG195 0xC3\r
+#define SB_GPIO_REG196 0xC4\r
+#define SB_GPIO_REG197 0xC5\r
+#define SB_GPIO_REG198 0xC6\r
+#define SB_GPIO_REG199 0xC7\r
+#define SB_GPIO_REG200 0xC8\r
+#define SB_GPIO_REG201 0xC9\r
+#define SB_GPIO_REG202 0xCA\r
+#define SB_GPIO_REG203 0xCB\r
+#define SB_GPIO_REG204 0xCC\r
+#define SB_GPIO_REG205 0xCD\r
+#define SB_GPIO_REG206 0xCE\r
+#define SB_GPIO_REG207 0xCF\r
+#define SB_GPIO_REG208 0xD0\r
+#define SB_GPIO_REG209 0xD1\r
+#define SB_GPIO_REG210 0xD2\r
+#define SB_GPIO_REG211 0xD3\r
+#define SB_GPIO_REG212 0xD4\r
+#define SB_GPIO_REG213 0xD5\r
+#define SB_GPIO_REG214 0xD6\r
+#define SB_GPIO_REG215 0xD7\r
+#define SB_GPIO_REG216 0xD8\r
+#define SB_GPIO_REG217 0xD9\r
+#define SB_GPIO_REG218 0xDA\r
+#define SB_GPIO_REG219 0xDB\r
+#define SB_GPIO_REG220 0xDC\r
+#define SB_GPIO_REG221 0xDD\r
+#define SB_GPIO_REG222 0xDE\r
+#define SB_GPIO_REG223 0xDF\r
+#define SB_GPIO_REG224 0xF0\r
+#define SB_GPIO_REG225 0xF1\r
+#define SB_GPIO_REG226 0xF2\r
+#define SB_GPIO_REG227 0xF3\r
+#define SB_GPIO_REG228 0xF4\r
+\r
+//\r
+// SB800 SB MMIO Base (SMBUS)\r
+// offset : 0xA00\r
+//\r
+#define SB_SMBUS_REG12 0x12 // I2CbusConfig\r
+\r
+//\r
+// SB800 SB MMIO Base (MISC)\r
+// offset : 0xE00\r
+//\r
+#define SB_MISC_REG00 0x00 // ClkCntrl0\r
+/*\r
+SB_MISC_REG00 EQU 000h\r
+ ClkCntrl0 EQU 0FFFFFFFFh\r
+*/\r
+#define SB_MISC_REG04 0x04 // ClkCntrl1\r
+/*\r
+SB_MISC_REG04 EQU 004h\r
+ ClkCntrl1 EQU 0FFFFFFFFh\r
+*/\r
+#define SB_MISC_REG08 0x08 // ClkCntrl2\r
+/*\r
+SB_MISC_REG08 EQU 008h\r
+ ClkCntrl2 EQU 0FFFFFFFFh\r
+*/\r
+#define SB_MISC_REG0C 0x0C // ClkCntrl3\r
+/*\r
+SB_MISC_REG0C EQU 00Ch\r
+ ClkCntrl3 EQU 0FFFFFFFFh\r
+*/\r
+#define SB_MISC_REG10 0x10 // ClkCntrl4\r
+/*\r
+SB_MISC_REG10 EQU 010h\r
+ ClkCntrl4 EQU 0FFFFFFFFh\r
+*/\r
+#define SB_MISC_REG14 0x14 // ClkCntrl5\r
+/*\r
+SB_MISC_REG14 EQU 014h\r
+ ClkCntrl5 EQU 0FFFFFFFFh\r
+*/\r
+#define SB_MISC_REG18 0x18 // ClkCntrl6\r
+/*\r
+SB_MISC_REG18 EQU 018h\r
+ ClkCntrl6 EQU 0FFFFFFFFh\r
+*/\r
+#define SB_MISC_REG30 0x30 // OscFreqCounter\r
+/*\r
+SB_MISC_REG30 EQU 030h\r
+ OscCounter EQU 0FFFFFFFFh ; The 32bit register shows the number of OSC clock per second.\r
+*/\r
+#define SB_MISC_REG34 0x34 // HpetClkPeriod\r
+/*\r
+SB_MISC_REG34 EQU 034h\r
+ HpetClkPeriod EQU 0FFFFFFFFh ; default - 0x429B17Eh (14.31818M).\r
+*/\r
+#define SB_MISC_REG40 0x40 // MiscCntrl for clock only\r
+/*\r
+SB_MISC_REG40 EQU 040h\r
+*/\r
+\r
+#define SB_MISC_REG80 0x80 /**< SB_MISC_REG80\r
+ * @par\r
+ * StrapStatus [15.0] - SB800 chip Strap Status\r
+ * @li <b>0001</b> - Not USED FWH\r
+ * @li <b>0002</b> - Not USED LPC ROM\r
+ * @li <b>0004</b> - EC enabled\r
+ * @li <b>0008</b> - Reserved\r
+ * @li <b>0010</b> - Internal Clock mode\r
+ */\r
+\r
+#define ChipSysNotUseFWHRom 0x0001 // EcPwm3 pad\r
+#define ChipSysNotUseLpcRom 0x0002 // Inverted version from EcPwm2 pad (default - 1)\r
+ // Note: Both EcPwm3 and EcPwm2 straps pins are used to select boot ROM type.\r
+#define ChipSysEcEnable 0x0004 // Enable Embedded Controller (EC)\r
+#define ChipSysBootFailTmrEn 0x0008 // Enable Watchdog function\r
+#define ChipSysIntClkGen 0x0010 // Select 25Mhz crystal clock or 100Mhz PCI-E clock **\r
+\r
+#define SB_MISC_REG84 0x84 // StrapOverride\r
+/*\r
+SB_MISC_REG84 EQU 084h\r
+ Override FWHDisableStrap EQU BIT0 ; Override FWHDiableStrap value from external pin.\r
+ Override UseLpcRomStrap EQU BIT1 ; Override UseLpcRomStrap value from external pin.\r
+ Override EcEnableStrap EQU BIT2 ; Override EcEnableStrap value from external pin.\r
+ Override BootFailTmrEnStrap EQU BIT3 ; Override BootFailTmrEnStrap value from external pin.\r
+ Override DefaultModeStrap EQU BIT5 ; Override DefaultModeStrap value from external pin.\r
+ Override I2CRomStrap EQU BIT7 ; Override I2CRomStrap value from external pin.\r
+ Override ILAAutorunEnBStrap EQU BIT8 ; Override ILAAutorunEnBStrap value from external pin.\r
+ Override FcPllBypStrap EQU BIT9 ; Override FcPllBypStrap value from external pin.\r
+ Override PciPllBypStrap EQU BIT10 ; Override PciPllBypStrap value from external pin.\r
+ Override ShortResetStrap EQU BIT11 ; Override ShortResetStrap value from external pin.\r
+ Override FastBif2ClkStrap EQU BIT13 ; Override FastBif2ClkStrap value from external pin'\r
+ PciRomBootStrap EQU BIT15 ; Override PCI Rom Boot Strap value from external pin ?? Not match 0x80 reg ??\r
+ BlinkSlowModestrap EQU BIT16 ; Override Blink Slow mode (100Mhz) from external pin'\r
+ ClkGenStrap EQU BIT17 ; Override CLKGEN from external pin.\r
+ BIF_GEN2_COMPL_Strap EQU BIT18 ; Override BIF_ GEN2_COMPLIANCE strap from external pin.\r
+ StrapOverrideEn EQU BIT31 ; Enable override strapping feature.\r
+*/\r
+#define SB_MISC_REGC0 0xC0 // CPU_Pstate0\r
+/*\r
+SB_MISC_REGC0 EQU 0C0h\r
+ Core0_PState EQU BIT0+BIT1+BIT2 ; 000: P0 001: P1 010: P2 011: P3 100: P4 101: P5 110: P6 111: P7\r
+ Core1_PState EQU BIT4+BIT5+BIT6\r
+ Core2_PState EQU BIT8+BIT9+BIT10\r
+ Core3_PState EQU BIT12+BIT13+BIT14\r
+ Core4_PState EQU BIT16++BIT17+BIT18\r
+ Core5_PState EQU BIT20+BIT21+BIT22\r
+ Core6_PState EQU BIT24+BIT25+BIT26\r
+ Core7_PState EQU BIT28+BIT29+BIT30\r
+*/\r
+#define SB_MISC_REGC4 0xC4 // CPU_Pstate1\r
+/*\r
+SB_MISC_REGC4 EQU 0C4h\r
+ Core8_PState EQU BIT0+BIT1+BIT2 ; 000: P0 001: P1 010: P2 011: P3 100: P4 101: P5 110: P6 111: P7\r
+ Core9_PState EQU BIT4+BIT5+BIT6\r
+ Core10_PState EQU BIT8+BIT9+BIT10\r
+ Core11_PState EQU BIT12+BIT13+BIT14\r
+ Core12_PState EQU BIT16++BIT17+BIT18\r
+ Core13_PState EQU BIT20+BIT21+BIT22\r
+ Core14_PState EQU BIT24+BIT25+BIT26\r
+ Core15_PState EQU BIT28+BIT29+BIT30\r
+*/\r
+#define SB_MISC_REGD0 0xD0 // CPU_Cstate0\r
+/*\r
+SB_MISC_REGD0 EQU 0D0h\r
+ Core0_CState EQU BIT0+BIT1+BIT2 ; 000: C0 001: C1 010: C2 011: C3 100: C4 101: C5 110: C6 111: C7\r
+ Core1_CState EQU BIT4+BIT5+BIT6\r
+ Core2_CState EQU BIT8+BIT9+BIT10\r
+ Core3_CState EQU BIT12+BIT13+BIT14\r
+ Core4_CState EQU BIT16++BIT17+BIT18\r
+ Core5_CState EQU BIT20+BIT21+BIT22\r
+ Core6_CState EQU BIT24+BIT25+BIT26\r
+ Core7_CState EQU BIT28+BIT29+BIT30\r
+*/\r
+#define SB_MISC_REGD4 0xD4 // CPU_Cstate1\r
+/*\r
+SB_MISC_REGD4 EQU 0D4h\r
+ Core8_CState EQU BIT0+BIT1+BIT2 ; 000: C0 001: C1 010: C2 011: C3 100: C4 101: C5 110: C6 111: C7\r
+ Core9_CState EQU BIT4+BIT5+BIT6\r
+ Core10_CState EQU BIT8+BIT9+BIT10\r
+ Core11_CState EQU BIT12+BIT13+BIT14\r
+ Core12_CState EQU BIT16++BIT17+BIT18\r
+ Core13_CState EQU BIT20+BIT21+BIT22\r
+ Core14_CState EQU BIT24+BIT25+BIT26\r
+ Core15_CState EQU BIT28+BIT29+BIT30\r
+*/\r
+#define SB_MISC_REGF0 0xF0 // SataPortSts ?? EC touch only\r
+/*\r
+SB_MISC_REGF0 EQU 0F0h\r
+ Port0Sts EQU BIT0 ; The selected status of Port 0.\r
+ Port1Sts EQU BIT1 ; The selected status of Port 1\r
+ Port2Sts EQU BIT2 ; The selected status of Port 2.\r
+ Port3Sts EQU BIT3 ; The selected status of Port 3\r
+ Port4Sts EQU BIT4 ; The selected status of Port 4.\r
+ Port5Sts EQU BIT5 ; The selected status of Port 5\r
+ SataPortSel EQU BIT24+BIT25 ; 00 - Select "led" for Port 0 to 5\r
+ ; 01 - Select "delete" for Port 0 to 5\r
+ ; 10 - Select "err" for Port 0 to 5\r
+ ; 11 - Select "led" for Port 0 to 5\r
+*/\r
+\r
+\r
+\r
+#define SB_RTC_REG00 0x00 // Seconds - RW\r
+#define SB_RTC_REG01 0x01 // Seconds Alarm - RW\r
+#define SB_RTC_REG02 0x02 // Minutes - RW\r
+#define SB_RTC_REG03 0x03 // Minutes Alarm - RW\r
+#define SB_RTC_REG04 0x04 // ours - RW\r
+#define SB_RTC_REG05 0x05 // ours Alarm- RW\r
+#define SB_RTC_REG06 0x06 // Day of Week - RW\r
+#define SB_RTC_REG07 0x07 // Date of Mont - RW\r
+#define SB_RTC_REG08 0x08 // Mont - RW\r
+#define SB_RTC_REG09 0x09 // Year - RW\r
+#define SB_RTC_REG0A 0x0A // Register A - RW\r
+#define SB_RTC_REG0B 0x0B // Register B - RW\r
+#define SB_RTC_REG0C 0x0C // Register C - R\r
+#define SB_RTC_REG0D 0x0D // DateAlarm - RW\r
+#define SB_RTC_REG32 0x32 // AltCentury - RW\r
+#define SB_RTC_REG48 0x48 // Century - RW\r
+#define SB_RTC_REG50 0x50 // Extended RAM Address Port - RW\r
+#define SB_RTC_REG53 0x53 // Extended RAM Data Port - RW\r
+#define SB_RTC_REG7E 0x7E // RTC Time Clear - RW\r
+#define SB_RTC_REG7F 0x7F // RTC RAM Enable - RW\r
+\r
+#define SB_ECMOS_REG00 0x00 // scratch - reg\r
+//;BIT0=0 AsicDebug is enabled\r
+//;BIT1=0 SLT S3 runs\r
+#define SB_ECMOS_REG01 0x01\r
+#define SB_ECMOS_REG02 0x02\r
+#define SB_ECMOS_REG03 0x03\r
+#define SB_ECMOS_REG04 0x04\r
+#define SB_ECMOS_REG05 0x05\r
+#define SB_ECMOS_REG06 0x06\r
+#define SB_ECMOS_REG07 0x07\r
+#define SB_ECMOS_REG08 0x08 // save 32BIT Physical address of Config structure\r
+#define SB_ECMOS_REG09 0x09\r
+#define SB_ECMOS_REG0A 0x0A\r
+#define SB_ECMOS_REG0B 0x0B\r
+\r
+#define SB_ECMOS_REG0C 0x0C //;save MODULE_ID\r
+#define SB_ECMOS_REG0D 0x0D //;Reserve for NB\r
+\r
+#define SB_IOMAP_REG00 0x000 // Dma_C 0\r
+#define SB_IOMAP_REG02 0x002 // Dma_C 1\r
+#define SB_IOMAP_REG04 0x004 // Dma_C 2\r
+#define SB_IOMAP_REG06 0x006 // Dma_C 3\r
+#define SB_IOMAP_REG08 0x008 // Dma_Status\r
+#define SB_IOMAP_REG09 0x009 // Dma_WriteRest\r
+#define SB_IOMAP_REG0A 0x00A // Dma_WriteMask\r
+#define SB_IOMAP_REG0B 0x00B // Dma_WriteMode\r
+#define SB_IOMAP_REG0C 0x00C // Dma_Clear\r
+#define SB_IOMAP_REG0D 0x00D // Dma_MasterClr\r
+#define SB_IOMAP_REG0E 0x00E // Dma_ClrMask\r
+#define SB_IOMAP_REG0F 0x00F // Dma_AllMask\r
+#define SB_IOMAP_REG20 0x020 // IntrCntrlReg1\r
+#define SB_IOMAP_REG21 0x021 // IntrCntrlReg2\r
+#define SB_IOMAP_REG40 0x040 // TimerC0\r
+#define SB_IOMAP_REG41 0x041 // TimerC1\r
+#define SB_IOMAP_REG42 0x042 // TimerC2\r
+#define SB_IOMAP_REG43 0x043 // Tmr1CntrlWord\r
+#define SB_IOMAP_REG61 0x061 // Nmi_Status\r
+#define SB_IOMAP_REG70 0x070 // Nmi_Enable\r
+#define SB_IOMAP_REG71 0x071 // RtcDataPort\r
+#define SB_IOMAP_REG72 0x072 // AlternatRtcAddrPort\r
+#define SB_IOMAP_REG73 0x073 // AlternatRtcDataPort\r
+#define SB_IOMAP_REG80 0x080 // Dma_Page_Reserved0\r
+#define SB_IOMAP_REG81 0x081 // Dma_PageC2\r
+#define SB_IOMAP_REG82 0x082 // Dma_PageC3\r
+#define SB_IOMAP_REG83 0x083 // Dma_PageC1\r
+#define SB_IOMAP_REG84 0x084 // Dma_Page_Reserved1\r
+#define SB_IOMAP_REG85 0x085 // Dma_Page_Reserved2\r
+#define SB_IOMAP_REG86 0x086 // Dma_Page_Reserved3\r
+#define SB_IOMAP_REG87 0x087 // Dma_PageC0\r
+#define SB_IOMAP_REG88 0x088 // Dma_Page_Reserved4\r
+#define SB_IOMAP_REG89 0x089 // Dma_PageC6\r
+#define SB_IOMAP_REG8A 0x08A // Dma_PageC7\r
+#define SB_IOMAP_REG8B 0x08B // Dma_PageC5\r
+#define SB_IOMAP_REG8C 0x08C // Dma_Page_Reserved5\r
+#define SB_IOMAP_REG8D 0x08D // Dma_Page_Reserved6\r
+#define SB_IOMAP_REG8E 0x08E // Dma_Page_Reserved7\r
+#define SB_IOMAP_REG8F 0x08F // Dma_Refres\r
+#define SB_IOMAP_REG92 0x092 // FastInit\r
+#define SB_IOMAP_REGA0 0x0A0 // IntrCntrl2Reg1\r
+#define SB_IOMAP_REGA1 0x0A1 // IntrCntrl2Reg2\r
+#define SB_IOMAP_REGC0 0x0C0 // Dma2_C4Addr\r
+#define SB_IOMAP_REGC2 0x0C2 // Dma2_C4Cnt\r
+#define SB_IOMAP_REGC4 0x0C4 // Dma2_C5Addr\r
+#define SB_IOMAP_REGC6 0x0C6 // Dma2_C5Cnt\r
+#define SB_IOMAP_REGC8 0x0C8 // Dma2_C6Addr\r
+#define SB_IOMAP_REGCA 0x0CA // Dma2_C6Cnt\r
+#define SB_IOMAP_REGCC 0x0CC // Dma2_C7Addr\r
+#define SB_IOMAP_REGCE 0x0CE // Dma2_C7Cnt\r
+#define SB_IOMAP_REGD0 0x0D0 // Dma_Status\r
+#define SB_IOMAP_REGD2 0x0D2 // Dma_WriteRest\r
+#define SB_IOMAP_REGD4 0x0D4 // Dma_WriteMask\r
+#define SB_IOMAP_REGD6 0x0D6 // Dma_WriteMode\r
+#define SB_IOMAP_REGD8 0x0D8 // Dma_Clear\r
+#define SB_IOMAP_REGDA 0x0DA // Dma_Clear\r
+#define SB_IOMAP_REGDC 0x0DC // Dma_ClrMask\r
+#define SB_IOMAP_REGDE 0x0DE // Dma_ClrMask\r
+#define SB_IOMAP_REGF0 0x0F0 // NCP_Error\r
+#define SB_IOMAP_REG40B 0x040B // DMA1_Extend\r
+#define SB_IOMAP_REG4D0 0x04D0 // IntrEdgeControl\r
+#define SB_IOMAP_REG4D6 0x04D6 // DMA2_Extend\r
+#define SB_IOMAP_REGC00 0x0C00 // Pci_Intr_Index\r
+#define SB_IOMAP_REGC01 0x0C01 // Pci_Intr_Data\r
+#define SB_IOMAP_REGC14 0x0C14 // Pci_Error\r
+#define SB_IOMAP_REGC50 0x0C50 // CMIndex\r
+#define SB_IOMAP_REGC51 0x0C51 // CMData\r
+#define SB_IOMAP_REGC52 0x0C52 // GpmPort\r
+#define SB_IOMAP_REGC6F 0x0C6F // Isa_Misc\r
+#define SB_IOMAP_REGCD0 0x0CD0 // PMio2_Index\r
+#define SB_IOMAP_REGCD1 0x0CD1 // PMio2_Data\r
+#define SB_IOMAP_REGCD4 0x0CD4 // BIOSRAM_Index\r
+#define SB_IOMAP_REGCD5 0x0CD5 // BIOSRAM_Data\r
+#define SB_IOMAP_REGCD6 0x0CD6 // PM_Index\r
+#define SB_IOMAP_REGCD7 0x0CD7 // PM_Data\r
+#define SB_IOMAP_REGCF9 0x0CF9 // CF9Rst reg\r
+\r
+\r
+#define SB_SPI_MMIO_REG00 0x00 //SPI_\r
+#define SB_SPI_MMIO_REG0C 0x0C //SPI_Cntrl1 Register\r
+\r
+#define AMD_NB_REG78 0x78\r
+#define AMD_NB_SCRATCH AMD_NB_REG78\r
+#define MailBoxPort 0x3E\r
+\r
+// GPP Link Configuration\r
+#define GPP_CFGMODE_X4000 0x0\r
+#define GPP_CFGMODE_X2200 0x2\r
+#define GPP_CFGMODE_X2110 0x3\r
+#define GPP_CFGMODE_X1111 0x4\r
+\r
+#define MAX_TRAINING_RETRY 0x4000\r
+#define MAX_GPP_RESETS 8 //lx-temp to confirm with jason\r
+\r
+\r
+#pragma pack (pop)\r
+\r
--- /dev/null
+/**\r
+ * @file\r
+ *\r
+ * Southbridge Initial routine\r
+ *\r
+ *\r
+ *\r
+ * @xrefitem bom "File Content Label" "Release Content"\r
+ * @e project: CIMx-SB\r
+ * @e sub-project:\r
+ * @e \$Revision:$ @e \$Date:$\r
+ *\r
+ */\r
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+\r
+#include "SBPLATFORM.h"\r
+//\r
+// Declaration of local functions\r
+//\r
+\r
+VOID abcfgTbl (IN ABTBLENTRY* pABTbl);\r
+\r
+/**\r
+ * sbUsbPhySetting - USB Phy Calibration Adjustment\r
+ *\r
+ *\r
+ * @param[in] Value Controller PCI config address (bus# + device# + function#)\r
+ *\r
+ */\r
+VOID sbUsbPhySetting (IN UINT32 Value);\r
+\r
+\r
+/*--------------------------- Documentation Pages ---------------------------*/\r
+/**\r
+ * @page LegacyInterfaceCalls Legacy Interface Calls\r
+ * <TD>@subpage SB_POWERON_INIT_Page "SB_POWERON_INIT"</TD><TD></TD>\r
+ * <TD>@subpage SB_BEFORE_PCI_INIT_Page "SB_BEFORE_PCI_INIT"</TD><TD></TD>\r
+ * <TD>@subpage SB_AFTER_PCI_INIT_Page "SB_AFTER_PCI_INIT"</TD><TD></TD>\r
+ * <TD>@subpage SB_LATE_POST_INIT_Page "SB_LATE_POST_INIT"</TD><TD></TD>\r
+ * <TD>@subpage SB_BEFORE_PCI_RESTORE_INIT_Page "SB_BEFORE_PCI_RESTORE_INIT"</TD><TD></TD>\r
+ * <TD>@subpage SB_AFTER_PCI_RESTORE_INIT_Page "SB_AFTER_PCI_RESTORE_INIT"</TD><TD></TD>\r
+ * <TD>@subpage SB_SMM_SERVICE_Page "SB_SMM_SERVICE"</TD><TD></TD>\r
+ * <TD>@subpage SB_SMM_ACPION_Page "SB_SMM_ACPION"</TD><TD></TD>\r
+ *\r
+ * @page LegacyInterfaceCallOuts Legacy Interface CallOuts\r
+ * <TD>@subpage CB_SBGPP_RESET_ASSERT_Page CB_SBGPP_RESET_ASSERT\r
+ * <TD>@subpage CB_SBGPP_RESET_DEASSERT_Page CB_SBGPP_RESET_DEASSERT\r
+ *\r
+*/\r
+\r
+/**\r
+ * sbEarlyPostByteInitTable - PCI device registers initial during early POST.\r
+ *\r
+ */\r
+REG8MASK sbEarlyPostByteInitTable[] =\r
+{\r
+ // SMBUS Device (Bus 0, Dev 20, Func 0)\r
+ {0x00, SMBUS_BUS_DEV_FUN, 0},\r
+ {SB_CFG_REG10, 0X00, (SBCIMx_Version & 0xFF)}, //Program the version information\r
+ {SB_CFG_REG11, 0X00, (SBCIMx_Version >> 8)},\r
+ {0xFF, 0xFF, 0xFF},\r
+\r
+ // IDE Device (Bus 0, Dev 20, Func 1)\r
+ {0x00, IDE_BUS_DEV_FUN, 0},\r
+ {SB_IDE_REG62 + 1, ~BIT0, BIT5}, // Enabling IDE Explicit Pre-Fetch IDE PCI Config 0x62[8]=0\r
+ // Allow MSI capability of IDE controller to be visible. IDE PCI Config 0x62[13]=1\r
+ {0xFF, 0xFF, 0xFF},\r
+\r
+ // Azalia Device (Bus 0, Dev 20, Func 2)\r
+ {0x00, AZALIA_BUS_DEV_FUN, 0},\r
+ {SB_AZ_REG4C, ~BIT0, BIT0},\r
+ {0xFF, 0xFF, 0xFF},\r
+\r
+ // LPC Device (Bus 0, Dev 20, Func 3)\r
+ {0x00, LPC_BUS_DEV_FUN, 0},\r
+ {SB_LPC_REG40, ~BIT2, BIT2}, // RPR 1.1 Enabling LPC DMA Function 0x40[2]=1b 0x78[0]=0b\r
+ {SB_LPC_REG78, ~BIT0, 00}, // RPR 1.1 Enabling LPC DMA Function 0x40[2]=1b 0x78[0]=0b\r
+ {SB_LPC_REG78, ~BIT1, 00}, // Disables MSI capability\r
+ {SB_LPC_REGBB, ~BIT0, BIT0 + BIT3 + BIT4 + BIT5}, // Enabled SPI Prefetch from HOST.\r
+ {0xFF, 0xFF, 0xFF},\r
+\r
+ // PCIB Bridge (Bus 0, Dev 20, Func 4)\r
+ {0x00, PCIB_BUS_DEV_FUN, 0},\r
+ {SB_PCIB_REG40, 0xFF, BIT5}, // RPR PCI-bridge Subtractive Decode\r
+ {SB_PCIB_REG4B, 0xFF, BIT7}, //\r
+ {SB_PCIB_REG66, 0xFF, BIT4}, // RPR Enabling One-Prefetch-Channel Mode, PCIB_PCI_config 0x64 [20]\r
+ {SB_PCIB_REG65, 0xFF, BIT7}, // RPR proper operation of CLKRUN#.\r
+ {SB_PCIB_REG0D, 0x00, 0x40}, // Setting Latency Timers to 0x40, Enables the PCIB to retain ownership\r
+ {SB_PCIB_REG1B, 0x00, 0x40}, // of the bus on the Primary side and on the Secondary side when GNT# is deasserted.\r
+ {SB_PCIB_REG66 + 1, 0xFF, BIT1}, // RPR Enable PCI bus GNT3#..\r
+ {0xFF, 0xFF, 0xFF},\r
+\r
+ // SATA Device (Bus 0, Dev 17, Func 0)\r
+ {0x00, SATA_BUS_DEV_FUN, 0},\r
+ {SB_SATA_REG44, 0xff, BIT0}, // Enables the SATA watchdog timer register prior to the SATA BIOS post\r
+ {SB_SATA_REG44 + 2, 0, 0x20}, // RPR 8.12 SATA PCI Watchdog timer setting\r
+ // [SB01923] Set timer out to 0x20 to fix IDE to SATA Bridge dropping drive issue.\r
+ {0xFF, 0xFF, 0xFF},\r
+};\r
+\r
+\r
+/**\r
+ * sbPmioEPostInitTable - Southbridge ACPI MMIO initial during POST.\r
+ *\r
+ */\r
+AcpiRegWrite sbPmioEPostInitTable[] =\r
+{\r
+ // HPET workaround\r
+ {PMIO_BASE >> 8, SB_PMIOA_REG54 + 3, 0xFC, BIT0 + BIT1},\r
+ {PMIO_BASE >> 8, SB_PMIOA_REG54 + 2, 0x7F, BIT7},\r
+ {PMIO_BASE >> 8, SB_PMIOA_REG54 + 2, 0x7F, 0x00},\r
+ // End of HPET workaround\r
+ // Enable SB800 A12 ACPI bits at PMIO 0xC0 [30,10:3]\r
+ // ClrAllStsInThermalEvent 3 Set to 1 to allow ASF remote power down/power cycle, Thermal event, Fan slow event to clear all the Gevent status and enabled bits. The bit should be set to 1 all the time.\r
+ // UsbGoodClkDlyEn 4 Set to 1 to delay de-assertion of Usb clk by 6 Osc clk. The bit should be set to 1 all the time.\r
+ // ForceNBCPUPwr 5 Set to 1 to force CPU pwrGood to be toggled along with NB pwrGood.\r
+ // MergeUsbPerReq 6 Set to 1 to merge usb perdical traffic into usb request as one of break event.\r
+ // IMCWatchDogRstEn 7 Set to 1 to allow IMC watchdog timer to reset entire acpi block. The bit should be set to 1 when IMC is enabled.\r
+ // GeventStsFixEn 8 1: Gevent status is not reset by its enable bit. 0: Gevent status is reset by its enable bit.\r
+ // PmeTimerFixEn 9 Set to 1 to reset Pme Timer when going to sleep state.\r
+ // UserRst2EcEn 10 Set to 1 to route user reset event to Ec. The bit should be set to 1 when IMC is enabled.\r
+ // Smbus0ClkSEn 30 Set to 1 to enable SMBus0 controller clock stretch support.\r
+ {PMIO_BASE >> 8, SB_PMIOA_REGC4, ~(BIT2 + BIT4), BIT2 + BIT4},\r
+ {PMIO_BASE >> 8, SB_PMIOA_REGC0, 0, 0xF9},\r
+ // PM_reg xC1 [3] = 1b, per RPR 2.7 CPU PwrGood Setting\r
+ {PMIO_BASE >> 8, SB_PMIOA_REGC0 + 1, 0x04, 0x0B},\r
+ // RtcSts 19-17 RTC_STS set only in Sleep State.\r
+ // GppPme 20 Set to 1 to enable PME request from SB GPP.\r
+ // Pcireset 22 Set to 1 to allow SW to reset PCIe.\r
+ {PMIO_BASE >> 8, SB_PMIOA_REGC2, 0x20, 0x58},\r
+ {PMIO_BASE >> 8, SB_PMIOA_REGC2 + 1, 0, 0x40},\r
+\r
+ //Item Id: SB02037: RTC_STS should be set in S state\r
+ //set PMIO 0xC0 [19:16] Set to 1110 to allow RTC_STS to be set only in non_G0 state.\r
+ //{PMIO_BASE >> 8, SB_PMIOA_REGC2, (UINT8)~(0x0F), 0x0E},\r
+\r
+ //Item Id: SB02034\r
+ //Title: SB GPP NIC auto wake at second time sleep\r
+ //set PMIO 0xC4 bit 2 to 1 then set PMIO 0xC0 bit 20 to 1 to enable fix for SB02034\r
+\r
+ {PMIO_BASE >> 8, SB_PMIOA_REGC2, ~(BIT4), BIT4},\r
+\r
+ //{GPIO_BASE >> 8, SB_GPIO_REG62 , 0x00, 0x4E},\r
+ {PMIO_BASE >> 8, SB_PMIOA_REG74, 0x00, BIT0 + BIT1 + BIT2 + BIT4},\r
+ {PMIO_BASE >> 8, SB_PMIOA_REGDE + 1, ~(BIT0 + BIT1), BIT0 + BIT1},\r
+ {PMIO_BASE >> 8, SB_PMIOA_REGDE, ~BIT4, BIT4},\r
+ {PMIO_BASE >> 8, SB_PMIOA_REGBA, ~BIT3, BIT3},\r
+ {PMIO_BASE >> 8, SB_PMIOA_REGBA + 1, ~BIT6, BIT6},\r
+ {PMIO_BASE >> 8, SB_PMIOA_REGBC, ~BIT1, BIT1},\r
+ {PMIO_BASE >> 8, SB_PMIOA_REGED, ~(BIT0 + BIT1), 0},\r
+ //RPR Hiding Flash Controller PM_IO 0xDC[7] = 0x0 & PM_IO 0xDC [1:0]=0x01\r
+ {PMIO_BASE >> 8, SB_PMIOA_REGDC, 0x7C, BIT0},\r
+ // RPR Turning off FC clock\r
+ {MISC_BASE >> 8, SB_MISC_REG40 + 1, ~(BIT3 + BIT2), BIT3 + BIT2},\r
+ {MISC_BASE >> 8, SB_MISC_REG40 + 2, ~BIT0, BIT0},\r
+ {SMI_BASE >> 8, SB_SMI_Gevent0, 0, 29},\r
+ {SMI_BASE >> 8, SB_SMI_Gevent1, 0, 1},\r
+ {SMI_BASE >> 8, SB_SMI_Gevent2, 0, 29},\r
+ {SMI_BASE >> 8, SB_SMI_Gevent3, 0, 29},\r
+ {SMI_BASE >> 8, SB_SMI_Gevent4, 0, 4},\r
+ {SMI_BASE >> 8, SB_SMI_Gevent5, 0, 5},\r
+ {SMI_BASE >> 8, SB_SMI_Gevent6, 0, 6},\r
+ {SMI_BASE >> 8, SB_SMI_Gevent7, 0, 29},\r
+\r
+ {SMI_BASE >> 8, SB_SMI_Gevent9, 0, 29},\r
+ {SMI_BASE >> 8, SB_SMI_Gevent10, 0, 29},\r
+ {SMI_BASE >> 8, SB_SMI_Gevent11, 0, 29},\r
+ {SMI_BASE >> 8, SB_SMI_Gevent12, 0, 29},\r
+ {SMI_BASE >> 8, SB_SMI_Gevent13, 0, 29},\r
+ {SMI_BASE >> 8, SB_SMI_Gevent14, 0, 29},\r
+ {SMI_BASE >> 8, SB_SMI_Gevent15, 0, 29},\r
+ {SMI_BASE >> 8, SB_SMI_Gevent16, 0, 29},\r
+ {SMI_BASE >> 8, SB_SMI_Gevent17, 0, 29},\r
+ {SMI_BASE >> 8, SB_SMI_Gevent18, 0, 29},\r
+ {SMI_BASE >> 8, SB_SMI_Gevent19, 0, 29},\r
+ {SMI_BASE >> 8, SB_SMI_Gevent20, 0, 29},\r
+ {SMI_BASE >> 8, SB_SMI_Gevent21, 0, 29},\r
+ {SMI_BASE >> 8, SB_SMI_Gevent22, 0, 29},\r
+ {SMI_BASE >> 8, SB_SMI_Gevent23, 0, 29},\r
+//\r
+ {SMI_BASE >> 8, SB_SMI_Usbwakup0, 0, 11},\r
+ {SMI_BASE >> 8, SB_SMI_Usbwakup1, 0, 11},\r
+ {SMI_BASE >> 8, SB_SMI_Usbwakup2, 0, 11},\r
+ {SMI_BASE >> 8, SB_SMI_Usbwakup3, 0, 11},\r
+ {SMI_BASE >> 8, SB_SMI_IMCGevent0, 0, 12},\r
+ {SMI_BASE >> 8, SB_SMI_IMCGevent1, 0, 29},\r
+ {SMI_BASE >> 8, SB_SMI_FanThGevent, 0, 13},\r
+ {SMI_BASE >> 8, SB_SMI_SBGppPme0, 0, 15},\r
+ {SMI_BASE >> 8, SB_SMI_SBGppPme1, 0, 16},\r
+ {SMI_BASE >> 8, SB_SMI_SBGppPme2, 0, 17},\r
+ {SMI_BASE >> 8, SB_SMI_SBGppPme3, 0, 18},\r
+ {SMI_BASE >> 8, SB_SMI_SBGppHp0, 0, 29},\r
+ {SMI_BASE >> 8, SB_SMI_SBGppHp1, 0, 29},\r
+ {SMI_BASE >> 8, SB_SMI_SBGppHp2, 0, 29},\r
+ {SMI_BASE >> 8, SB_SMI_SBGppHp3, 0, 29},\r
+ {SMI_BASE >> 8, SB_SMI_GecPme, 0, 19},\r
+ {SMI_BASE >> 8, SB_SMI_CIRPme, 0, 23},\r
+ {SMI_BASE >> 8, SB_SMI_Gevent8, 0, 26},\r
+ {SMI_BASE >> 8, SB_SMI_AzaliaPme, 0, 27},\r
+ {SMI_BASE >> 8, SB_SMI_SataGevent0, 0, 30},\r
+ {SMI_BASE >> 8, SB_SMI_SataGevent1, 0, 31},\r
+\r
+ {SMI_BASE >> 8, SB_SMI_WakePinGevent, 0, 29},\r
+ {SMI_BASE >> 8, SB_SMI_ASFMasterIntr, 0, 29},\r
+ {SMI_BASE >> 8, SB_SMI_ASFSlaveIntr, 0, 29},\r
+\r
+// {SMI_BASE >> 8, SB_SMI_REG04, ~BIT4, BIT4},\r
+// {SMI_BASE >> 8, SB_SMI_REG04 + 1, ~BIT0, BIT0},\r
+// {SMI_BASE >> 8, SB_SMI_REG04 + 2, ~BIT3, BIT3},\r
+ {SMI_BASE >> 8, SB_SMI_REG08, ~BIT4, 0},\r
+ {SMI_BASE >> 8, SB_SMI_REG08+3, ~BIT2, 0},\r
+// {SMI_BASE >> 8, SB_SMI_REG0C, ~BIT4, BIT4},\r
+ {SMI_BASE >> 8, SB_SMI_REG0C + 2, ~BIT3, BIT3},\r
+ {SMI_BASE >> 8, SB_SMI_TWARN, 0, 9},\r
+ {SMI_BASE >> 8, SB_SMI_TMI, 0, 29},\r
+ {0xFF, 0xFF, 0xFF, 0xFF},\r
+};\r
+\r
+/**\r
+ * abTblEntry800 - AB-Link Configuration Table for SB800\r
+ *\r
+ */\r
+ABTBLENTRY abTblEntry800[] =\r
+{\r
+ // RPR Enable downstream posted transactions to pass non-posted transactions.\r
+ {ABCFG, SB_ABCFG_REG10090, BIT8 + BIT16, BIT8 + BIT16},\r
+\r
+ // RPR Enable SB800 to issue memory read/write requests in the upstream direction.\r
+ {AXCFG, SB_AB_REG04, BIT2, BIT2},\r
+\r
+ // RPR Enabling IDE/PCIB Prefetch for Performance Enhancement\r
+ // PCIB prefetch ABCFG 0x10060 [20] = 1 ABCFG 0x10064 [20] = 1\r
+ {ABCFG, SB_ABCFG_REG10060, BIT20, BIT20}, // PCIB prefetch enable\r
+ {ABCFG, SB_ABCFG_REG10064, BIT20, BIT20}, // PCIB prefetch enable\r
+\r
+ // RPR Controls the USB OHCI controller prefetch used for enhancing performance of ISO out devices.\r
+ // RPR Setting B-Link Prefetch Mode (ABCFG 0x80 [18:17] = 11)\r
+ {ABCFG, SB_ABCFG_REG80, BIT0 + BIT17 + BIT18, BIT0 + BIT17 + BIT18},\r
+\r
+ // RPR Enabled SMI ordering enhancement. ABCFG 0x90[21]\r
+ // RPR USB Delay A-Link Express L1 State. ABCFG 0x90[17]\r
+ {ABCFG, SB_ABCFG_REG90, BIT21 + BIT17, BIT21 + BIT17},\r
+\r
+ // RPR Disable the credit variable in the downstream arbitration equation\r
+ // RPR Register bit to qualify additional address bits into downstream register programming. (A12 BIT1 default is set)\r
+ {ABCFG, SB_ABCFG_REG9C, BIT0, BIT0},\r
+\r
+ // RPR Enabling Detection of Upstream Interrupts ABCFG 0x94 [20] = 1\r
+ // ABCFG 0x94 [19:0] = cpu interrupt delivery address [39:20]\r
+ {ABCFG, SB_ABCFG_REG94, BIT20, BIT20 + 0x00FEE},\r
+\r
+ // RPR Programming cycle delay for AB and BIF clock gating\r
+ // RPR Enable the AB and BIF clock-gating logic.\r
+ // RPR Enable the A-Link int_arbiter enhancement to allow the A-Link bandwidth to be used more efficiently\r
+ // RPR Enable the requester ID for upstream traffic. [16]: SB/NB link [17]: GPP\r
+ {ABCFG, SB_ABCFG_REG10054, 0x00FFFFFF, 0x010407FF},\r
+ {ABCFG, SB_ABCFG_REG98, 0xFFFF00FF, 0x00034700},\r
+ {ABCFG, SB_ABCFG_REG54, 0x00FF0000, 0x00040000},\r
+ // RPR Non-Posted Memory Write Support\r
+ {AX_INDXC, SB_AX_INDXC_REG10, BIT9, BIT9},\r
+ {ABCFG, 0, 0, (UINT8) 0xFF}, // This dummy entry is to clear ab index\r
+ { (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF},\r
+};\r
+\r
+/**\r
+ * SbPcieOrderRule - AB-Link Configuration Table for ablink Post Pass Np Downstream/Upstream Feature\r
+ *\r
+ */\r
+ABTBLENTRY SbPcieOrderRule[] =\r
+{\r
+// abPostPassNpDownStreamTbl\r
+ {ABCFG, SB_ABCFG_REG10060, BIT31, BIT31},\r
+ {ABCFG, SB_ABCFG_REG1009C, BIT4 + BIT5, BIT4 + BIT5},\r
+ {ABCFG, SB_ABCFG_REG9C, BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7, BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + BIT7},\r
+ {ABCFG, SB_ABCFG_REG90, BIT21 + BIT22 + BIT23, BIT21 + BIT22 + BIT23},\r
+ {ABCFG, SB_ABCFG_REGF0, BIT6 + BIT5, BIT6 + BIT5},\r
+ {AXINDC, SB_AX_INDXC_REG02, BIT9, BIT9},\r
+ {ABCFG, SB_ABCFG_REG10090, BIT9 + BIT10 + BIT11 + BIT12, BIT9 + BIT10 + BIT11 + BIT12},\r
+// abPostPassNpUpStreamTbl\r
+ {ABCFG, SB_ABCFG_REG58, BIT10, BIT10},\r
+ {ABCFG, SB_ABCFG_REGF0, BIT3 + BIT4, BIT3 + BIT4},\r
+ {ABCFG, SB_ABCFG_REG54, BIT1, BIT1},\r
+ { (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF, (UINT8)0xFF},\r
+};\r
+\r
+/**\r
+ * commonInitEarlyBoot - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB.\r
+ *\r
+ * This settings should be done during S3 resume also\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+commonInitEarlyBoot (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT32 abValue;\r
+ UINT16 dwTempVar;\r
+ SB_CPUID_DATA CpuId;\r
+ UINT8 cimNativepciesupport;\r
+ UINT8 cimIrConfig;\r
+ UINT8 Data;\r
+\r
+ cimNativepciesupport = (UINT8) pConfig->NativePcieSupport;\r
+ cimIrConfig = (UINT8) pConfig->IrConfig;\r
+#if SB_CIMx_PARAMETER == 0\r
+ cimNativepciesupport = cimNativepciesupportDefault;\r
+ cimIrConfig = cimIrConfigDefault;\r
+#endif\r
+\r
+ //IR init Logical device 0x05\r
+ if ( cimIrConfig ) {\r
+ // Enable EC_PortActive\r
+ RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4), AccWidthUint16 | S3_SAVE, 0xFFFE, BIT0);\r
+ EnterEcConfig ();\r
+ RWEC8 (0x07, 0x00, 0x05); //Select logical device 05, IR controller\r
+ RWEC8 (0x60, 0x00, 0x05); //Set Base Address to 550h\r
+ RWEC8 (0x61, 0x00, 0x50);\r
+ RWEC8 (0x70, 0xF0, 0x05); //Set IRQ to 05h\r
+ RWEC8 (0x30, 0x00, 0x01); //Enable logical device 5, IR controller\r
+ Data = 0xAB;\r
+ WriteIO (0x550, AccWidthUint8, &Data);\r
+ ReadIO (0x551, AccWidthUint8, &Data);\r
+ Data = ((Data & 0xFC ) | cimIrConfig);\r
+ WriteIO (0x551, AccWidthUint8, &Data);\r
+ ExitEcConfig ();\r
+ Data = 0xA0; // EC APIC index\r
+ WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &Data);\r
+ Data = 0x05; // IRQ5\r
+ WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &Data);\r
+ } else {\r
+ EnterEcConfig ();\r
+ RWEC8 (0x07, 0x00, 0x05); //Select logical device 05, IR controller\r
+ RWEC8 (0x30, 0x00, 0x00); //Disable logical device 5, IR controller\r
+ ExitEcConfig ();\r
+ }\r
+\r
+\r
+ CpuidRead (0x01, &CpuId);\r
+\r
+ //\r
+ // SB CFG programming\r
+ //\r
+ //Make BAR registers of smbus visible.\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, 0);\r
+ //Early post initialization of pci config space\r
+ programPciByteTable ((REG8MASK*) FIXUP_PTR (&sbEarlyPostByteInitTable[0]), sizeof (sbEarlyPostByteInitTable) / sizeof (REG8MASK) );\r
+ if ( pConfig->BuildParameters.SmbusSsid != NULL ) {\r
+ RWPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.SmbusSsid);\r
+ }\r
+ //Make BAR registers of smbus invisible.\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, BIT6);\r
+\r
+ //\r
+ // LPC CFG programming\r
+ //\r
+ // SSID for LPC Controller\r
+ if (pConfig->BuildParameters.LpcSsid != NULL ) {\r
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.LpcSsid);\r
+ }\r
+ // LPC MSI\r
+ if ( pConfig->BuildParameters.LpcMsi) {\r
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG78, AccWidthUint32 | S3_SAVE, ~BIT1, BIT1);\r
+ }\r
+\r
+ //\r
+ // PCIB CFG programming\r
+ //\r
+ //Disable or Enable PCI Clks based on input\r
+ RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG42, AccWidthUint8 | S3_SAVE, ~(BIT5 + BIT4 + BIT3 + BIT2), ((pConfig->PciClks) & 0x0F) << 2 );\r
+ RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG4A, AccWidthUint8 | S3_SAVE, ~(BIT1 + BIT0), (pConfig->PciClks) >> 4 );\r
+ // PCIB MSI\r
+ if ( pConfig->BuildParameters.PcibMsi) {\r
+ RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG40, AccWidthUint8 | S3_SAVE, ~BIT3, BIT3);\r
+ }\r
+\r
+ //\r
+ // AB CFG programming\r
+ //\r
+ // Read Arbiter address, Arbiter address is in PMIO 6Ch\r
+ ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6C, AccWidthUint16, &dwTempVar);\r
+ RWIO (dwTempVar, AccWidthUint8, 0, 0); // Write 0 to enable the arbiter\r
+\r
+ abLinkInitBeforePciEnum (pConfig); // Set ABCFG registers\r
+ // AB MSI\r
+ if ( pConfig->BuildParameters.AbMsi) {\r
+ abValue = readAlink (SB_ABCFG_REG94 | (UINT32) (ABCFG << 29));\r
+ abValue = abValue | BIT20;\r
+ writeAlink (SB_ABCFG_REG94 | (UINT32) (ABCFG << 29), abValue);\r
+ }\r
+\r
+\r
+ //\r
+ // SB Specific Function programming\r
+ //\r
+\r
+ // PCIE Native setting\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGBA + 1, AccWidthUint8, ~BIT14, 0);\r
+ if ( pConfig->NativePcieSupport == 1) {\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG74 + 3, AccWidthUint8, ~(BIT3 + BIT1 + BIT0), BIT2 + BIT0);\r
+ } else {\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG74 + 3, AccWidthUint8, ~(BIT3 + BIT1 + BIT0), BIT2);\r
+ }\r
+\r
+#ifdef ACPI_SLEEP_TRAP\r
+ // Set SLP_TYPE as SMI event\r
+ RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGB0, AccWidthUint8, ~(BIT2 + BIT3), BIT2);\r
+ // Disabled SLP function for S1/S3/S4/S5\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGBE, AccWidthUint8, ~BIT5, 0x00);\r
+ // Set S state transition disabled (BIT0) force ACPI to send SMI message when writing to SLP_TYP Acpi register. (BIT1)\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG08 + 3, AccWidthUint8, ~(BIT0 + BIT1), BIT1);\r
+ // Enabled Global Smi ( BIT7 clear as 0 to enable )\r
+ RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REG98 + 3 , AccWidthUint8, ~BIT7, 0x00);\r
+#endif\r
+ if ( pConfig->SbUsbPll == 0) {\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF3, AccWidthUint8, 0, 0x20);\r
+ }\r
+ // Set Stutter timer settings\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 1, AccWidthUint8, ~(BIT3 + BIT4), BIT3 + BIT4);\r
+ // Set LDTSTP# duration to 10us for HydraD CPU, or when HT link is 200MHz\r
+ if ((pConfig->AnyHT200MhzLink) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100080) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x100090) || ((CpuId.EAX_Reg & 0x00ff00f0) == 0x1000A0)) {\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94, AccWidthUint8, 0, 0x0A);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 3, AccWidthUint8 | S3_SAVE, 0xFE, 0x28);\r
+ } else {\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94, AccWidthUint8, 0, 0x01);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 3, AccWidthUint8 | S3_SAVE, 0xFE, 0x20);\r
+ }\r
+\r
+ //PM_Reg 0x7A[15] (CountHaltMsgEn) should be set when C1e option is enabled\r
+ //PM_Reg 0x7A[3:0] (NumOfCpu) should be set to 1h when C1e option is enabled\r
+ //PM_Reg 0x80[13] has to set to 1 to enable Message C scheme. \r
+ if (pConfig->MTC1e) {\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7A, AccWidthUint16 | S3_SAVE, 0x7FF0, BIT15 + 1);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80 + 1, AccWidthUint8 | S3_SAVE, ~BIT5, BIT5);\r
+ }\r
+\r
+ programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr));\r
+}\r
+\r
+/**\r
+ * abSpecialSetBeforePciEnum - Special setting ABCFG registers before PCI emulation.\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+abSpecialSetBeforePciEnum (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT32 abValue;\r
+ abValue = readAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29));\r
+ abValue &= 0xf0;\r
+ if ( pConfig->SbPcieOrderRule && abValue ) {\r
+ abValue = readAlink (SB_RCINDXC_REG02 | (UINT32) (RCINDXC << 29));\r
+ abValue = abValue | BIT9;\r
+ writeAlink (SB_RCINDXC_REG02 | (UINT32) (RCINDXC << 29), abValue);\r
+ }\r
+}\r
+\r
+VOID\r
+usbDesertPll (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ if ( pConfig->SbUsbPll == 0) {\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF3, AccWidthUint8, 0, 0x00);\r
+ }\r
+}\r
+\r
+/**\r
+ * commonInitEarlyPost - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB.\r
+ *\r
+ * This settings might not program during S3 resume\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+commonInitEarlyPost (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT8 dbPortStatus;\r
+ UINT8 cimSpreadSpectrum;\r
+ UINT32 cimSpreadSpectrumType;\r
+ AMDSBCFG* pTmp;\r
+ pTmp = pConfig;\r
+\r
+ cimSpreadSpectrum = pConfig->SpreadSpectrum;\r
+ cimSpreadSpectrumType = pConfig->BuildParameters.SpreadSpectrumType;\r
+#if SB_CIMx_PARAMETER == 0\r
+ cimSpreadSpectrum = cimSpreadSpectrumDefault;\r
+ cimSpreadSpectrumType = cimSpreadSpectrumTypeDefault;\r
+#endif\r
+ programSbAcpiMmioTbl ((AcpiRegWrite*) FIXUP_PTR (&sbPmioEPostInitTable[0]));\r
+\r
+ // CallBackToOEM (PULL_UP_PULL_DOWN_SETTINGS, NULL, pConfig);\r
+\r
+ if ( cimSpreadSpectrum ) {\r
+ // Misc_Reg_40[25]=1 -> allow to change spread profile\r
+ // Misc_Reg19=83 -> new spread profile\r
+ // Misc_Reg[12:10]=9975be\r
+ // Misc_Reg0B=91\r
+ // Misc_Reg09=21\r
+ // Misc_Misc_Reg_08[0]=1 -> enable spread\r
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x43, AccWidthUint8, ~BIT1, BIT1);\r
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x19, AccWidthUint8, 0, 0x83);\r
+ getChipSysMode (&dbPortStatus);\r
+ if ( ((dbPortStatus & ChipSysIntClkGen) != ChipSysIntClkGen) ) {\r
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x1A, AccWidthUint8, ~(BIT5 + BIT6 + BIT7), 0x80);\r
+ }\r
+\r
+ if ( cimSpreadSpectrumType == 0 ) {\r
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x12, AccWidthUint8, 0, 0x99);\r
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x11, AccWidthUint8, 0, 0x75);\r
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccWidthUint8, 0, 0xBE);\r
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x0B, AccWidthUint8, 0, 0x91);\r
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x09, AccWidthUint8, 0, 0x21);\r
+ } else { // Spread profile for Ontario CPU related platform\r
+ // This spread profile setting is for Ontario HDMI & DVI output from DP with -0.425%\r
+ // Misc_Reg[12:10]=828FA8\r
+ // Misc_Reg0B=11\r
+ // Misc_Reg09=21\r
+ // Misc_Reg10[25:24]=01b\r
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x12, AccWidthUint8, 0, 0x82);\r
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x11, AccWidthUint8, 0, 0x8F);\r
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x10, AccWidthUint8, 0, 0xA8);\r
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x0B, AccWidthUint8, 0, 0x11);\r
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x09, AccWidthUint8, 0, 0x21);\r
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x13, AccWidthUint8, 0xFC, 0x1);\r
+ }\r
+\r
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG08, AccWidthUint8, 0xFE, 0x01);\r
+ } else {\r
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG08, AccWidthUint8, 0xFE, 0x00);\r
+ }\r
+\r
+ // RPR PLL 100Mhz Reference Clock Buffer setting for internal clock generator mode\r
+ getChipSysMode (&dbPortStatus);\r
+ if ( ((dbPortStatus & ChipSysIntClkGen) == ChipSysIntClkGen) ) {\r
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG04 + 1, AccWidthUint8, ~BIT5, BIT5);\r
+ }\r
+\r
+ // Set ASF SMBUS master function enabled here (temporary)\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG28, AccWidthUint16 | S3_SAVE, ~(BIT0 + BIT2), BIT0 + BIT2);\r
+\r
+ programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr));\r
+#ifndef NO_EC_SUPPORT\r
+ // Software IMC enable\r
+ if (((pConfig->BuildParameters.ImcEnableOverWrite == 1) && ((dbPortStatus & ChipSysEcEnable) == 0)) || ((pConfig->BuildParameters.ImcEnableOverWrite == 2) && ((dbPortStatus & ChipSysEcEnable) == ChipSysEcEnable))) {\r
+ if (validateImcFirmware (pConfig)) {\r
+ softwareToggleImcStrapping (pConfig);\r
+ } else {\r
+ CallBackToOEM (IMC_FIRMWARE_FAIL, 0, pConfig);\r
+ }\r
+ }\r
+#endif\r
+\r
+}\r
+/**\r
+ * abLinkInitBeforePciEnum - Set ABCFG registers before PCI emulation.\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+abLinkInitBeforePciEnum (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT32 cimResetCpuOnSyncFlood;\r
+ ABTBLENTRY *pAbTblPtr;\r
+ AMDSBCFG* Temp;\r
+\r
+ cimResetCpuOnSyncFlood = pConfig->ResetCpuOnSyncFlood;\r
+#if SB_CIMx_PARAMETER == 0\r
+ cimResetCpuOnSyncFlood = cimResetCpuOnSyncFloodDefault;\r
+#endif\r
+ Temp = pConfig;\r
+ if ( pConfig->SbPcieOrderRule ) {\r
+ pAbTblPtr = (ABTBLENTRY *) FIXUP_PTR (&SbPcieOrderRule[0]);\r
+ abcfgTbl (pAbTblPtr);\r
+ }\r
+ pAbTblPtr = (ABTBLENTRY *) FIXUP_PTR (&abTblEntry800[0]);\r
+ abcfgTbl (pAbTblPtr);\r
+ if ( cimResetCpuOnSyncFlood ) {\r
+ rwAlink (SB_ABCFG_REG10050 | (UINT32) (ABCFG << 29), ~BIT2, BIT2);\r
+ }\r
+}\r
+\r
+/**\r
+ * abcfgTbl - Program ABCFG by input table.\r
+ *\r
+ *\r
+ * @param[in] pABTbl ABCFG config table.\r
+ *\r
+ */\r
+VOID\r
+abcfgTbl (\r
+ IN ABTBLENTRY* pABTbl\r
+ )\r
+{\r
+ UINT32 ddValue;\r
+\r
+ while ( (pABTbl->regType) != 0xFF ) {\r
+ if ( pABTbl->regType > AXINDC ) {\r
+ ddValue = pABTbl->regIndex | (pABTbl->regType << 29);\r
+ writeAlink (ddValue, ((readAlink (ddValue)) & (0xFFFFFFFF^ (pABTbl->regMask))) | pABTbl->regData);\r
+ } else {\r
+ ddValue = 0x30 | (pABTbl->regType << 29);\r
+ writeAlink (ddValue, pABTbl->regIndex);\r
+ ddValue = 0x34 | (pABTbl->regType << 29);\r
+ writeAlink (ddValue, ((readAlink (ddValue)) & (0xFFFFFFFF^ (pABTbl->regMask))) | pABTbl->regData);\r
+ }\r
+ ++pABTbl;\r
+ }\r
+\r
+ //Clear ALink Access Index\r
+ ddValue = 0;\r
+ WriteIO (ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &ddValue);\r
+}\r
+\r
+/**\r
+ * commonInitLateBoot - Prepare Southbridge register setting to boot to OS.\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+commonInitLateBoot (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT8 dbValue;\r
+ UINT32 ddVar;\r
+ // We need to do the following setting in late post also because some bios core pci enumeration changes these values\r
+ // programmed during early post.\r
+ // RPR 4.5 Master Latency Timer\r
+\r
+ dbValue = 0x40;\r
+ WritePCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG0D, AccWidthUint8, &dbValue);\r
+ WritePCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG1B, AccWidthUint8, &dbValue);\r
+\r
+ //SB P2P AutoClock control settings.\r
+ ddVar = (pConfig->PcibAutoClkCtrlHigh << 16) | (pConfig->PcibAutoClkCtrlLow);\r
+ WritePCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG4C, AccWidthUint32, &ddVar);\r
+ ddVar = (pConfig->PcibClkStopOverride);\r
+ RWPCI ((PCIB_BUS_DEV_FUN << 16) + SB_PCIB_REG50, AccWidthUint16, 0x3F, (UINT16) (ddVar << 6));\r
+\r
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBB, AccWidthUint8, 0xBF | S3_SAVE, BIT3 + BIT4 + BIT5);\r
+\r
+ // USB Phy Calibration Adjustment\r
+ ddVar = (USB1_EHCI_BUS_DEV_FUN << 16);\r
+ sbUsbPhySetting (ddVar);\r
+ ddVar = (USB2_EHCI_BUS_DEV_FUN << 16);\r
+ sbUsbPhySetting (ddVar);\r
+ ddVar = (USB3_EHCI_BUS_DEV_FUN << 16);\r
+ sbUsbPhySetting (ddVar);\r
+ \r
+ c3PopupSetting (pConfig);\r
+ FusionRelatedSetting (pConfig);\r
+}\r
+\r
+/**\r
+ * sbUsbPhySetting - USB Phy Calibration Adjustment\r
+ *\r
+ *\r
+ * @param[in] Value Controller PCI config address (bus# + device# + function#)\r
+ *\r
+ */\r
+VOID\r
+sbUsbPhySetting (\r
+ IN UINT32 Value\r
+ )\r
+{\r
+ UINT32 ddBarAddress;\r
+ UINT32 ddPhyStatus03;\r
+ UINT32 ddPhyStatus4;\r
+ UINT8 dbRevId;\r
+ //Get BAR address\r
+ ReadPCI ((UINT32) Value + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress);\r
+ if ( (ddBarAddress != - 1) && (ddBarAddress != 0) ) {\r
+ ReadMEM ( ddBarAddress + SB_EHCI_BAR_REGA8, AccWidthUint32, &ddPhyStatus03);\r
+ ReadMEM ( ddBarAddress + SB_EHCI_BAR_REGAC, AccWidthUint32, &ddPhyStatus4);\r
+ ddPhyStatus03 &= 0x07070707;\r
+ ddPhyStatus4 &= 0x00000007;\r
+ if ( (ddPhyStatus03 != 0x00) | (ddPhyStatus4 != 0x00) ) {\r
+ // RPR 7.7 USB 2.0 Ports Driving Strength step 1\r
+ //Make BAR registers of smbus visible.\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, 0);\r
+ ReadPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG08, AccWidthUint8, &dbRevId);\r
+ //Make BAR registers of smbus invisible.\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, BIT6);\r
+ if (dbRevId == 0x41) { // A12\r
+ RWMEM (ddBarAddress + SB_EHCI_BAR_REGC0, AccWidthUint32, 0xFFFF00FF, 0x1500);\r
+ RWMEM (ddBarAddress + SB_EHCI_BAR_REGC4, AccWidthUint32, 0xFFFFF0FF, 0);\r
+ } else if (dbRevId == 0x42) { // A13\r
+ RWMEM (ddBarAddress + SB_EHCI_BAR_REGC0, AccWidthUint32, 0xFFFF00FF, 0x0F00);\r
+ RWMEM (ddBarAddress + SB_EHCI_BAR_REGC4, AccWidthUint32, 0xFFFFF0FF, 0x0100);\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * hpetInit - Program Southbridge HPET function\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ * @param[in] pStaticOptions Platform build configuration table.\r
+ *\r
+ */\r
+VOID\r
+hpetInit (\r
+ IN AMDSBCFG* pConfig,\r
+ IN BUILDPARAM *pStaticOptions\r
+ )\r
+{\r
+ DESCRIPTION_HEADER* pHpetTable;\r
+ UINT8 cimHpetTimer;\r
+ UINT8 cimHpetMsiDis;\r
+\r
+ cimHpetTimer = (UINT8) pConfig->HpetTimer;\r
+ cimHpetMsiDis = (UINT8) pConfig->HpetMsiDis;\r
+#if SB_CIMx_PARAMETER == 0\r
+ cimHpetTimer = cimHpetTimerDefault;\r
+ cimHpetMsiDis = cimHpetMsiDisDefault;\r
+#endif\r
+ pHpetTable = NULL;\r
+ if ( cimHpetTimer == TRUE ) {\r
+ //Program the HPET BAR address\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFF800, pStaticOptions->HpetBase);\r
+ //Enabling decoding of HPET MMIO\r
+ //Enable HPET MSI support\r
+ //Enable High Precision Event Timer (also called Multimedia Timer) interrupt\r
+ if ( cimHpetMsiDis == FALSE ) {\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFF800, BIT0 + BIT1 + BIT2 + BIT3 + BIT4);\r
+ } else {\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFF800, BIT0 + BIT1);\r
+ }\r
+\r
+ } else {\r
+ if ( ! (pConfig->S3Resume) ) {\r
+ //pHpetTable = (DESCRIPTION_HEADER*) ACPI_LocateTable ('TEPH'); //gcc multi-character character constant warning\r
+ pHpetTable = (DESCRIPTION_HEADER*) ACPI_LocateTable (0x54455048);//'TEPH'\r
+ }\r
+ if ( pHpetTable != NULL ) {\r
+ //pHpetTable->Signature = 'HPET';\r
+ pHpetTable->Signature = 0x48504554; //'HPET'\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * c3PopupSetting - Program Southbridge C state function\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+c3PopupSetting (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ AMDSBCFG* Temp;\r
+ UINT8 dbValue;\r
+ Temp = pConfig;\r
+ //RPR C-State and VID/FID Change\r
+ dbValue = getNumberOfCpuCores ();\r
+ if (dbValue > 1) {\r
+ //PM 0x80[2]=1, For system with dual core CPU, set this bit to 1 to automatically clear BM_STS when the C3 state is being initiated.\r
+ //PM 0x80[1]=1, For system with dual core CPU, set this bit to 1 and BM_STS will cause C3 to wakeup regardless of BM_RLD\r
+ //PM 0x7E[6]=1, Enable pop-up for C3. For internal bus mastering or BmReq# from the NB, the SB will de-assert\r
+ //LDTSTP# (pop-up) to allow DMA traffic, then assert LDTSTP# again after some idle time.\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint8 | S3_SAVE, ~(BIT1 + BIT2), (BIT1 + BIT2));\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7E, AccWidthUint8 | S3_SAVE, ~BIT6, BIT6);\r
+ }\r
+ //SB800 needs to changed for RD790 support\r
+ //PM 0x80 [8] = 0 for system with RS780\r
+ //Note: RS690 north bridge has AllowLdtStop built for both display and PCIE traffic to wake up the HT link.\r
+ //BmReq# needs to be ignored otherwise may cause LDTSTP# not to toggle.\r
+ //PM_IO 0x80[3]=1, Ignore BM_STS_SET message from NB\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG80, AccWidthUint16 | S3_SAVE, ~(BIT9 + BIT8 + BIT7 + BIT4 + BIT3 + BIT2 + BIT1 + BIT0), 0x21F);\r
+ //LdtStartTime = 10h for minimum LDTSTP# de-assertion duration of 16us in StutterMode. This is to guarantee that\r
+ //the HT link has been safely reconnected before it can be disconnected again. If C3 pop-up is enabled, the 16us also\r
+ //serves as the minimum idle time before LDTSTP# can be asserted again. This allows DMA to finish before the HT\r
+ //link is disconnected.\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94 + 2, AccWidthUint8, 0, 0x10);\r
+\r
+ //This setting provides 16us delay before the assertion of LDTSTOP# when C3 is entered. The\r
+ //delay will allow USB DMA to go on in a continuous manner\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG98 + 1, AccWidthUint8, 0, 0x10);\r
+ // Not in the RPR so far, it's hand writing from ASIC\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7C, AccWidthUint8 | S3_SAVE, 0, 0x85);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7C + 1, AccWidthUint8 | S3_SAVE, 0, 0x01);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG7E + 1, AccWidthUint8 | S3_SAVE, ~(BIT7 + BIT5), BIT7 + BIT5);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88 + 1, AccWidthUint8 | S3_SAVE, ~BIT4, BIT4);\r
+ // RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG94, AccWidthUint8, 0, 0x10);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG98 + 3, AccWidthUint8, 0, 0x10);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGB4 + 1, AccWidthUint8, 0, 0x0B);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8 | S3_SAVE, 0xFF, BIT4);\r
+ if (pConfig->LdtStpDisable) {\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8 | S3_SAVE, ~BIT5, 0);\r
+ }\r
+}\r
+\r
+/**\r
+ * FusionRelatedSetting - Program Fusion C related function\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+FusionRelatedSetting (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT8 cimAcDcMsg;\r
+ UINT8 cimTimerTickTrack;\r
+ UINT8 cimClockInterruptTag;\r
+ UINT8 cimOhciTrafficHanding;\r
+ UINT8 cimEhciTrafficHanding;\r
+ UINT8 cimFusionMsgCMultiCore;\r
+ UINT8 cimFusionMsgCStage;\r
+ UINT32 ddValue;\r
+\r
+ cimAcDcMsg = (UINT8) pConfig->AcDcMsg;\r
+ cimTimerTickTrack = (UINT8) pConfig->TimerTickTrack;\r
+ cimClockInterruptTag = (UINT8) pConfig->ClockInterruptTag;\r
+ cimOhciTrafficHanding = (UINT8) pConfig->OhciTrafficHanding;\r
+ cimEhciTrafficHanding = (UINT8) pConfig->EhciTrafficHanding;\r
+ cimFusionMsgCMultiCore = (UINT8) pConfig->FusionMsgCMultiCore;\r
+ cimFusionMsgCStage = (UINT8) pConfig->FusionMsgCStage;\r
+#if SB_CIMx_PARAMETER == 0\r
+ cimAcDcMsg = cimAcDcMsgDefault;\r
+ cimTimerTickTrack = cimTimerTickTrackDefault;\r
+ cimClockInterruptTag = cimClockInterruptTagDefault;\r
+ cimOhciTrafficHanding = cimOhciTrafficHandingDefault;\r
+ cimEhciTrafficHanding = cimEhciTrafficHandingDefault;\r
+ cimFusionMsgCMultiCore = cimFusionMsgCMultiCoreDefault;\r
+ cimFusionMsgCStage = cimFusionMsgCStageDefault;\r
+#endif\r
+ ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGA0, AccWidthUint32 | S3_SAVE, &ddValue);\r
+ ddValue = ddValue & 0xC07F00A0;\r
+ if ( cimAcDcMsg ) {\r
+ ddValue = ddValue | BIT0;\r
+ }\r
+ if ( cimTimerTickTrack ) {\r
+ ddValue = ddValue | BIT1;\r
+ }\r
+ if ( cimClockInterruptTag ) {\r
+ ddValue = ddValue | BIT10;\r
+ }\r
+ if ( cimOhciTrafficHanding ) {\r
+ ddValue = ddValue | BIT13;\r
+ }\r
+ if ( cimEhciTrafficHanding ) {\r
+ ddValue = ddValue | BIT15;\r
+ }\r
+ if ( cimFusionMsgCMultiCore ) {\r
+ ddValue = ddValue | BIT23;\r
+ }\r
+ if ( cimFusionMsgCStage ) {\r
+ ddValue = (ddValue | (BIT6 + BIT4 + BIT3 + BIT2));\r
+ }\r
+ WriteMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGA0, AccWidthUint32 | S3_SAVE, &ddValue);\r
+}\r
+#ifndef NO_EC_SUPPORT\r
+/**\r
+ * validateImcFirmware - Validate IMC Firmware.\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ * @retval TRUE Pass\r
+ * @retval FALSE Failed\r
+ */\r
+BOOLEAN\r
+validateImcFirmware (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT32 ImcSig;\r
+ UINT32 ImcSigAddr;\r
+ UINT32 ImcAddr;\r
+ UINT32 CurAddr;\r
+ UINT32 ImcBinSig0;\r
+ UINT32 ImcBinSig1;\r
+ UINT16 ImcBinSig2;\r
+ UINT8 dbIMCChecksume;\r
+ UINT8 dbIMC;\r
+ ImcAddr = 0;\r
+\r
+ // Software IMC enable\r
+ ImcSigAddr = 0x80000; // start from 512k to 64M\r
+ ImcSig = 0x0; //\r
+ while ( ( ImcSig != 0x55aa55aa ) && ( ImcSigAddr <= 0x4000000 ) ) {\r
+ CurAddr = 0xffffffff - ImcSigAddr + 0x20001;\r
+ ReadMEM (CurAddr, AccWidthUint32, &ImcSig);\r
+ ReadMEM ((CurAddr + 4), AccWidthUint32, &ImcAddr);\r
+ ImcSigAddr <<= 1;\r
+ }\r
+\r
+ dbIMCChecksume = 0xff;\r
+ if ( ImcSig == 0x55aa55aa ) {\r
+ // "_AMD_IMC_C" at offset 0x2000 of the binary\r
+ ReadMEM ((ImcAddr + 0x2000), AccWidthUint32, &ImcBinSig0);\r
+ ReadMEM ((ImcAddr + 0x2004), AccWidthUint32, &ImcBinSig1);\r
+ ReadMEM ((ImcAddr + 0x2008), AccWidthUint16, &ImcBinSig2);\r
+ if ((ImcBinSig0 == 0x444D415F) && (ImcBinSig1 == 0x434D495F) && (ImcBinSig2 == 0x435F) ) {\r
+ dbIMCChecksume = 0;\r
+ for ( CurAddr = ImcAddr; CurAddr < ImcAddr + 0x10000; CurAddr++ ) {\r
+ ReadMEM (CurAddr, AccWidthUint8, &dbIMC);\r
+ dbIMCChecksume = dbIMCChecksume + dbIMC;\r
+ }\r
+ }\r
+ }\r
+ if ( dbIMCChecksume ) {\r
+ return FALSE;\r
+ } else {\r
+ return TRUE;\r
+ }\r
+}\r
+\r
+/**\r
+ * softwareToggleImcStrapping - Software Toggle IMC Firmware Strapping.\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+softwareToggleImcStrapping (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT8 dbValue;\r
+ UINT8 dbPortStatus;\r
+ UINT32 abValue;\r
+ UINT32 abValue1;\r
+\r
+ getChipSysMode (&dbPortStatus);\r
+\r
+ ReadPMIO (SB_PMIOA_REGBF, AccWidthUint8, &dbValue);\r
+ //if ( (dbValue & (BIT6 + BIT7)) != 0xC0 ) { // PwrGoodOut =1, PwrGoodEnB=1\r
+ //The strapStatus register is not mapped into StrapOveride not in the same bit position. The following is difference.\r
+\r
+ //StrapStatus StrapOverride\r
+ // bit4 bit17\r
+ // bit6 bit12\r
+ // bit12 bit15\r
+ // bit15 bit16\r
+ // bit16 bit18\r
+ ReadMEM ((ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80), AccWidthUint32, &abValue);\r
+ abValue1 = abValue;\r
+ if (abValue & BIT4) {\r
+ abValue1 = (abValue1 & ~BIT4) | BIT17;\r
+ }\r
+ if (abValue & BIT6) {\r
+ abValue1 = (abValue1 & ~BIT6) | BIT12;\r
+ }\r
+ if (abValue & BIT12) {\r
+ abValue1 = (abValue1 & ~BIT12) | BIT15;\r
+ }\r
+ if (abValue & BIT15) {\r
+ abValue1 = (abValue1 & ~BIT15) | BIT16;\r
+ }\r
+ if (abValue & BIT16) {\r
+ abValue1 = (abValue1 & ~BIT16) | BIT18;\r
+ }\r
+ abValue1 |= BIT31; // Overwrite enable\r
+ if ((dbPortStatus & ChipSysEcEnable) == 0) {\r
+ abValue1 |= BIT2; // bit2- EcEnableStrap\r
+ } else {\r
+ abValue1 &= ~BIT2; // bit2=0 EcEnableStrap\r
+ }\r
+ WriteMEM ((ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG84), AccWidthUint32, &abValue1);\r
+ dbValue |= BIT6; // PwrGoodOut =1\r
+ dbValue &= ~BIT7; // PwrGoodEnB =0\r
+ WritePMIO (SB_PMIOA_REGBF, AccWidthUint8, &dbValue);\r
+\r
+ dbValue = 06;\r
+ WriteIO (0xcf9, AccWidthUint8, &dbValue);\r
+ SbStall (0xffffffff);\r
+}\r
+#endif\r
+\r
+#ifndef NO_HWM_SUPPORT\r
+/**\r
+ * validateImcFirmware - Validate IMC Firmware.\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+hwmInit (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xB2, AccWidthUint8 | S3_SAVE, 0, 0x55);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xB3, AccWidthUint8 | S3_SAVE, 0, 0x55);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x91, AccWidthUint8 | S3_SAVE, 0, 0x55);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x92, AccWidthUint8 | S3_SAVE, 0, 0x55);\r
+\r
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x00, AccWidthUint8 | S3_SAVE, 0, 0x06);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x10, AccWidthUint8 | S3_SAVE, 0, 0x06);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x20, AccWidthUint8 | S3_SAVE, 0, 0x06);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x30, AccWidthUint8 | S3_SAVE, 0, 0x06);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x40, AccWidthUint8 | S3_SAVE, 0, 0x06);\r
+\r
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x66, AccWidthUint8 | S3_SAVE, 0, 0x01);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x6B, AccWidthUint8 | S3_SAVE, 0, 0x01);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x70, AccWidthUint8 | S3_SAVE, 0, 0x01);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x75, AccWidthUint8 | S3_SAVE, 0, 0x01);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0x7A, AccWidthUint8 | S3_SAVE, 0, 0x01);\r
+\r
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xF8, AccWidthUint8 | S3_SAVE, 0, 0x05);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xF9, AccWidthUint8 | S3_SAVE, 0, 0x06);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xFF, AccWidthUint8 | S3_SAVE, 0, 0x42);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xE9, AccWidthUint8 | S3_SAVE, 0, 0xFF);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xEB, AccWidthUint8 | S3_SAVE, 0, 0x1F);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xEF, AccWidthUint8 | S3_SAVE, 0, 0x04);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO2_BASE + 0xFB, AccWidthUint8 | S3_SAVE, 0, 0x00);\r
+}\r
+#endif\r
--- /dev/null
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+\r
+\r
+//AMD Library Routines (AMDLIB.C)\r
+UINT8 getNumberOfCpuCores (OUT VOID);\r
+UINT32 readAlink (IN UINT32 Index);\r
+VOID writeAlink (IN UINT32 Index, IN UINT32 Data);\r
+VOID rwAlink (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask);\r
+\r
+//AMD Library Routines (LEGACY.C)\r
+UINT32 GetFixUp (OUT VOID);\r
+\r
+//AMD Library Routines (IOLIB.C)\r
+VOID ReadIO (IN UINT16 Address, IN UINT8 OpFlag, IN VOID *Value);\r
+VOID WriteIO (IN UINT16 Address, IN UINT8 OpFlag, IN VOID *Value);\r
+VOID RWIO (IN UINT16 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data);\r
+\r
+\r
+\r
+//AMD Library Routines (MEMLIB.C)\r
+VOID ReadMEM (IN UINT32 Address, IN UINT8 OpFlag, IN VOID* Value);\r
+VOID WriteMEM (IN UINT32 Address, IN UINT8 OpFlag, IN VOID* Value);\r
+VOID RWMEM (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data);\r
+\r
+//AMD Library Routines (PCILIB.C)\r
+VOID ReadPCI (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value);\r
+VOID WritePCI (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value);\r
+VOID RWPCI (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data);\r
+\r
+//AMD Library Routines (SBPELIB.C)\r
+/**\r
+ * Read Southbridge Revision ID cie Base\r
+ *\r
+ *\r
+ * @retval 0xXXXXXXXX Revision ID\r
+ *\r
+ */\r
+UINT8 getRevisionID (OUT VOID);\r
+\r
+/**\r
+ * programPciByteTable - Program PCI register by table (8 bits data)\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pPciByteTable - Table data pointer\r
+ * @param[in] dwTableSize - Table length\r
+ *\r
+ */\r
+VOID programPciByteTable (IN REG8MASK* pPciByteTable, IN UINT16 dwTableSize);\r
+\r
+/**\r
+ * programSbAcpiMmioTbl - Program SB ACPI MMIO register by table (8 bits data)\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pAcpiTbl - Table data pointer\r
+ *\r
+ */\r
+VOID programSbAcpiMmioTbl (IN AcpiRegWrite *pAcpiTbl);\r
+\r
+/**\r
+ * getChipSysMode - Get Chip status\r
+ *\r
+ *\r
+ * @param[in] Value - Return Chip strap status\r
+ * StrapStatus [15.0] - SB800 chip Strap Status\r
+ * @li <b>0001</b> - Not USED FWH\r
+ * @li <b>0002</b> - Not USED LPC ROM\r
+ * @li <b>0004</b> - EC enabled\r
+ * @li <b>0008</b> - Reserved\r
+ * @li <b>0010</b> - Internal Clock mode\r
+ *\r
+ */\r
+VOID getChipSysMode (IN VOID* Value);\r
+\r
+/**\r
+ * Read Southbridge CIMx configuration structure pointer\r
+ *\r
+ *\r
+ *\r
+ * @retval 0xXXXXXXXX CIMx configuration structure pointer.\r
+ *\r
+ */\r
+AMDSBCFG* getConfigPointer (OUT VOID);\r
+\r
+//AMD Library Routines (PMIOLIB.C)\r
+/**\r
+ * Read PMIO\r
+ *\r
+ *\r
+ *\r
+ * @param[in] Address - PMIO Offset value\r
+ * @param[in] OpFlag - Access sizes\r
+ * @param[in] Value - Read Data Buffer\r
+ *\r
+ */\r
+VOID ReadPMIO (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value);\r
+\r
+/**\r
+ * Write PMIO\r
+ *\r
+ *\r
+ *\r
+ * @param[in] Address - PMIO Offset value\r
+ * @param[in] OpFlag - Access sizes\r
+ * @param[in] Value - Write Data Buffer\r
+ *\r
+ */\r
+VOID WritePMIO (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value);\r
+\r
+/**\r
+ * RWPMIO - Read/Write PMIO\r
+ *\r
+ *\r
+ *\r
+ * @param[in] Address - PMIO Offset value\r
+ * @param[in] OpFlag - Access sizes\r
+ * @param[in] AndMask - Data And Mask 32 bits\r
+ * @param[in] OrMask - Data OR Mask 32 bits\r
+ *\r
+ */\r
+VOID RWPMIO (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask);\r
+\r
+//AMD Library Routines (PMIO2LIB.C)\r
+\r
+/**\r
+ * Read PMIO2\r
+ *\r
+ *\r
+ *\r
+ * @param[in] Address - PMIO2 Offset value\r
+ * @param[in] OpFlag - Access sizes\r
+ * @param[in] Value - Read Data Buffer\r
+ *\r
+ */\r
+VOID ReadPMIO2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value);\r
+\r
+/**\r
+ * Write PMIO 2\r
+ *\r
+ *\r
+ *\r
+ * @param[in] Address - PMIO2 Offset value\r
+ * @param[in] OpFlag - Access sizes\r
+ * @param[in] Value - Write Data Buffer\r
+ *\r
+ */\r
+VOID WritePMIO2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value);\r
+\r
+/**\r
+ * RWPMIO2 - Read/Write PMIO2\r
+ *\r
+ *\r
+ *\r
+ * @param[in] Address - PMIO2 Offset value\r
+ * @param[in] OpFlag - Access sizes\r
+ * @param[in] AndMask - Data And Mask 32 bits\r
+ * @param[in] OrMask - Data OR Mask 32 bits\r
+ *\r
+ */\r
+VOID RWPMIO2 (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask);\r
+//AMD Library Routines (ECLIB.C)\r
+// ECLIB Routines\r
+\r
+// #ifndef NO_EC_SUPPORT\r
+\r
+/**\r
+ * EnterEcConfig - Force EC into Config mode\r
+ *\r
+ *\r
+ *\r
+ *\r
+ */\r
+VOID EnterEcConfig (VOID);\r
+\r
+/**\r
+ * ExitEcConfig - Force EC exit Config mode\r
+ *\r
+ *\r
+ *\r
+ *\r
+ */\r
+VOID ExitEcConfig (VOID);\r
+\r
+/**\r
+ * ReadEC8 - Read EC register data\r
+ *\r
+ *\r
+ *\r
+ * @param[in] Address - EC Register Offset Value\r
+ * @param[in] Value - Read Data Buffer\r
+ *\r
+ */\r
+VOID ReadEC8 (IN UINT8 Address, IN UINT8* Value);\r
+\r
+/**\r
+ * WriteEC8 - Write date into EC register\r
+ *\r
+ *\r
+ *\r
+ * @param[in] Address - EC Register Offset Value\r
+ * @param[in] Value - Write Data Buffer\r
+ *\r
+ */\r
+VOID WriteEC8 (IN UINT8 Address, IN UINT8* Value);\r
+\r
+/**\r
+ * RWEC8 - Read/Write EC register\r
+ *\r
+ *\r
+ *\r
+ * @param[in] Address - EC Register Offset Value\r
+ * @param[in] AndMask - Data And Mask 8 bits\r
+ * @param[in] OrMask - Data OR Mask 8 bits\r
+ *\r
+ */\r
+VOID RWEC8 (IN UINT8 Address, IN UINT8 AndMask, IN UINT8 OrMask);\r
+\r
+/**\r
+ * IsZoneFuncEnable - check every zone support function with BitMap from user define\r
+ *\r
+ */\r
+BOOLEAN IsZoneFuncEnable ( UINT16 Flag, UINT8 func, UINT8 Zone);\r
+\r
+VOID sbECfancontrolservice (IN AMDSBCFG* pConfig);\r
+VOID SBIMCFanInitializeS3 (VOID);\r
+VOID GetSbAcpiMmioBase (OUT UINT32* AcpiMmioBase);\r
+VOID GetSbAcpiPmBase (OUT UINT16* AcpiPmBase);\r
+\r
+// #endif\r
+\r
--- /dev/null
+/**\r
+ * @file\r
+ *\r
+ * SB Initialization.\r
+ *\r
+ * Init IOAPIC/IOMMU/Misc NB features.\r
+ *\r
+ * @xrefitem bom "File Content Label" "Release Content"\r
+ * @e project: CIMx-SB\r
+ * @e sub-project:\r
+ * @e \$Revision:$ @e \$Date:$\r
+ *\r
+ */\r
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+\r
+#include "SBPLATFORM.h"\r
+\r
+#ifndef B1_IMAGE\r
+\r
+/*----------------------------------------------------------------------------------------*/\r
+/**\r
+ * sbBeforePciInit - Config Southbridge before PCI emulation\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+\r
+VOID\r
+sbBeforePciInit (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ commonInitEarlyBoot (pConfig);\r
+ commonInitEarlyPost (pConfig);\r
+#ifndef NO_EC_SUPPORT\r
+ ecInitBeforePciEnum (pConfig);\r
+#endif\r
+ usbInitBeforePciEnum (pConfig); // USB POST TIME Only\r
+ sataInitBeforePciEnum (pConfig); // Init SATA class code and PHY\r
+ gecInitBeforePciEnum (pConfig); // Init GEC\r
+ azaliaInitBeforePciEnum (pConfig); // Detect and configure High Definition Audio\r
+ sbPcieGppEarlyInit (pConfig); // Gpp port init\r
+ abSpecialSetBeforePciEnum (pConfig);\r
+ usbDesertPll (pConfig);\r
+}\r
+\r
+/**\r
+ * sbAfterPciInit - Config Southbridge after PCI emulation\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+sbAfterPciInit (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ usbInitAfterPciInit (pConfig); // Init USB MMIO\r
+ sataInitAfterPciEnum (pConfig); // SATA port enumeration\r
+ gecInitAfterPciEnum (pConfig);\r
+ azaliaInitAfterPciEnum (pConfig); // Detect and configure High Definition Audio\r
+\r
+#ifndef NO_HWM_SUPPORT\r
+ hwmInit (pConfig);\r
+#endif\r
+}\r
+\r
+/**\r
+ * sbMidPostInit - Config Southbridge during middle of POST\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+sbMidPostInit (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ sataInitMidPost (pConfig);\r
+}\r
+\r
+/*----------------------------------------------------------------------------------------*/\r
+/**\r
+ * sbLatePost - Prepare Southbridge to boot to OS.\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+sbLatePost (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+// UINT16 dwVar;\r
+ BUILDPARAM *pStaticOptions;\r
+ pStaticOptions = &(pConfig->BuildParameters);\r
+ commonInitLateBoot (pConfig);\r
+ sataInitLatePost (pConfig);\r
+ gecInitLatePost (pConfig);\r
+ hpetInit (pConfig, pStaticOptions); // SB Configure HPET base and enable bit\r
+#ifndef NO_EC_SUPPORT\r
+ ecInitLatePost (pConfig);\r
+#endif\r
+ sbPcieGppLateInit (pConfig);\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------------------*/\r
+/**\r
+ * sbBeforePciRestoreInit - Config Southbridge before ACPI S3 resume PCI config device restore\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+\r
+VOID\r
+sbBeforePciRestoreInit (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ pConfig->S3Resume = 1;\r
+ commonInitEarlyBoot (pConfig); // set /SMBUS/ACPI/IDE/LPC/PCIB\r
+ abLinkInitBeforePciEnum (pConfig); // Set ABCFG registers\r
+ usbInitBeforePciEnum (pConfig); // USB POST TIME Only\r
+ sataInitBeforePciEnum (pConfig);\r
+ gecInitBeforePciEnum (pConfig); // Init GEC\r
+ azaliaInitBeforePciEnum (pConfig); // Detect and configure High Definition Audio\r
+ sbPcieGppEarlyInit (pConfig); // Gpp port init\r
+ abSpecialSetBeforePciEnum (pConfig);\r
+}\r
+\r
+/*----------------------------------------------------------------------------------------*/\r
+/**\r
+ * sbAfterPciRestoreInit - Config Southbridge after ACPI S3 resume PCI config device restore\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+\r
+VOID\r
+sbAfterPciRestoreInit (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ BUILDPARAM *pStaticOptions;\r
+\r
+ pConfig->S3Resume = 1;\r
+\r
+ usbSetPllDuringS3 (pConfig);\r
+ pStaticOptions = &(pConfig->BuildParameters);\r
+ commonInitLateBoot (pConfig);\r
+ sataInitAfterPciEnum (pConfig);\r
+ gecInitAfterPciEnum (pConfig);\r
+ azaliaInitAfterPciEnum (pConfig); // Detect and configure High Definition Audio\r
+ hpetInit (pConfig, pStaticOptions); // SB Configure HPET base and enable bit\r
+ sataInitLatePost (pConfig);\r
+ c3PopupSetting (pConfig);\r
+\r
+#ifndef NO_HWM_SUPPORT\r
+ SBIMCFanInitializeS3 ();\r
+#endif\r
+}\r
+\r
+/*----------------------------------------------------------------------------------------*/\r
+/**\r
+ * sbSmmAcpiOn - Config Southbridge during ACPI_ON\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+sbSmmAcpiOn (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ // Commented the following code since we need to leave the IRQ1/12 filtering enabled always as per latest\r
+ // recommendation in RPR. This is required to fix the keyboard stuck issue when playing games under Windows\r
+ AMDSBCFG* pTmp; //lx-dummy for /W4 build\r
+ pTmp = pConfig;\r
+\r
+ // Disable Power Button SMI\r
+ RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGB2, AccWidthUint8, ~(BIT4 + BIT5), 0);\r
+ RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGAC, AccWidthUint8, ~(BIT6 + BIT7), 0);\r
+}\r
+\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------------------*/\r
+/**\r
+ * Call Back routine.\r
+ *\r
+ *\r
+ *\r
+ * @param[in] Func Callback ID.\r
+ * @param[in] Data Callback specific data.\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ */\r
+UINTN\r
+CallBackToOEM (\r
+ IN UINT32 Func,\r
+ IN UINT32 Data,\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT32 Result;\r
+ Result = 0;\r
+ if ( pConfig->StdHeader.CALLBACK.CalloutPtr == NULL ) return Result;\r
+ Result = (pConfig->StdHeader.CALLBACK.CalloutPtr) ( Func, Data, pConfig);\r
+\r
+ return Result;\r
+}\r
+\r
+\r
--- /dev/null
+/**\r
+ * @file\r
+ *\r
+ * Southbridge IO access common routine\r
+ *\r
+ *\r
+ *\r
+ * @xrefitem bom "File Content Label" "Release Content"\r
+ * @e project: CIMx-SB\r
+ * @e sub-project:\r
+ * @e \$Revision:$ @e \$Date:$\r
+ *\r
+ */\r
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+\r
+#include "SBPLATFORM.h"\r
+\r
+/**\r
+ * Read Southbridge Revision ID cie Base\r
+ *\r
+ *\r
+ * @retval 0xXXXXXXXX Revision ID\r
+ *\r
+ */\r
+UINT8\r
+getRevisionID (\r
+ OUT VOID\r
+ )\r
+{\r
+ UINT8 dbVar0;\r
+ ReadPCI (((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG08), AccWidthUint8, &dbVar0);\r
+ return dbVar0;\r
+}\r
+\r
+/*----------------------------------------------------------------------------------------*/\r
+/**\r
+ * programPciByteTable - Program PCI register by table (8 bits data)\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pPciByteTable - Table data pointer\r
+ * @param[in] dwTableSize - Table length\r
+ *\r
+ */\r
+VOID\r
+programPciByteTable (\r
+ IN REG8MASK* pPciByteTable,\r
+ IN UINT16 dwTableSize\r
+ )\r
+{\r
+ UINT8 i;\r
+ UINT8 dbBusNo;\r
+ UINT8 dbDevFnNo;\r
+ UINT32 ddBDFR;\r
+\r
+ dbBusNo = pPciByteTable->bRegIndex;\r
+ dbDevFnNo = pPciByteTable->bANDMask;\r
+ pPciByteTable++;\r
+\r
+ for ( i = 1; i < dwTableSize; i++ ) {\r
+ if ( (pPciByteTable->bRegIndex == 0xFF) && (pPciByteTable->bANDMask == 0xFF) && (pPciByteTable->bORMask == 0xFF) ) {\r
+ pPciByteTable++;\r
+ dbBusNo = pPciByteTable->bRegIndex;\r
+ dbDevFnNo = pPciByteTable->bANDMask;\r
+ pPciByteTable++;\r
+ i++;\r
+ } else {\r
+ ddBDFR = (dbBusNo << 24) + (dbDevFnNo << 16) + (pPciByteTable->bRegIndex) ;\r
+ RWPCI (ddBDFR, AccWidthUint8 | S3_SAVE, pPciByteTable->bANDMask, pPciByteTable->bORMask);\r
+ pPciByteTable++;\r
+ }\r
+ }\r
+}\r
+\r
+/*----------------------------------------------------------------------------------------*/\r
+/**\r
+ * programSbAcpiMmioTbl - Program SB ACPI MMIO register by table (8 bits data)\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pAcpiTbl - Table data pointer\r
+ *\r
+ */\r
+VOID\r
+programSbAcpiMmioTbl (\r
+ IN AcpiRegWrite *pAcpiTbl\r
+ )\r
+{\r
+ UINT8 i;\r
+ UINT32 ddtempVar;\r
+ if (pAcpiTbl != NULL) {\r
+ for ( i = 1; pAcpiTbl->MmioBase < 0xf0; i++ ) {\r
+ ddtempVar = 0xFED80000 | (pAcpiTbl->MmioBase) << 8 | pAcpiTbl->MmioReg;\r
+ RWMEM (ddtempVar, AccWidthUint8, ((pAcpiTbl->DataANDMask) | 0xFFFFFF00), pAcpiTbl->DataOrMask);\r
+ pAcpiTbl++;\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * getChipSysMode - Get Chip status\r
+ *\r
+ *\r
+ * @param[in] Value - Return Chip strap status\r
+ * StrapStatus [15.0] - SB800 chip Strap Status\r
+ * @li <b>0001</b> - Not USED FWH\r
+ * @li <b>0002</b> - Not USED LPC ROM\r
+ * @li <b>0004</b> - EC enabled\r
+ * @li <b>0008</b> - Reserved\r
+ * @li <b>0010</b> - Internal Clock mode\r
+ *\r
+ */\r
+VOID\r
+getChipSysMode (\r
+ IN VOID* Value\r
+ )\r
+{\r
+ ReadMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80, AccWidthUint8, Value);\r
+}\r
+\r
+/*----------------------------------------------------------------------------------------*/\r
+/**\r
+ * Read Southbridge CIMx configuration structure pointer\r
+ *\r
+ *\r
+ *\r
+ * @retval 0xXXXXXXXX CIMx configuration structure pointer.\r
+ *\r
+ */\r
+AMDSBCFG*\r
+getConfigPointer (\r
+ OUT VOID\r
+ )\r
+{\r
+ UINT8 dbReg;\r
+ UINT8 dbValue;\r
+ UINT8 i;\r
+ UINT32 ddValue;\r
+ ddValue = 0;\r
+ dbReg = SB_ECMOS_REG08;\r
+\r
+ for ( i = 0; i <= 3; i++ ) {\r
+ WriteIO (SB_IOMAP_REG72, AccWidthUint8, &dbReg);\r
+ ReadIO (SB_IOMAP_REG73, AccWidthUint8, &dbValue);\r
+ ddValue |= (dbValue << (i * 8));\r
+ dbReg++;\r
+ }\r
+ return ( (AMDSBCFG*) (UINTN)ddValue);\r
+}\r
+\r
+/**\r
+ * getEfuseStatue - Get Efuse status\r
+ *\r
+ *\r
+ * @param[in] Value - Return Chip strap status\r
+ *\r
+ */\r
+VOID\r
+getEfuseStatus (\r
+ IN VOID* Value\r
+ )\r
+{\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, ~BIT5, BIT5);\r
+ WriteMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, Value);\r
+ ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8 + 1, AccWidthUint8, Value);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, ~BIT5, 0);\r
+}\r
--- /dev/null
+\r
+/**\r
+ * @file\r
+ *\r
+ * Southbridge Init during POWER-ON\r
+ *\r
+ * Prepare Southbridge environment during power on stage.\r
+ *\r
+ * @xrefitem bom "File Content Label" "Release Content"\r
+ * @e project: CIMx-SB\r
+ * @e sub-project:\r
+ * @e \$Revision:$ @e \$Date:$\r
+ *\r
+ */\r
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+\r
+#include "SBPLATFORM.h"\r
+/**\r
+ * sbPorInitPciTable - PCI device registers initial during the power on stage.\r
+ */\r
+const static REG8MASK sbPorInitPciTable[] =\r
+{\r
+ // SATA device\r
+ {0x00, SATA_BUS_DEV_FUN, 0},\r
+ {SB_SATA_REG84 + 3, ~BIT2, 0},\r
+ {SB_SATA_REG84 + 1, ~(BIT4 + BIT5), BIT4 + BIT5},\r
+ {SB_SATA_REGA0, ~(BIT2 + BIT3 + BIT4 + BIT5 + BIT6), BIT2 + BIT3 + BIT4 + BIT5},\r
+ {0xFF, 0xFF, 0xFF},\r
+ // LPC Device (Bus 0, Dev 20, Func 3)\r
+ {0x00, LPC_BUS_DEV_FUN, 0},\r
+ {SB_LPC_REG48, 0x00, BIT0 + BIT1 + BIT2},\r
+ {SB_LPC_REG7C, 0x00, BIT0 + BIT2},\r
+ {SB_LPC_REGBB, 0xFF, BIT3 + BIT4 + BIT5},\r
+ // A12 set 0xBB [5:3] = 111 to improve SPI timing margin.\r
+ // A12 Set 0xBA [6:5] = 11 improve SPI timing margin. (SPI Prefetch enhancement)\r
+ {SB_LPC_REGBB, 0xBE, BIT0 + BIT3 + BIT4 + BIT5},\r
+ {SB_LPC_REGBA, 0x9F, BIT5 + BIT6},\r
+ {0xFF, 0xFF, 0xFF},\r
+ // P2P Bridge (Bus 0, Dev 20, Func 4)\r
+ {0x00, PCIB_BUS_DEV_FUN, 0},\r
+ {SB_PCIB_REG4B, 0xFF, BIT6 + BIT7 + BIT4},\r
+ // Enable IO but not allocate any IO range. This is for post code display on debug port behind P2P bridge.\r
+ {SB_PCIB_REG1C, 0x00, 0xF0},\r
+ {SB_PCIB_REG1D, 0x00, 0x00},\r
+ {SB_PCIB_REG04, 0x00, 0x21},\r
+ {SB_PCIB_REG40, 0xDF, 0x20},\r
+ {SB_PCIB_REG50, 0x02, 0x01},\r
+ {0xFF, 0xFF, 0xFF},\r
+};\r
+\r
+/**\r
+ * sbPmioPorInitTable - Southbridge ACPI MMIO initial during the power on stage.\r
+ */\r
+const static AcpiRegWrite sbPmioPorInitTable[] =\r
+{\r
+ {PMIO_BASE >> 8, SB_PMIOA_REG5D, 0x00, BIT0},\r
+ {PMIO_BASE >> 8, SB_PMIOA_REGD2, 0xCF, BIT4 + BIT5},\r
+ {SMBUS_BASE >> 8, SB_SMBUS_REG12, 0x00, BIT0},\r
+ {PMIO_BASE >> 8, SB_PMIOA_REG28, 0xFF, BIT0},\r
+ {PMIO_BASE >> 8, SB_PMIOA_REG44 + 3, 0x7F, BIT7},\r
+ {PMIO_BASE >> 8, SB_PMIOA_REG48, 0xFF, BIT0},\r
+ {PMIO_BASE >> 8, SB_PMIOA_REG00, 0xFF, 0x0E},\r
+ {PMIO_BASE >> 8, SB_PMIOA_REG00 + 2, 0xFF, 0x40},\r
+ {PMIO_BASE >> 8, SB_PMIOA_REG00 + 3, 0xFF, 0x08},\r
+ {PMIO_BASE >> 8, SB_PMIOA_REG34, 0xEF, BIT0 + BIT1},\r
+ {PMIO_BASE >> 8, SB_PMIOA_REGEC, 0xFD, BIT1},\r
+ {PMIO_BASE >> 8, SB_PMIOA_REG5B, 0xF9, BIT1 + BIT2},\r
+ {PMIO_BASE >> 8, SB_PMIOA_REG08, 0xFE, BIT2 + BIT4},\r
+ {PMIO_BASE >> 8, SB_PMIOA_REG08 + 1, 0xFF, BIT0},\r
+ {PMIO_BASE >> 8, SB_PMIOA_REG54, 0x00, BIT4 + BIT7},\r
+ {PMIO_BASE >> 8, SB_PMIOA_REG04 + 3, 0xFD, BIT1},\r
+ {PMIO_BASE >> 8, SB_PMIOA_REG74, 0xF6, BIT0 + BIT3},\r
+ {PMIO_BASE >> 8, SB_PMIOA_REGF0, ~BIT2, 0x00},\r
+ // RPR GEC I/O Termination Setting\r
+ // PM_Reg 0xF6 = Power-on default setting\r
+ // PM_Reg 0xF7 = Power-on default setting\r
+ // PM_Reg 0xF8 = 0x6C\r
+ // PM_Reg 0xF9 = 0x21\r
+ // PM_Reg 0xFA = 0x00 SB800 A12 GEC I/O Pad settings for 3.3V CMOS\r
+ {PMIO_BASE >> 8, SB_PMIOA_REGF8, 0x00, 0x6C},\r
+ {PMIO_BASE >> 8, SB_PMIOA_REGF8 + 1, 0x00, 0x27},\r
+ {PMIO_BASE >> 8, SB_PMIOA_REGF8 + 2, 0x00, 0x00},\r
+ {PMIO_BASE >> 8, SB_PMIOA_REGC4, 0xFE, 0x14},\r
+ {PMIO_BASE >> 8, SB_PMIOA_REGC0 + 2, 0xBF, 0x40},\r
+\r
+ {PMIO_BASE >> 8, SB_PMIOA_REGBE, 0xDF, BIT5},//ENH210907 SB800: request to no longer clear kb_pcirst_en (bit 1) of PM_Reg BEh per the RPR\r
+\r
+ {0xFF, 0xFF, 0xFF, 0xFF},\r
+};\r
+\r
+/**\r
+ * sbPowerOnInit - Config Southbridge during power on stage.\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+sbPowerOnInit (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+\r
+ UINT8 dbPortStatus;\r
+ UINT8 dbSysConfig;\r
+ UINT32 abValue;\r
+ UINT8 dbValue;\r
+ UINT8 dbEfuse;\r
+ UINT8 dbCg2WR;\r
+ UINT8 dbCg1Pll;\r
+ UINT8 cimNbSbGen2;\r
+ UINT8 cimSataMode;\r
+ UINT8 cimSpiFastReadEnable;\r
+ UINT8 cimSpiFastReadSpeed;\r
+ UINT8 SataPortNum;\r
+\r
+ cimNbSbGen2 = pConfig->NbSbGen2;\r
+ cimSataMode = pConfig->SATAMODE.SataModeReg;\r
+// Adding Fast Read Function support\r
+ if (pConfig->BuildParameters.SpiFastReadEnable != NULL ) {\r
+ cimSpiFastReadEnable = (UINT8) pConfig->BuildParameters.SpiFastReadEnable;\r
+ } else {\r
+ cimSpiFastReadEnable = cimSpiFastReadEnableDefault;\r
+ }\r
+ cimSpiFastReadSpeed = (UINT8) pConfig->BuildParameters.SpiFastReadSpeed;\r
+#if SB_CIMx_PARAMETER == 0\r
+ cimNbSbGen2 = cimNbSbGen2Default;\r
+ cimSataMode = (UINT8) ((cimSataMode & 0xFB) | cimSataSetMaxGen2Default);\r
+ cimSataMode = (UINT8) ((cimSataMode & 0x0F) | (cimSATARefClkSelDefault + cimSATARefDivSelDefault));\r
+ cimSpiFastReadEnable = cimSpiFastReadEnableDefault;\r
+ cimSpiFastReadSpeed = cimSpiFastReadSpeedDefault;\r
+#endif\r
+\r
+// SB800 Only Enabled (Mmio_mem_enablr) // Default value is correct\r
+ RWPMIO (SB_PMIOA_REG24, AccWidthUint8, 0xFF, BIT0);\r
+\r
+// Set A-Link bridge access address. This address is set at device 14h, function 0,\r
+// register 0f0h. This is an I/O address. The I/O address must be on 16-byte boundary.\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGE0, AccWidthUint32, 00, ALINK_ACCESS_INDEX);\r
+ writeAlink (0x80000004, 0x04); // RPR 4.2 Enable SB800 to issue memory read/write requests in the upstream direction\r
+ abValue = readAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29)); // RPR 4.5 Disable the credit variable in the downstream arbitration equation\r
+ abValue = abValue | BIT0;\r
+ writeAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29), abValue);\r
+ writeAlink (0x30, 0x10); // AXINDC 0x10[9]=1, Enabling Non-Posted memory write for K8 platform.\r
+ writeAlink (0x34, readAlink (0x34) | BIT9);\r
+\r
+ dbEfuse = FUSE_ID_EFUSE_LOC;\r
+ getEfuseStatus (&dbEfuse);\r
+ if ( dbEfuse == M1_D1_FUSE_ID ) {\r
+ dbEfuse = MINOR_ID_EFUSE_LOC;\r
+ getEfuseStatus (&dbEfuse);\r
+ if ( dbEfuse == M1_MINOR_ID ) {\r
+ // Limit ALink speed to 2.5G if Hudson-M1\r
+ cimNbSbGen2 = 0;\r
+ }\r
+ }\r
+// Step 1:\r
+// AXINDP_Reg 0xA4[0] = 0x1\r
+// Step 2:\r
+// AXCFG_Reg 0x88[3:0] = 0x2\r
+// Step3:\r
+// AXINDP_Reg 0xA4[18] = 0x1\r
+ if ( cimNbSbGen2 == TRUE ) {\r
+ rwAlink (SB_AX_INDXP_REGA4, 0xFFFFFFFF, BIT0);\r
+ rwAlink ((UINT32)SB_AX_CFG_REG88, 0xFFFFFFF0, 0x2);\r
+ rwAlink (SB_AX_INDXP_REGA4, 0xFFFFFFFF, BIT18);\r
+ }\r
+\r
+// Set Build option into SB\r
+ WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioPmeBaseAddress));\r
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F, (pConfig->BuildParameters.SpiRomBaseAddress));\r
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint32 | S3_SAVE, 0, (pConfig->BuildParameters.GecShadowRomBase + 1));\r
+// Enabled SMBUS0/SMBUS1 (ASF) Base Address\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG2C, AccWidthUint16, 06, (pConfig->BuildParameters.Smbus0BaseAddress) + BIT0); //protect BIT[2:1]\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG28, AccWidthUint16, 00, (pConfig->BuildParameters.Smbus1BaseAddress));\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG60, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1EvtBlkAddr));\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG62, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1CntBlkAddr));\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG64, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmTmrBlkAddr));\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG66, AccWidthUint16, 00, (pConfig->BuildParameters.CpuControlBlkAddr));\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG68, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiGpe0BlkAddr));\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6A, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr));\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6C, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmaCntBlkAddr));\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6E, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr) + 8);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG48, AccWidthUint32, 00, (pConfig->BuildParameters.WatchDogTimerBase));\r
+\r
+ dbEfuse = SATA_FIS_BASE_EFUSE_LOC;\r
+ getEfuseStatus (&dbEfuse);\r
+\r
+ programSbAcpiMmioTbl ((AcpiRegWrite*) FIXUP_PTR (&sbPmioPorInitTable[0]));\r
+\r
+\r
+ SataPortNum = 0;\r
+ for ( SataPortNum = 0; SataPortNum < 0x06; SataPortNum++ ) {\r
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, 1 << SataPortNum);\r
+ SbStall (2);\r
+ RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, (0xFF ^ (1 << SataPortNum)) , 0x00);\r
+ SbStall (2);\r
+ }\r
+\r
+\r
+ //The following bits must be set before enabling SPI prefetch.\r
+ // Set SPI MMio bit offset 00h[19] to 1 and offset 00h[26:24] to 111, offset 0ch[21:16] to 1, Set LPC cfg BBh[6] to 0 ( by default it is 0).\r
+ // if Ec is enable\r
+ // Maximum spi speed that can be supported by SB is 22M (SPI Mmio offset 0ch[13:12] to 10) if the rom can run at the speed.\r
+ // else\r
+ // Maximum spi speed that can be supported by SB is 33M (SPI Mmio offset 0ch[13:12] to 01 in normal mode or offset 0ch[15:14] in fast mode) if the rom can run at\r
+ // the speed.\r
+ getChipSysMode (&dbSysConfig);\r
+ if (pConfig->BuildParameters.SpiSpeed < 0x02) {\r
+ pConfig->BuildParameters.SpiSpeed = 0x01;\r
+ if (dbSysConfig & ChipSysEcEnable) pConfig->BuildParameters.SpiSpeed = 0x02;\r
+ }\r
+\r
+ if (pConfig->SbSpiSpeedSupport) {\r
+ RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, (BIT19 + BIT24 + BIT25 + BIT26));\r
+ RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, 0xFFC0FFFF, 1 << 16 );\r
+ RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint16 | S3_SAVE, ~(BIT13 + BIT12), (pConfig->BuildParameters.SpiSpeed << 12));\r
+ }\r
+ // SPI Fast Read Function\r
+ if ( cimSpiFastReadEnable ) {\r
+ RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFBFFFF, BIT18);\r
+ } else {\r
+ RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFBFFFF, 0x00);\r
+ }\r
+\r
+ if ( cimSpiFastReadSpeed ) {\r
+ RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint16 | S3_SAVE, ~(BIT15 + BIT14), ( cimSpiFastReadSpeed << 14));\r
+ }\r
+ //Program power on pci init table\r
+ programPciByteTable ( (REG8MASK*) FIXUP_PTR (&sbPorInitPciTable[0]), sizeof (sbPorInitPciTable) / sizeof (REG8MASK) );\r
+\r
+ programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr));\r
+\r
+ dbValue = 0x0A;\r
+ WriteIO (SB_IOMAP_REG70, AccWidthUint8, &dbValue);\r
+ ReadIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);\r
+ dbValue &= 0xEF;\r
+ WriteIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);\r
+\r
+// Change the CG PLL multiplier to x1.1\r
+ if ( pConfig->UsbRxMode !=0 ) {\r
+ dbCg2WR = 0x00;\r
+ dbCg1Pll = 0x3A;\r
+ ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, &dbCg2WR);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, 0, 0x3A);\r
+ ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD9, AccWidthUint8, &dbCg1Pll);\r
+ dbCg2WR &= BIT4;\r
+ if (( dbCg2WR == 0x00 ) && ( dbCg1Pll !=0x10 ))\r
+ {\r
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x18, AccWidthUint8, 0xE1, 0x10);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD8, AccWidthUint8, 0, 0x3A);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD9, AccWidthUint8, 0, USB_PLL_Voltage);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, 0xEF, 0x10);\r
+ dbValue = 0x06;\r
+ WriteIO (0xCF9, AccWidthUint8, &dbValue);\r
+ } else {\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8, AccWidthUint8, 0xEF, 0x00);\r
+ }\r
+ }\r
+\r
+ RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint32 | S3_SAVE, ~(pConfig->BuildParameters.BiosSize << 4), 0);\r
+\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0, (pConfig->SATAMODE.SataModeReg) & 0xFD );\r
+\r
+ if (dbEfuse & BIT0) {\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0xFB, 0x04);\r
+ }\r
+\r
+ ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, &dbPortStatus);\r
+ if ( ((dbPortStatus & 0xF0) == 0x10) ) {\r
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_PMIOA_REG08, AccWidthUint8, 0, BIT5);\r
+ }\r
+\r
+ if ( pConfig->BuildParameters.LegacyFree ) {\r
+ RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C000);\r
+ } else {\r
+ RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0xFF03FFD5);\r
+ }\r
+\r
+ dbValue = 0x09;\r
+ WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue);\r
+ ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);\r
+ if ( !pConfig->BuildParameters.EcKbd ) {\r
+ // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input\r
+ dbValue = dbValue & 0xF9;\r
+ }\r
+ if ( pConfig->BuildParameters.LegacyFree ) {\r
+ // Disable IRQ1/IRQ12 filter enable for Legacy free with USB KBC emulation.\r
+ dbValue = dbValue & 0x9F;\r
+ }\r
+ // Enabled IRQ input\r
+ dbValue = dbValue | BIT4;\r
+ WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue);\r
+\r
+#ifndef NO_EC_SUPPORT\r
+ getChipSysMode (&dbPortStatus);\r
+ if ( ((dbPortStatus & ChipSysEcEnable) == 0x00) ) {\r
+ // EC is disabled by jumper setting or board config\r
+ RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4), AccWidthUint16 | S3_SAVE, 0xFFFE, BIT0);\r
+ } else {\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xF7, 0x08);\r
+ ecPowerOnInit ( pConfig);\r
+ }\r
+#endif\r
+\r
+ ReadMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG80, AccWidthUint8, &dbValue);\r
+ if (dbValue & ChipSysIntClkGen) {\r
+ ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, &dbValue);\r
+ if (dbValue & BIT2) {\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC0 + 2, AccWidthUint8, 0xDF, 0x20);\r
+ } else {\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xFB, 0x40);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC0 + 2, AccWidthUint8, 0xDF, 0x20);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xFB, 0x00);\r
+ }\r
+ }\r
+\r
+ // Restore GPP clock to on as it may be off during last POST when some device was disabled;\r
+ // the device can't be detected if enabled again as the values retain on S5 and warm reset.\r
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG00, AccWidthUint32, 0xFFFFFFFF, 0xFFFFFFFF);\r
+ RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_MISC_REG04, AccWidthUint8, 0xFF, 0xFF);\r
+\r
+ // Set PMx88[5]to enable LdtStp# output to do the C3 or FidVid transation\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8, 0xFF, BIT5);\r
+}\r
--- /dev/null
+/**\r
+ * @file\r
+ *\r
+ * Southbridge CIMx Function Support Define (All)\r
+ *\r
+ *\r
+ *\r
+ * @xrefitem bom "File Content Label" "Release Content"\r
+ * @e project: CIMx-SB\r
+ * @e sub-project:\r
+ * @e \$Revision:$ @e \$Date:$\r
+ *\r
+ */\r
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+\r
+// Southbridge SBMAIN Routines\r
+\r
+/**\r
+ * Southbridge Main Function Public Function\r
+ *\r
+ */\r
+\r
+/**\r
+ * sbBeforePciInit - Config Southbridge before PCI emulation\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID sbBeforePciInit (IN AMDSBCFG* pConfig);\r
+\r
+\r
+/**\r
+ * sbAfterPciInit - Config Southbridge after PCI emulation\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID sbAfterPciInit (IN AMDSBCFG* pConfig);\r
+\r
+/**\r
+ * sbMidPostInit - Config Southbridge during middle of POST\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID sbMidPostInit (IN AMDSBCFG* pConfig);\r
+\r
+/**\r
+ * sbLatePost - Prepare Southbridge to boot to OS.\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID sbLatePost (IN AMDSBCFG* pConfig);\r
+\r
+/**\r
+ * sbBeforePciRestoreInit - Config Southbridge before ACPI S3 resume PCI config device restore\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID sbBeforePciRestoreInit (IN AMDSBCFG* pConfig);\r
+\r
+/**\r
+ * sbAfterPciRestoreInit - Config Southbridge after ACPI S3 resume PCI config device restore\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID sbAfterPciRestoreInit (IN AMDSBCFG* pConfig);\r
+\r
+/**\r
+ * sbSmmAcpiOn - Config Southbridge during ACPI_ON\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID sbSmmAcpiOn (IN AMDSBCFG* pConfig);\r
+\r
+/**\r
+ * CallBackToOEM - Call Back routine.\r
+ *\r
+ *\r
+ *\r
+ * @param[in] Func Callback ID.\r
+ * @param[in] Data Callback specific data.\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ */\r
+UINTN CallBackToOEM (IN UINT32 Func, IN UINT32 Data, IN AMDSBCFG* pConfig);\r
+\r
+\r
+// Southbridge SBPOR Routines\r
+\r
+/**\r
+ * Southbridge power-on initial Public Function\r
+ *\r
+ */\r
+\r
+/**\r
+ * sbPowerOnInit - Config Southbridge during power on stage.\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID sbPowerOnInit (IN AMDSBCFG* pConfig);\r
+\r
+\r
+// Southbridge Common Routines\r
+\r
+/**\r
+ * Southbridge Common Public Function\r
+ *\r
+ */\r
+\r
+/**\r
+ * commonInitEarlyBoot - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB.\r
+ *\r
+ * This settings should be done during S3 resume also\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID commonInitEarlyBoot (IN AMDSBCFG* pConfig);\r
+\r
+/**\r
+ * commonInitEarlyPost - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB.\r
+ *\r
+ * This settings might not program during S3 resume\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID commonInitEarlyPost (IN AMDSBCFG* pConfig);\r
+\r
+/**\r
+ * commonInitLateBoot - Prepare Southbridge register setting to boot to OS.\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID commonInitLateBoot (IN AMDSBCFG* pConfig);\r
+\r
+/**\r
+ * abSpecialSetBeforePciEnum - Special setting ABCFG registers before PCI emulation.\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID abSpecialSetBeforePciEnum (IN AMDSBCFG* pConfig);\r
+\r
+VOID usbSetPllDuringS3 (IN AMDSBCFG* pConfig);\r
+VOID usbDesertPll (IN AMDSBCFG* pConfig);\r
+\r
+/**\r
+ * hpetInit - Program Southbridge HPET function\r
+ *\r
+ * ** Eric\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ * @param[in] pStaticOptions Platform build configuration table.\r
+ *\r
+ */\r
+VOID hpetInit (IN AMDSBCFG* pConfig, IN BUILDPARAM *pStaticOptions);\r
+\r
+/**\r
+ * c3PopupSetting - Program Southbridge C state function\r
+ *\r
+ * ** Eric\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID c3PopupSetting (IN AMDSBCFG* pConfig);\r
+\r
+/**\r
+ * FusionRelatedSetting - Program Fusion C related function\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID FusionRelatedSetting (IN AMDSBCFG* pConfig);\r
+\r
+/**\r
+ * Southbridge Common Private Function\r
+ *\r
+ */\r
+\r
+/**\r
+ * abLinkInitBeforePciEnum - Set ABCFG registers before PCI emulation.\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID abLinkInitBeforePciEnum (IN AMDSBCFG* pConfig);\r
+\r
+// Southbridge SATA Routines\r
+\r
+/**\r
+ * Southbridge SATA Controller Public Function\r
+ *\r
+ */\r
+\r
+/**\r
+ * sataInitMidPost - Config SATA controller in Middle POST.\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID sataInitMidPost (IN AMDSBCFG* pConfig);\r
+\r
+/**\r
+ * sataInitAfterPciEnum - Config SATA controller after PCI emulation\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID sataInitAfterPciEnum (IN AMDSBCFG* pConfig);\r
+\r
+/**\r
+ * sataInitBeforePciEnum - Config SATA controller before PCI emulation\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID sataInitBeforePciEnum (IN AMDSBCFG* pConfig);\r
+\r
+/**\r
+ * sataInitLatePost - Prepare SATA controller to boot to OS.\r
+ *\r
+ * - Set class ID to AHCI (if set to AHCI * Mode)\r
+ * - Enable AHCI interrupt\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID sataInitLatePost (IN AMDSBCFG* pConfig);\r
+\r
+// Southbridge GEC Routines\r
+\r
+/**\r
+ * Southbridge GEC Controller Public Function\r
+ *\r
+ */\r
+\r
+/**\r
+ * gecInitBeforePciEnum - Config GEC controller before PCI emulation\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID gecInitBeforePciEnum (IN AMDSBCFG* pConfig);\r
+\r
+/**\r
+ * gecInitAfterPciEnum - Config GEC controller after PCI emulation\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID gecInitAfterPciEnum (IN AMDSBCFG* pConfig);\r
+\r
+/**\r
+ * gecInitLatePost - Prepare GEC controller to boot to OS.\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID gecInitLatePost (IN AMDSBCFG* pConfig);\r
+\r
+// Southbridge USB Routines\r
+\r
+/**\r
+ * Southbridge USB Controller Public Function\r
+ *\r
+ */\r
+\r
+/**\r
+ * Config USB controller before PCI emulation\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID usbInitBeforePciEnum (IN AMDSBCFG* pConfig);\r
+\r
+/**\r
+ * Config USB controller after PCI emulation\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID usbInitAfterPciInit (IN AMDSBCFG* pConfig);\r
+\r
+/**\r
+ * Config USB1 EHCI controller after PCI emulation\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID usb1EhciInitAfterPciInit (IN AMDSBCFG* pConfig);\r
+VOID usb2EhciInitAfterPciInit (IN AMDSBCFG* pConfig);\r
+VOID usb3EhciInitAfterPciInit (IN AMDSBCFG* pConfig);\r
+VOID usb1OhciInitAfterPciInit (IN AMDSBCFG* pConfig);\r
+VOID usb2OhciInitAfterPciInit (IN AMDSBCFG* pConfig);\r
+VOID usb3OhciInitAfterPciInit (IN AMDSBCFG* pConfig);\r
+VOID usb4OhciInitAfterPciInit (IN AMDSBCFG* pConfig);\r
+\r
+// Southbridge SMI Service Routines (SMM.C)\r
+\r
+/**\r
+ * Southbridge SMI Service Routines Public Function\r
+ *\r
+ */\r
+\r
+/**\r
+ * Southbridge SMI service module\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID sbSmmService (IN AMDSBCFG* pConfig);\r
+\r
+/**\r
+ * softwareSMIservice - Software SMI service\r
+ *\r
+ * ** Eric\r
+ *\r
+ * @param[in] VOID Southbridge software SMI service ID.\r
+ *\r
+ */\r
+VOID softwareSMIservice (IN VOID);\r
+\r
+// Southbridge GPP Controller Routines\r
+\r
+/**\r
+ * Southbridge GPP Controller Routines Public Function\r
+ *\r
+ */\r
+\r
+/**\r
+ * GPP early programming and link training. On exit all populated EPs should be fully operational.\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID sbPcieGppEarlyInit (IN AMDSBCFG* pConfig);\r
+\r
+/**\r
+ * sbPcieGppLateInit - Late PCIE initialization for SB800 GPP component\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID sbPcieGppLateInit (IN AMDSBCFG* pConfig);\r
+\r
+// Southbridge HD Controller Routines (AZALIA.C)\r
+\r
+/**\r
+ * Southbridge HD Controller Routines (AZALIA.C) Public Function\r
+ *\r
+ */\r
+\r
+/**\r
+ * Config HD Audio Before PCI emulation\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID azaliaInitBeforePciEnum (IN AMDSBCFG* pConfig);\r
+\r
+/**\r
+ * Config HD Audio after PCI emulation\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID azaliaInitAfterPciEnum (IN AMDSBCFG* pConfig);\r
+\r
+\r
+// Southbridge EC Routines\r
+\r
+#ifndef NO_EC_SUPPORT\r
+/**\r
+ * Southbridge EC Controller Public Function\r
+ *\r
+ */\r
+\r
+/**\r
+ * Config EC controller during power-on\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+ VOID ecPowerOnInit (IN AMDSBCFG* pConfig);\r
+\r
+/**\r
+ * Config EC controller before PCI emulation\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+ VOID ecInitBeforePciEnum (IN AMDSBCFG* pConfig);\r
+\r
+/**\r
+ * Prepare EC controller to boot to OS.\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+ VOID ecInitLatePost (IN AMDSBCFG* pConfig);\r
+\r
+/**\r
+ * validateImcFirmware - Validate IMC Firmware.\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ * @retval TRUE Pass\r
+ * @retval FALSE Failed\r
+ */\r
+ BOOLEAN validateImcFirmware (IN AMDSBCFG* pConfig);\r
+\r
+/**\r
+ * validateImcFirmware - Validate IMC Firmware.\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+ VOID softwareToggleImcStrapping (IN AMDSBCFG* pConfig);\r
+#endif\r
+\r
+#ifndef NO_HWM_SUPPORT\r
+/**\r
+ * validateImcFirmware - Validate IMC Firmware.\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+ VOID hwmInit (IN AMDSBCFG* pConfig);\r
+#endif\r
+\r
--- /dev/null
+\r
+/**\r
+ * @file\r
+ *\r
+ * Southbridge CIMx configuration structure define\r
+ *\r
+ *\r
+ *\r
+ * @xrefitem bom "File Content Label" "Release Content"\r
+ * @e project: CIMx-SB\r
+ * @e sub-project:\r
+ * @e \$Revision:$ @e \$Date:$\r
+ *\r
+ */\r
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+\r
+#ifndef _AMD_SBTYPE_H_\r
+#define _AMD_SBTYPE_H_\r
+\r
+#pragma pack (push, 1)\r
+\r
+/**\r
+ * Entry point of Southbridge CIMx\r
+ *\r
+ *\r
+ * @param[in] Param1 Southbridge CIMx Function ID.\r
+ * @param[in] Param2 Southbridge Input Data.\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+typedef UINT32 (*SBCIM_HOOK_ENTRY) (UINT32 Param1, UINT32 Param2, void* pConfig);\r
+/**\r
+ * SMM_SERVICE_ROUTINE - Southbridge SMI service routine\r
+ *\r
+ */\r
+typedef void (*SMM_SERVICE_ROUTINE) (void);\r
+\r
+\r
+/**\r
+ * The STATIC platform information for CIMx Module.\r
+ *\r
+ */\r
+typedef struct _BUILDPARAM {\r
+ UINT32 BiosSize:3; /**< BiosSize\r
+ * @par\r
+ * BIOSSize [2.0] - BIOS Image Size\r
+ * @li <b>0</b> - 1M\r
+ * @li <b>1</b> - 2M\r
+ * @li <b>3</b> - 4M\r
+ * @li <b>7</b> - 8M\r
+ * In SB800, default ROM size is 1M Bytes, if your platform ROM bigger then 1M\r
+ * you have to set the ROM size outside CIMx module and before AGESA module get call\r
+ *\r
+ */\r
+ UINT32 LegacyFree:1; /**< LegacyFree\r
+ * @par\r
+ * Config Southbridge CIMx module for Legacy Free Mode\r
+ */\r
+ UINT32 SpiSpeed:2; /**< SpiSpeed\r
+ * @par\r
+ * SPI Speed [1.0] - the clock speed for non-fast read command\r
+ * @li <b>00</b> - 66Mhz\r
+ * @li <b>01</b> - 33Mhz\r
+ * @li <b>10</b> - 22Mhz\r
+ * @li <b>11</b> - 16.5Mhz\r
+ *\r
+ */\r
+ UINT32 ImcEnableOverWrite:2; /**< ImcEnableOverWrite\r
+ * @par\r
+ * Imc Enable OverWrite\r
+ * @li <b>00</b> - by default strapping\r
+ * @li <b>01</b> - On\r
+ * @li <b>10</b> - Off\r
+ *\r
+ */\r
+ UINT32 SpiFastReadEnable:1; /**< SpiFastReadEnable\r
+ * @par\r
+ * @li <b>00</b> - Disable SPI Fast Read Function\r
+ * @li <b>01</b> - Enable SPI Fast Read Function\r
+ */\r
+ UINT32 SpiFastReadSpeed:2; /**< SpiFastReadSpeed\r
+ * @par\r
+ * @li <b>00</b> - 66Mhz\r
+ * @li <b>01</b> - 33Mhz\r
+ * @li <b>10</b> - 22Mhz\r
+ * @li <b>11</b> - 16.5Mhz\r
+ */\r
+ UINT32 SpreadSpectrumType:1; /**< SpreadSpectrumType\r
+ * @par\r
+ * @li <b>0</b> - Spread Spectrum for normal platform\r
+ * @li <b>1</b> - Spread Spectrum for Ontario platform\r
+ */\r
+/** Dummy0 - Reserved */\r
+ UINT32 Dummy0:4;\r
+ UINT32 EcKbd:1; /**< EcKbd\r
+ * @par\r
+ * EcKbd [16] - Platform use EC (as SIO) or SIO chip for PS/2 Keyboard and Mouse\r
+ * @li <b>0</b> - Use SIO PS/2 function.\r
+ * @li <b>1</b> - Use EC PS/2 function instead of SIO PS/2 function. **\r
+ * @li <b>**</b> When set 1, EC function have to enable, otherwise, CIMx treat as legacy-free system.\r
+ */\r
+/** EcChannel0 - Reserved */\r
+ UINT32 EcChannel0:1;\r
+/** UsbMsi - Reserved */\r
+ UINT32 UsbMsi:1;\r
+/** HdAudioMsi - Reserved */\r
+ UINT32 HdAudioMsi:1;\r
+/** LpcMsi - Reserved */\r
+ UINT32 LpcMsi:1;\r
+/** PcibMsi - Reserved */\r
+ UINT32 PcibMsi:1;\r
+/** AbMsi - Reserved */\r
+ UINT32 AbMsi:1;\r
+/** Dummy1 - Reserved */\r
+ UINT32 Dummy1:9;\r
+\r
+ UINT32 Smbus0BaseAddress; /**< Smbus0BaseAddress\r
+ * @par\r
+ * Smbus BASE Address\r
+ */\r
+ UINT32 Smbus1BaseAddress; /**< Smbus1BaseAddress\r
+ * @par\r
+ * Smbus1 (ASF) BASE Address\r
+ */\r
+ UINT32 SioPmeBaseAddress; /**< SioPmeBaseAddress\r
+ * @par\r
+ * SIO PME BASE Address\r
+ */\r
+ UINT32 WatchDogTimerBase; /**< WatchDogTimerBase\r
+ * @par\r
+ * Watch Dog Timer Address\r
+ */\r
+ UINT32 GecShadowRomBase; /**< GecShadowRomBase\r
+ * @par\r
+ * GEC (NIC) SHADOWROM BASE Address\r
+ */\r
+ UINT32 SpiRomBaseAddress; /**< SpiRomBaseAddress\r
+ * @par\r
+ * SPI ROM BASE Address\r
+ */\r
+ UINT16 AcpiPm1EvtBlkAddr; /**< AcpiPm1EvtBlkAddr\r
+ * @par\r
+ * ACPI PM1 event block Address\r
+ */\r
+ UINT16 AcpiPm1CntBlkAddr; /**< AcpiPm1CntBlkAddr\r
+ * @par\r
+ * ACPI PM1 Control block Address\r
+ */\r
+ UINT16 AcpiPmTmrBlkAddr; /**< AcpiPmTmrBlkAddr\r
+ * @par\r
+ * ACPI PM timer block Address\r
+ */\r
+ UINT16 CpuControlBlkAddr; /**< CpuControlBlkAddr\r
+ * @par\r
+ * ACPI CPU control block Address\r
+ */\r
+ UINT16 AcpiGpe0BlkAddr; /**< AcpiGpe0BlkAddr\r
+ * @par\r
+ * ACPI GPE0 block Address\r
+ */\r
+ UINT16 SmiCmdPortAddr; /**< SmiCmdPortAddr\r
+ * @par\r
+ * SMI command port Address\r
+ */\r
+ UINT16 AcpiPmaCntBlkAddr; /**< AcpiPmaCntBlkAddr\r
+ * @par\r
+ * ACPI PMA Control block Address\r
+ */\r
+ UINT32 HpetBase; /**< HpetBase\r
+ * @par\r
+ * HPET Base address\r
+ */\r
+ UINT32 SataIDESsid; /**< SataIDESsid\r
+ * @par\r
+ * SATA IDE mode SSID\r
+ */\r
+ UINT32 SataRAIDSsid; /**< SataRAIDSsid\r
+ * @par\r
+ * SATA RAID mode SSID\r
+ */\r
+ UINT32 SataRAID5Ssid; /**< SataRAID5Ssid\r
+ * @par\r
+ * SATA RAID5 mode SSID\r
+ */\r
+ UINT32 SataAHCISsid; /**< SataAHCISsid\r
+ * @par\r
+ * SATA AHCI mode SSID\r
+ */\r
+ UINT32 OhciSsid; /**< OhciSsid\r
+ * @par\r
+ * OHCI Controller SSID\r
+ */\r
+ UINT32 EhciSsid; /**< EhciSsid\r
+ * @par\r
+ * EHCI Controller SSID\r
+ */\r
+ UINT32 Ohci4Ssid; /**< Ohci4Ssid\r
+ * @par\r
+ * OHCI4 Controller SSID (Force USB 1.1 mode)\r
+ */\r
+ UINT32 SmbusSsid; /**< SmbusSsid\r
+ * @par\r
+ * SMBUS controller SSID\r
+ */\r
+ UINT32 IdeSsid; /**< IdeSsid\r
+ * @par\r
+ * IDE (Sata) controller SSID\r
+ */\r
+ UINT32 AzaliaSsid; /**< AzaliaSsid\r
+ * @par\r
+ * HD Audio controller SSID\r
+ */\r
+ UINT32 LpcSsid; /**< LpcSsid\r
+ * @par\r
+ * LPC controller SSID\r
+ */\r
+ UINT32 PCIBSsid; /**< PCIBSsid\r
+ * @par\r
+ * PCIB controller SSID\r
+ */\r
+} BUILDPARAM;\r
+\r
+/**\r
+ * The EC fan MSGREG struct for CIMx Module. *\r
+ */\r
+typedef struct _EC_struct {\r
+ UINT8 MSGFun81zone0MSGREG0; ///<Thermal zone\r
+ UINT8 MSGFun81zone0MSGREG1; ///<Thermal zone\r
+ UINT8 MSGFun81zone0MSGREG2; ///<Thermal zone control byte 1\r
+ UINT8 MSGFun81zone0MSGREG3; ///<Thermal zone control byte 2\r
+ UINT8 MSGFun81zone0MSGREG4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.\r
+ UINT8 MSGFun81zone0MSGREG5; ///<Hysteresis inforamtion\r
+ UINT8 MSGFun81zone0MSGREG6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032\r
+ UINT8 MSGFun81zone0MSGREG7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.\r
+ UINT8 MSGFun81zone0MSGREG8; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry\r
+ UINT8 MSGFun81zone0MSGREG9; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry\r
+\r
+ //EC LDN9 funtion 81 zone 1\r
+ UINT8 MSGFun81zone1MSGREG0; ///<Thermal zone\r
+ UINT8 MSGFun81zone1MSGREG1; ///<Thermal zone\r
+ UINT8 MSGFun81zone1MSGREG2; ///<Thermal zone control byte 1\r
+ UINT8 MSGFun81zone1MSGREG3; ///<Thermal zone control byte 2\r
+ UINT8 MSGFun81zone1MSGREG4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.\r
+ UINT8 MSGFun81zone1MSGREG5; ///<Hysteresis inforamtion\r
+ UINT8 MSGFun81zone1MSGREG6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032\r
+ UINT8 MSGFun81zone1MSGREG7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.\r
+ UINT8 MSGFun81zone1MSGREG8; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry\r
+ UINT8 MSGFun81zone1MSGREG9; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry\r
+\r
+ //EC LDN9 funtion 81 zone 2\r
+ UINT8 MSGFun81zone2MSGREG0; ///<Thermal zone\r
+ UINT8 MSGFun81zone2MSGREG1; ///<Thermal zone\r
+ UINT8 MSGFun81zone2MSGREG2; ///<Thermal zone control byte 1\r
+ UINT8 MSGFun81zone2MSGREG3; ///<Thermal zone control byte 2\r
+ UINT8 MSGFun81zone2MSGREG4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.\r
+ UINT8 MSGFun81zone2MSGREG5; ///<Hysteresis inforamtion\r
+ UINT8 MSGFun81zone2MSGREG6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032\r
+ UINT8 MSGFun81zone2MSGREG7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.\r
+ UINT8 MSGFun81zone2MSGREG8; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry\r
+ UINT8 MSGFun81zone2MSGREG9; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry\r
+\r
+ //EC LDN9 funtion 81 zone 3\r
+ UINT8 MSGFun81zone3MSGREG0; ///<Thermal zone\r
+ UINT8 MSGFun81zone3MSGREG1; ///<Thermal zone\r
+ UINT8 MSGFun81zone3MSGREG2; ///<Thermal zone control byte 1\r
+ UINT8 MSGFun81zone3MSGREG3; ///<Thermal zone control byte 2\r
+ UINT8 MSGFun81zone3MSGREG4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.\r
+ UINT8 MSGFun81zone3MSGREG5; ///<Hysteresis inforamtion\r
+ UINT8 MSGFun81zone3MSGREG6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032\r
+ UINT8 MSGFun81zone3MSGREG7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.\r
+ UINT8 MSGFun81zone3MSGREG8; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry\r
+ UINT8 MSGFun81zone3MSGREG9; ///< @todo Style_Analyzer: Add Doxygen comments to struct entry\r
+\r
+ //EC LDN9 funtion 83 zone 0\r
+ UINT8 MSGFun83zone0MSGREG0; ///<Thermal zone\r
+ UINT8 MSGFun83zone0MSGREG1; ///<Thermal zone\r
+ UINT8 MSGFun83zone0MSGREG2; ///<_AC0\r
+ UINT8 MSGFun83zone0MSGREG3; ///<_AC1\r
+ UINT8 MSGFun83zone0MSGREG4; ///<_AC2\r
+ UINT8 MSGFun83zone0MSGREG5; ///<_AC3\r
+ UINT8 MSGFun83zone0MSGREG6; ///<_AC4\r
+ UINT8 MSGFun83zone0MSGREG7; ///<_AC5\r
+ UINT8 MSGFun83zone0MSGREG8; ///<_AC6\r
+ UINT8 MSGFun83zone0MSGREG9; ///<_AC7\r
+ UINT8 MSGFun83zone0MSGREGA; ///<_CRT\r
+ UINT8 MSGFun83zone0MSGREGB; ///<_PSV\r
+\r
+ //EC LDN9 funtion 83 zone 1\r
+ UINT8 MSGFun83zone1MSGREG0; ///<Thermal zone\r
+ UINT8 MSGFun83zone1MSGREG1; ///<Thermal zone\r
+ UINT8 MSGFun83zone1MSGREG2; ///<_AC0\r
+ UINT8 MSGFun83zone1MSGREG3; ///<_AC1\r
+ UINT8 MSGFun83zone1MSGREG4; ///<_AC2\r
+ UINT8 MSGFun83zone1MSGREG5; ///<_AC3\r
+ UINT8 MSGFun83zone1MSGREG6; ///<_AC4\r
+ UINT8 MSGFun83zone1MSGREG7; ///<_AC5\r
+ UINT8 MSGFun83zone1MSGREG8; ///<_AC6\r
+ UINT8 MSGFun83zone1MSGREG9; ///<_AC7\r
+ UINT8 MSGFun83zone1MSGREGA; ///<_CRT\r
+ UINT8 MSGFun83zone1MSGREGB; ///<_PSV\r
+\r
+ //EC LDN9 funtion 83 zone 2\r
+ UINT8 MSGFun83zone2MSGREG0; ///<Thermal zone\r
+ UINT8 MSGFun83zone2MSGREG1; ///<Thermal zone\r
+ UINT8 MSGFun83zone2MSGREG2; ///<_AC0\r
+ UINT8 MSGFun83zone2MSGREG3; ///<_AC1\r
+ UINT8 MSGFun83zone2MSGREG4; ///<_AC2\r
+ UINT8 MSGFun83zone2MSGREG5; ///<_AC3\r
+ UINT8 MSGFun83zone2MSGREG6; ///<_AC4\r
+ UINT8 MSGFun83zone2MSGREG7; ///<_AC5\r
+ UINT8 MSGFun83zone2MSGREG8; ///<_AC6\r
+ UINT8 MSGFun83zone2MSGREG9; ///<_AC7\r
+ UINT8 MSGFun83zone2MSGREGA; ///<_CRT\r
+ UINT8 MSGFun83zone2MSGREGB; ///<_PSV\r
+\r
+ //EC LDN9 funtion 83 zone 3\r
+ UINT8 MSGFun83zone3MSGREG0; ///<Thermal zone\r
+ UINT8 MSGFun83zone3MSGREG1; ///<Thermal zone\r
+ UINT8 MSGFun83zone3MSGREG2; ///<_AC0\r
+ UINT8 MSGFun83zone3MSGREG3; ///<_AC1\r
+ UINT8 MSGFun83zone3MSGREG4; ///<_AC2\r
+ UINT8 MSGFun83zone3MSGREG5; ///<_AC3\r
+ UINT8 MSGFun83zone3MSGREG6; ///<_AC4\r
+ UINT8 MSGFun83zone3MSGREG7; ///<_AC5\r
+ UINT8 MSGFun83zone3MSGREG8; ///<_AC6\r
+ UINT8 MSGFun83zone3MSGREG9; ///<_AC7\r
+ UINT8 MSGFun83zone3MSGREGA; ///<_CRT\r
+ UINT8 MSGFun83zone3MSGREGB; ///<_PSV\r
+\r
+ //EC LDN9 funtion 85 zone 0\r
+ UINT8 MSGFun85zone0MSGREG0; ///<Thermal zone\r
+ UINT8 MSGFun85zone0MSGREG1; ///<Thermal zone\r
+ UINT8 MSGFun85zone0MSGREG2; ///<AL0 PWM level in percentage (0 - 100%)\r
+ UINT8 MSGFun85zone0MSGREG3; ///<AL1 PWM level in percentage (0 - 100%)\r
+ UINT8 MSGFun85zone0MSGREG4; ///<AL2 PWM level in percentage (0 - 100%)\r
+ UINT8 MSGFun85zone0MSGREG5; ///<AL3 PWM level in percentage (0 - 100%)\r
+ UINT8 MSGFun85zone0MSGREG6; ///<AL4 PWM level in percentage (0 - 100%)\r
+ UINT8 MSGFun85zone0MSGREG7; ///<AL5 PWM level in percentage (0 - 100%)\r
+ UINT8 MSGFun85zone0MSGREG8; ///<AL6 PWM level in percentage (0 - 100%)\r
+ UINT8 MSGFun85zone0MSGREG9; ///<AL7 PWM level in percentage (0 - 100%)\r
+\r
+ //EC LDN9 funtion 85 zone 1\r
+ UINT8 MSGFun85zone1MSGREG0; ///<Thermal zone\r
+ UINT8 MSGFun85zone1MSGREG1; ///<Thermal zone\r
+ UINT8 MSGFun85zone1MSGREG2; ///<AL0 PWM level in percentage (0 - 100%)\r
+ UINT8 MSGFun85zone1MSGREG3; ///<AL1 PWM level in percentage (0 - 100%)\r
+ UINT8 MSGFun85zone1MSGREG4; ///<AL2 PWM level in percentage (0 - 100%)\r
+ UINT8 MSGFun85zone1MSGREG5; ///<AL3 PWM level in percentage (0 - 100%)\r
+ UINT8 MSGFun85zone1MSGREG6; ///<AL4 PWM level in percentage (0 - 100%)\r
+ UINT8 MSGFun85zone1MSGREG7; ///<AL5 PWM level in percentage (0 - 100%)\r
+ UINT8 MSGFun85zone1MSGREG8; ///<AL6 PWM level in percentage (0 - 100%)\r
+ UINT8 MSGFun85zone1MSGREG9; ///<AL7 PWM level in percentage (0 - 100%)\r
+\r
+ //EC LDN9 funtion 85 zone 2\r
+ UINT8 MSGFun85zone2MSGREG0; ///<Thermal zone\r
+ UINT8 MSGFun85zone2MSGREG1; ///<Thermal zone\r
+ UINT8 MSGFun85zone2MSGREG2; ///<AL0 PWM level in percentage (0 - 100%)\r
+ UINT8 MSGFun85zone2MSGREG3; ///<AL1 PWM level in percentage (0 - 100%)\r
+ UINT8 MSGFun85zone2MSGREG4; ///<AL2 PWM level in percentage (0 - 100%)\r
+ UINT8 MSGFun85zone2MSGREG5; ///<AL3 PWM level in percentage (0 - 100%)\r
+ UINT8 MSGFun85zone2MSGREG6; ///<AL4 PWM level in percentage (0 - 100%)\r
+ UINT8 MSGFun85zone2MSGREG7; ///<AL5 PWM level in percentage (0 - 100%)\r
+ UINT8 MSGFun85zone2MSGREG8; ///<AL6 PWM level in percentage (0 - 100%)\r
+ UINT8 MSGFun85zone2MSGREG9; ///<AL7 PWM level in percentage (0 - 100%)\r
+\r
+ //EC LDN9 funtion 85 zone 3\r
+ UINT8 MSGFun85zone3MSGREG0; ///<Thermal zone\r
+ UINT8 MSGFun85zone3MSGREG1; ///<Thermal zone\r
+ UINT8 MSGFun85zone3MSGREG2; ///<AL0 PWM level in percentage (0 - 100%)\r
+ UINT8 MSGFun85zone3MSGREG3; ///<AL1 PWM level in percentage (0 - 100%)\r
+ UINT8 MSGFun85zone3MSGREG4; ///<AL2 PWM level in percentage (0 - 100%)\r
+ UINT8 MSGFun85zone3MSGREG5; ///<AL3 PWM level in percentage (0 - 100%)\r
+ UINT8 MSGFun85zone3MSGREG6; ///<AL4 PWM level in percentage (0 - 100%)\r
+ UINT8 MSGFun85zone3MSGREG7; ///<AL5 PWM level in percentage (0 - 100%)\r
+ UINT8 MSGFun85zone3MSGREG8; ///<AL6 PWM level in percentage (0 - 100%)\r
+ UINT8 MSGFun85zone3MSGREG9; ///<AL7 PWM level in percentage (0 - 100%)\r
+\r
+ //EC LDN9 funtion 89 TEMPIN channel 0\r
+ UINT8 MSGFun89zone0MSGREG0; ///<Thermal zone\r
+ UINT8 MSGFun89zone0MSGREG1; ///<Thermal zone\r
+ UINT8 MSGFun89zone0MSGREG2; ///<At DWORD bit 0-7\r
+ UINT8 MSGFun89zone0MSGREG3; ///<At DWORD bit 15-8\r
+ UINT8 MSGFun89zone0MSGREG4; ///<At DWORD bit 23-16\r
+ UINT8 MSGFun89zone0MSGREG5; ///<At DWORD bit 31-24\r
+ UINT8 MSGFun89zone0MSGREG6; ///<Ct DWORD bit 0-7\r
+ UINT8 MSGFun89zone0MSGREG7; ///<Ct DWORD bit 15-8\r
+ UINT8 MSGFun89zone0MSGREG8; ///<Ct DWORD bit 23-16\r
+ UINT8 MSGFun89zone0MSGREG9; ///<Ct DWORD bit 31-24\r
+ UINT8 MSGFun89zone0MSGREGA; ///<Mode bit 0-7\r
+\r
+ //EC LDN9 funtion 89 TEMPIN channel 1\r
+ UINT8 MSGFun89zone1MSGREG0; ///<Thermal zone\r
+ UINT8 MSGFun89zone1MSGREG1; ///<Thermal zone\r
+ UINT8 MSGFun89zone1MSGREG2; ///<At DWORD bit 0-7\r
+ UINT8 MSGFun89zone1MSGREG3; ///<At DWORD bit 15-8\r
+ UINT8 MSGFun89zone1MSGREG4; ///<At DWORD bit 23-16\r
+ UINT8 MSGFun89zone1MSGREG5; ///<At DWORD bit 31-24\r
+ UINT8 MSGFun89zone1MSGREG6; ///<Ct DWORD bit 0-7\r
+ UINT8 MSGFun89zone1MSGREG7; ///<Ct DWORD bit 15-8\r
+ UINT8 MSGFun89zone1MSGREG8; ///<Ct DWORD bit 23-16\r
+ UINT8 MSGFun89zone1MSGREG9; ///<Ct DWORD bit 31-24\r
+ UINT8 MSGFun89zone1MSGREGA; ///<Mode bit 0-7\r
+\r
+ //EC LDN9 funtion 89 TEMPIN channel 2\r
+ UINT8 MSGFun89zone2MSGREG0; ///<Thermal zone\r
+ UINT8 MSGFun89zone2MSGREG1; ///<Thermal zone\r
+ UINT8 MSGFun89zone2MSGREG2; ///<At DWORD bit 0-7\r
+ UINT8 MSGFun89zone2MSGREG3; ///<At DWORD bit 15-8\r
+ UINT8 MSGFun89zone2MSGREG4; ///<At DWORD bit 23-16\r
+ UINT8 MSGFun89zone2MSGREG5; ///<At DWORD bit 31-24\r
+ UINT8 MSGFun89zone2MSGREG6; ///<Ct DWORD bit 0-7\r
+ UINT8 MSGFun89zone2MSGREG7; ///<Ct DWORD bit 15-8\r
+ UINT8 MSGFun89zone2MSGREG8; ///<Ct DWORD bit 23-16\r
+ UINT8 MSGFun89zone2MSGREG9; ///<Ct DWORD bit 31-24\r
+ UINT8 MSGFun89zone2MSGREGA; ///<Mode bit 0-7\r
+\r
+ //EC LDN9 funtion 89 TEMPIN channel 3\r
+ UINT8 MSGFun89zone3MSGREG0; ///<Thermal zone\r
+ UINT8 MSGFun89zone3MSGREG1; ///<Thermal zone\r
+ UINT8 MSGFun89zone3MSGREG2; ///<At DWORD bit 0-7\r
+ UINT8 MSGFun89zone3MSGREG3; ///<At DWORD bit 15-8\r
+ UINT8 MSGFun89zone3MSGREG4; ///<At DWORD bit 23-16\r
+ UINT8 MSGFun89zone3MSGREG5; ///<At DWORD bit 31-24\r
+ UINT8 MSGFun89zone3MSGREG6; ///<Ct DWORD bit 0-7\r
+ UINT8 MSGFun89zone3MSGREG7; ///<Ct DWORD bit 15-8\r
+ UINT8 MSGFun89zone3MSGREG8; ///<Ct DWORD bit 23-16\r
+ UINT8 MSGFun89zone3MSGREG9; ///<Ct DWORD bit 31-24\r
+ UINT8 MSGFun89zone3MSGREGA; ///<Mode bit 0-7\r
+\r
+ // FLAG for Fun83/85/89 support\r
+ UINT16 IMCFUNSupportBitMap; /// Bit0=81FunZone0 support(1=On;0=Off); bit1-3=81FunZone1-Zone3;Bit4-7=83FunZone0-Zone3;Bit8-11=85FunZone0-Zone3;Bit11-15=89FunZone0-Zone3;\r
+} EC_struct;\r
+/** SBGPPPORTCONFIG - Southbridge GPP port config structure */\r
+typedef struct {\r
+ UINT32 PortPresent:1; /**< Port connection\r
+ * @par\r
+ * @li <b>0</b> - Port doesn't have slot. No need to train the link\r
+ * @li <b>1</b> - Port connection defined and needs to be trained\r
+ */\r
+ UINT32 PortDetected:1; /**< Link training status\r
+ * @par\r
+ * @li <b>0</b> - EP not detected\r
+ * @li <b>1</b> - EP detected\r
+ */\r
+ UINT32 PortIsGen2:2; /**< Port link speed configuration\r
+ * @par\r
+ * @li <b>00</b> - Auto\r
+ * @li <b>01</b> - Forced GEN1\r
+ * @li <b>10</b> - Forced GEN2\r
+ * @li <b>11</b> - Reserved\r
+ */\r
+\r
+ UINT32 PortHotPlug:1; /**< Support hot plug?\r
+ * @par\r
+ * @li <b>0</b> - No support\r
+ * @li <b>1</b> - support\r
+ */\r
+/** PortMisc - Reserved */\r
+ UINT32 PortMisc:27;\r
+} SBGPPPORTCONFIG;\r
+\r
+/** CODECENTRY - Southbridge HD Audio OEM Codec structure */\r
+typedef struct _CODECENTRY {\r
+/** Nid - Reserved ?? */\r
+ UINT8 Nid;\r
+/** Byte40 - Reserved ?? */\r
+ UINT32 Byte40;\r
+} CODECENTRY;\r
+\r
+/** CODECTBLLIST - Southbridge HD Audio Codec table list */\r
+typedef struct _CODECTBLLIST {\r
+/** CodecID - Codec ID */\r
+ UINT32 CodecID;\r
+/** CodecTablePtr - Codec table pointer */\r
+ CODECENTRY* CodecTablePtr;\r
+} CODECTBLLIST;\r
+\r
+/** Sata Controller structure */\r
+typedef struct _SATAST {\r
+ UINT8 SataController:1; /**< SataController\r
+ * @par\r
+ * Sata Controller\r
+ * @li <b>0</b> - disable\r
+ * @li <b>1</b> - enable\r
+ */\r
+ UINT8 SataIdeCombMdPriSecOpt:1; /**< SataIdeCombMdPriSecOpt - Reserved */\r
+ UINT8 SataSetMaxGen2:1; /**< SataSetMaxGen2\r
+ * @par\r
+ * Sata Controller Set to Max Gen2 mode\r
+ * @li <b>0</b> - disable\r
+ * @li <b>1</b> - enable\r
+ */\r
+ UINT8 SataIdeCombinedMode:1; /**< SataIdeCombinedMode\r
+ * @par\r
+ * Sata IDE Controller set to Combined Mode\r
+ * @li <b>0</b> - enable\r
+ * @li <b>1</b> - disable\r
+ */\r
+/** SATARefClkSel - Reserved */\r
+ UINT8 SATARefClkSel:2; // 4:5\r
+/** SATARefDivSel - Reserved */\r
+ UINT8 SATARefDivSel:2; // 6:7\r
+} SATAST;\r
+\r
+/** _USBST Controller structure\r
+ *\r
+ * Usb Ohci1 Contoller is define at BIT0\r
+ * - 0:disable 1:enable\r
+ * (Bus 0 Dev 18 Func0) *\r
+ * Usb Ehci1 Contoller is define at BIT1\r
+ * - 0:disable 1:enable\r
+ * (Bus 0 Dev 18 Func2) *\r
+ * Usb Ohci2 Contoller is define at BIT2\r
+ * - 0:disable 1:enable\r
+ * (Bus 0 Dev 19 Func0) *\r
+ * Usb Ehci2 Contoller is define at BIT3\r
+ * - 0:disable 1:enable\r
+ * (Bus 0 Dev 19 Func2) *\r
+ * Usb Ohci3 Contoller is define at BIT4\r
+ * - 0:disable 1:enable\r
+ * (Bus 0 Dev 22 Func0) *\r
+ * Usb Ehci3 Contoller is define at BIT5\r
+ * - 0:disable 1:enable\r
+ * (Bus 0 Dev 22 Func2) *\r
+ * Usb Ohci4 Contoller is define at BIT6\r
+ * - 0:disable 1:enable\r
+ * (Bus 0 Dev 20 Func5) *\r
+ */\r
+typedef struct _USBST {\r
+ UINT8 Ohci1:1; ///< Ohci0 controller - 0:disable, 1:enable\r
+ UINT8 Ehci1:1; ///< Ehci1 controller - 0:disable, 1:enable\r
+ UINT8 Ohci2:1; ///< Ohci2 controller - 0:disable, 1:enable\r
+ UINT8 Ehci2:1; ///< Ehci2 controller - 0:disable, 1:enable\r
+ UINT8 Ohci3:1; ///< Ohci3 controller - 0:disable, 1:enable\r
+ UINT8 Ehci3:1; ///< Ehci3 controller - 0:disable, 1:enable\r
+ UINT8 Ohci4:1; ///< Ohci4 controller - 0:disable, 1:enable\r
+ UINT8 UTemp:1; ///< Reserved\r
+} USBST;\r
+\r
+/**\r
+ * _AZALIAPIN - HID Azalia or GPIO define structure.\r
+ *\r
+ */\r
+typedef struct _AZALIAPIN {\r
+ UINT8 AzaliaSdin0:2; /**< AzaliaSdin0\r
+ * @par\r
+ * SDIN0 is define at BIT0 & BIT1\r
+ * @li <b>00</b> - GPIO PIN\r
+ * @li <b>10</b> - As a Azalia SDIN pin\r
+ */\r
+ UINT8 AzaliaSdin1:2; /**< AzaliaSdin1\r
+ * @par\r
+ * SDIN0 is define at BIT2 & BIT3\r
+ * @li <b>00</b> - GPIO PIN\r
+ * @li <b>10</b> - As a Azalia SDIN pin\r
+ */\r
+ UINT8 AzaliaSdin2:2; /**< AzaliaSdin2\r
+ * @par\r
+ * SDIN0 is define at BIT4 & BIT5\r
+ * @li <b>00</b> - GPIO PIN\r
+ * @li <b>10</b> - As a Azalia SDIN pin\r
+ */\r
+ UINT8 AzaliaSdin3:2; /**< AzaliaSdin3\r
+ * @par\r
+ * SDIN0 is define at BIT6 & BIT7\r
+ * @li <b>00</b> - GPIO PIN\r
+ * @li <b>10</b> - As a Azalia SDIN pin\r
+ */\r
+} AZALIAPIN;\r
+\r
+/** AMDSBCFG - Southbridge CIMx configuration structure (Main) */\r
+typedef struct _AMDSBCFG {\r
+/** StdHeader - Standard header for all AGESA/CIMx services. */\r
+ AMD_CONFIG_PARAMS StdHeader;\r
+\r
+/** BuildParameters - The STATIC platform information for CIMx Module. */\r
+ BUILDPARAM BuildParameters;\r
+ //offset 90 bytes (32-121)\r
+ //MsgXchgBiosCimx //offset 4 bytes (122-125)\r
+ // SATA Configuration\r
+\r
+ union /**< union - Reserved */\r
+ { /**< SATAMODE - Sata Controller structure */\r
+/** SataModeReg - Reserved */\r
+ UINT8 SataModeReg;\r
+/** SataMode - Reserved */\r
+ SATAST SataMode;\r
+ } SATAMODE;\r
+/** S3Resume - Flag of ACPI S3 Resume. */\r
+ UINT8 S3Resume:1; // 8\r
+/** RebootRequired - Flag of Reboot system is required. */\r
+ UINT8 RebootRequired:1; // 9\r
+/** SbSpiSpeedSupport - Reserved */\r
+ UINT8 SbSpiSpeedSupport:1; // 10\r
+/**< SpreadSpectrum\r
+ * @par\r
+ * Spread Spectrum function\r
+ * @li <b>0</b> - disable\r
+ * @li <b>1</b> - enable\r
+ */\r
+ UINT8 SpreadSpectrum:1; // 11\r
+/** NbSbGen2 - Reserved */\r
+ UINT8 NbSbGen2:1; // 12\r
+ UINT8 GppGen2:1; // 13\r
+ UINT8 GppMemWrImprove:1; // 14\r
+/** MsgXchgBiosCimxReserved - Reserved */\r
+ UINT8 MsgXchgBiosCimxReserved:1; // 15 (BB USED)\r
+/**< SataClass - SATA Controller mode [16:18]\r
+ * @par\r
+ * @li <b>000</b> - Native IDE mode\r
+ * @li <b>001</b> - RAID mode\r
+ * @li <b>010</b> - AHCI mode\r
+ * @li <b>011</b> - Legacy IDE mode\r
+ * @li <b>100</b> - IDE->AHCI mode\r
+ * @li <b>101</b> - AHCI mode as 4394 ID (AMD driver)\r
+ * @li <b>110</b> - IDE->AHCI mode as 4394 ID (AMD driver)\r
+ */\r
+ UINT16 SataClass:3; // 16:18\r
+/**< Sata IDE Controller mode\r
+ * @par\r
+ * @li <b>0</b> - Legacy IDE mode\r
+ * @li <b>1</b> - Native IDE mode\r
+ */\r
+ UINT16 SataIdeMode:1; // 19\r
+/**< SataEspPort - SATA port is external accessible on a signal only connector (eSATA:)\r
+ * @par\r
+ * @li <b> BIT0 </b> - PORT0 set as ESP port\r
+ * @li <b> BIT1 </b> - PORT1 set as ESP port\r
+ * @li <b> BIT2 </b> - PORT2 set as ESP port\r
+ * @li <b> BIT3 </b> - PORT3 set as ESP port\r
+ * @li <b> BIT4 </b> - PORT4 set as ESP port\r
+ * @li <b> BIT5 </b> - PORT5 set as ESP port\r
+ */\r
+ UINT16 SataEspPort:6; // 20:25\r
+/** SataPortPower - Reserved */\r
+ UINT16 SataPortPower:6; // 31:26\r
+\r
+ // SATA Debug Option //offset 4 bytes (126-129)\r
+\r
+/**< SataPortMode - Force Each PORT to GEN1/GEN2 mode\r
+ * @par\r
+ * @li <b> 0 </b> Auto for each PORTs\r
+ * @li <b> BIT0 = 1</b> - PORT0 set to GEN1\r
+ * @li <b> BIT1 = 1</b> - PORT0 set to GEN2\r
+ * @li <b> BIT2 = 1</b> - PORT1 set to GEN1\r
+ * @li <b> BIT3 = 1</b> - PORT1 set to GEN2\r
+ * @li <b> BIT4 = 1</b> - PORT2 set to GEN1\r
+ * @li <b> BIT5 = 1</b> - PORT2 set to GEN2\r
+ * @li <b> BIT6 = 1</b> - PORT3 set to GEN1\r
+ * @li <b> BIT7 = 1</b> - PORT3 set to GEN2\r
+ * @li <b> BIT8 = 1</b> - PORT4 set to GEN1\r
+ * @li <b> BIT9 = 1</b> - PORT4 set to GEN2\r
+ * @li <b> BIT10 = 1</b> - PORT5 set to GEN1\r
+ * @li <b> BIT11 = 1</b> - PORT5 set to GEN2\r
+ */\r
+ UINT32 SataPortMode:12; //11:0\r
+/** SATAClkSelOpt - Reserved */\r
+ UINT32 SATAClkSelOpt:4; // Removed from coding side\r
+/** SataAggrLinkPmCap - Reserved */\r
+ UINT32 SataAggrLinkPmCap:1; //16, 0:OFF 1:ON\r
+/** SataPortMultCap - Reserved */\r
+ UINT32 SataPortMultCap:1; //17, 0:OFF 1:ON\r
+/** SataClkAutoOff - Reserved */\r
+ UINT32 SataClkAutoOff:1; //18, AutoClockOff 0:Disabled, 1:Enabled\r
+/** SataPscCap - Reserved */\r
+ UINT32 SataPscCap:1; //19, 0:Enable PSC capability, 1:Disable PSC capability\r
+/** BIOSOSHandoff - Reserved */\r
+ UINT32 BIOSOSHandoff:1; //20\r
+/** SataFisBasedSwitching - Reserved */\r
+ UINT32 SataFisBasedSwitching:1; //21\r
+/** SataCccSupport - Reserved */\r
+ UINT32 SataCccSupport:1; //22\r
+/** SataSscCap - Reserved */\r
+ UINT32 SataSscCap:1; //23, 0:Enable SSC capability, 1:Disable SSC capability\r
+/** SataMsiCapability - Reserved */\r
+ UINT32 SataMsiCapability:1; //24 0:Hidden 1:Visible. This feature is disabled per RPR, but remains the interface.\r
+/** SataForceRaid - Reserved */\r
+ UINT32 SataForceRaid:1; //25 0:No function 1:Force RAID\r
+/** SataDebugDummy - Reserved */\r
+ UINT32 SataDebugDummy:6; //31:26\r
+//\r
+// USB Configuration //offset 4 bytes (130-133)\r
+//\r
+\r
+/** USBDeviceConfig - USB Controller Configuration\r
+ *\r
+ * - Usb Ohci1 Contoller is define at BIT0\r
+ * - 0:disable 1:enable\r
+ * (Bus 0 Dev 18 Func0) *\r
+ * - Usb Ehci1 Contoller is define at BIT1\r
+ * - 0:disable 1:enable\r
+ * (Bus 0 Dev 18 Func2) *\r
+ * - Usb Ohci2 Contoller is define at BIT2\r
+ * - 0:disable 1:enable\r
+ * (Bus 0 Dev 19 Func0) *\r
+ * - Usb Ehci2 Contoller is define at BIT3\r
+ * - 0:disable 1:enable\r
+ * (Bus 0 Dev 19 Func2) *\r
+ * - Usb Ohci3 Contoller is define at BIT4\r
+ * - 0:disable 1:enable\r
+ * (Bus 0 Dev 22 Func0) *\r
+ * - Usb Ehci3 Contoller is define at BIT5\r
+ * - 0:disable 1:enable\r
+ * (Bus 0 Dev 22 Func2) *\r
+ * - Usb Ohci4 Contoller is define at BIT6\r
+ * - 0:disable 1:enable\r
+ * (Bus 0 Dev 20 Func5) *\r
+ */\r
+ union /**< union - Reserved */\r
+ { /**< USBMODE - USB Controller structure */\r
+/** SataModeReg - Reserved */\r
+ UINT8 UsbModeReg;\r
+/** SataMode - Reserved */\r
+ USBST UsbMode;\r
+ } USBMODE;\r
+/*!\r
+ */\r
+\r
+/**< GecConfig\r
+ * @par\r
+ * InChip Gbit NIC\r
+ * @li <b>1</b> - disable\r
+ * @li <b>0</b> - enable\r
+ */\r
+ UINT8 GecConfig:1; //8\r
+\r
+/**< IrConfig\r
+ * @par\r
+ * Ir Controller setting\r
+ * @li <b>00 </b> - disable\r
+ * @li <b>01 </b> - Rx and Tx0\r
+ * @li <b>10 </b> - Rx and Tx1\r
+ * @li <b>11 </b> - Rx and both Tx0,Tx1\r
+ */\r
+ UINT8 IrConfig:2; //9:10\r
+\r
+/** GecDummy - Reserved */\r
+ UINT8 GecDummy:5; //15:11\r
+\r
+ //Azalia Configuration\r
+\r
+/**< AzaliaController - Azalia Controller Configuration\r
+ * @par\r
+ * Azalia Controller [0-1]\r
+ * @li <b>0</b> - Auto : Detect Azalia controller automatically.\r
+ * @li <b>1</b> - Diable : Disable Azalia controller.\r
+ * @li <b>2</b> - Enable : Enable Azalia controller.\r
+ */\r
+ UINT8 AzaliaController:2; //17:16\r
+/**< AzaliaPinCfg - Azalia Controller SDIN pin Configuration\r
+ * @par\r
+ * @li <b>0</b> - disable\r
+ * @li <b>1</b> - enable\r
+ */\r
+ UINT8 AzaliaPinCfg:1; //18\r
+/**< AzaliaFrontPanel - Azalia Controller Front Panel Configuration\r
+ * @par\r
+ * Support Front Panel configuration\r
+ * @li <b>0</b> - Auto\r
+ * @li <b>1</b> - disable\r
+ * @li <b>2</b> - enable\r
+ */\r
+ UINT8 AzaliaFrontPanel:2; //20:19\r
+/**< FrontPanelDetected - Force Azalia Controller Front Panel Configuration\r
+ * @par\r
+ * Force Front Panel configuration\r
+ * @li <b>0</b> - Not Detected\r
+ * @li <b>1</b> - Detected\r
+ */\r
+ UINT8 FrontPanelDetected:1; //21\r
+/**< AzaliaSnoop - Azalia Controller Snoop feature Configuration\r
+ * @par\r
+ * Azalia Controller Snoop feature Configuration\r
+ * @li <b>0</b> - disable\r
+ * @li <b>1</b> - enable\r
+ */\r
+ UINT8 AzaliaSnoop:1; //22\r
+/** AzaliaDummy - Reserved */\r
+ UINT8 AzaliaDummy:1; //23\r
+\r
+ union\r
+ {\r
+/**< AzaliaSdinPin - Azalia Controller SDIN pin Configuration\r
+ *\r
+ * SDIN0 is define at BIT0 & BIT1\r
+ * - 00: GPIO PIN\r
+ * - 01: Reserved\r
+ * - 10: As a Azalia SDIN pin\r
+ *\r
+ * SDIN1 is define at BIT2 & BIT3\r
+ * * Config same as SDIN0\r
+ * SDIN2 is define at BIT4 & BIT5\r
+ * * Config same as SDIN0\r
+ * SDIN3 is define at BIT6 & BIT7\r
+ * * Config same as SDIN0\r
+ */\r
+ UINT8 AzaliaSdinPin;\r
+ AZALIAPIN AzaliaConfig;\r
+ } AZALIACONFIG;\r
+\r
+/** AZOEMTBL - Azalia Controller OEM Codec Table Pointer\r
+ *\r
+ */\r
+ union\r
+ {\r
+ PLACEHOLDER PlaceHolder;\r
+ CODECTBLLIST* pAzaliaOemCodecTablePtr; //offset 4 bytes (134-137)\r
+ } AZOEMTBL;\r
+\r
+/** AZOEMFPTBL - Azalia Controller Front Panel OEM Table Pointer\r
+ *\r
+ */\r
+ union\r
+ {\r
+ PLACEHOLDER PlaceHolder;\r
+ VOID* pAzaliaOemFpCodecTablePtr; //offset 4 bytes (138-141)\r
+ } AZOEMFPTBL;\r
+\r
+ //Miscellaneous Configuration //offset 4 bytes (142-145)\r
+/** AnyHT200MhzLink - Reserved */\r
+ UINT32 AnyHT200MhzLink:1; //0\r
+/**< HpetTimer - South Bridge Hpet Timer Configuration\r
+ * @par\r
+ * @li <b>0</b> - disable\r
+ * @li <b>1</b> - enable\r
+ */\r
+ UINT32 HpetTimer:1; //1\r
+/**< PciClks - PCI Slot Clock Control\r
+ * @par\r
+ * PCI SLOT 0 define at BIT0\r
+ * - 00: disable\r
+ * - 01: enable\r
+ *\r
+ * PCI SLOT 1 define at BIT1\r
+ * * Config same as PCI SLOT0\r
+ * PCI SLOT 2 define at BIT2\r
+ * * Config same as PCI SLOT0\r
+ * PCI SLOT 3 define at BIT3\r
+ * * Config same as PCI SLOT0\r
+ * PCI SLOT 4 define at BIT4\r
+ * * Config same as PCI SLOT0\r
+ */\r
+ UINT32 PciClks:5; //2:6\r
+/** MiscReserved1 - Reserved */\r
+ UINT32 MiscReserved1:4; //9:7, Reserved\r
+/** MobilePowerSavings - Debug function Reserved */\r
+ UINT32 MobilePowerSavings:1; //11, 0:Disable, 1:Enable Power saving features especially for Mobile platform\r
+/** MiscDummy1 - Debug function Reserved */\r
+ UINT32 MiscDummy1:1;\r
+/** NativePcieSupport - Debug function Reserved */\r
+ UINT32 NativePcieSupport:1; //13, 0:Enable, 1:Disabled\r
+/** FlashPinConfig - Debug function Reserved */\r
+ UINT32 FlashPinConfig:1; //14, 0:desktop mode 1:mobile mode\r
+/** UsbPhyPowerDown - Debug function Reserved */\r
+ UINT32 UsbPhyPowerDown:1; //15\r
+/** PcibClkStopOverride - Debug function Reserved */\r
+ UINT32 PcibClkStopOverride:10; //25:16\r
+/**< HpetMsiDis - South Bridge HPET MSI Configuration\r
+ * @par\r
+ * @li <b>1</b> - disable\r
+ * @li <b>0</b> - enable\r
+ */\r
+ UINT32 HpetMsiDis:1; //26\r
+/**< ResetCpuOnSyncFlood - Rest CPU on Sync Flood\r
+ * @par\r
+ * @li <b>0</b> - disable\r
+ * @li <b>1</b> - enable\r
+ */\r
+ UINT32 ResetCpuOnSyncFlood:1; //27\r
+/**< LdtStpDisable - LdtStp# output disable\r
+ * @par\r
+ * @li <b>0</b> - LdtStp# output enable\r
+ * @li <b>1</b> - LdtStp# output disable\r
+ */\r
+ UINT32 LdtStpDisable:1; //28\r
+/**< MTC1e - Message Triggered C1e\r
+ * @par\r
+ * @li <b>0</b> - disable\r
+ * @li <b>1</b> - enable\r
+ */\r
+ UINT32 MTC1e:1; //29\r
+/** MiscDummy - Reserved */\r
+ UINT32 MiscDummy:2; //31:30\r
+\r
+ //DebugOptions //offset 4 bytes (146-149)\r
+/** PcibAutoClkCtrlLow - Debug function Reserved */\r
+ UINT32 PcibAutoClkCtrlLow:16;\r
+/** PcibAutoClkCtrlHigh - Debug function Reserved */\r
+ UINT32 PcibAutoClkCtrlHigh:16;\r
+\r
+/**< OEMPROGTBL - ACPI MMIO register setting table OEM override\r
+ * @par\r
+ * OEM table for customer override ACPI MMIO register in their code.\r
+ */\r
+ union\r
+ {\r
+ PLACEHOLDER OemProgrammingTablePtr; //offset 4 bytes (150-153)\r
+ VOID *OemProgrammingTablePtr_Ptr;\r
+ } OEMPROGTBL;\r
+\r
+ //Gpp Configuration //offset 24 bytes total (154-177)\r
+ union {\r
+ UINT32 PORTCFG32;\r
+ SBGPPPORTCONFIG PortCfg;\r
+ } PORTCONFIG[MAX_GPP_PORTS]; //offset 16 bytes\r
+\r
+ UINT32 GppLinkConfig; // GPP_LINK_CONFIG = PCIE_GPP_Enable[3:0]\r
+ // 0000 - Port ABCD -> 4:0:0:0\r
+ // 0001 - N/A\r
+ // 0010 - Port ABCD -> 2:2:0:0\r
+ // 0011 - Port ABCD -> 2:1:1:0\r
+ // 0100 - Port ABCD -> 1:1:1:1\r
+ //\r
+ UINT32 GppFoundGfxDev:4; //3:0 If port A-D (mapped to bit [3:0]) has GFX EP detected\r
+ UINT32 CoreGen2Enable:1; //4\r
+ UINT32 GppFunctionEnable:1; //5\r
+ UINT32 GppUnhidePorts:1; //6\r
+ UINT32 AlinkPhyPllPowerDown:1; //7\r
+ UINT32 GppConfigDummy1:2; //9:8\r
+ UINT32 GppLaneReversal:1; //10\r
+ UINT32 GppPhyPllPowerDown:1; //11\r
+ UINT32 GppCompliance :1; //12\r
+ UINT32 GppPortAspm:8; //20:13 ASPM state for GPP ports, 14:13 for port0, ..., 20:19 for port3\r
+ // 00 - Disabled\r
+ // 01 - L0s\r
+ // 10 - L1\r
+ // 11 - L0s + L1\r
+ //\r
+ UINT32 GppConfigDummy:11; //31:21\r
+\r
+ //TempMMIO //offset 4 bytes (178-181)\r
+ UINT32 TempMMIO;\r
+\r
+ // DebugOption2\r
+ UINT32 GecPhyStatus:1;\r
+ UINT32 GecDebugOptionDummy:7;\r
+ UINT32 SBGecPwr:2;\r
+ UINT32 SBGecDebugBus:1;\r
+ UINT32 DebugOption2Dummy1:1;\r
+ UINT32 DebugOption2Dummy2:1;\r
+ UINT32 SbPcieOrderRule:1;\r
+ UINT32 SbUsbPll:1;\r
+ UINT32 AcDcMsg:1;\r
+ UINT32 TimerTickTrack:1;\r
+ UINT32 ClockInterruptTag:1;\r
+ UINT32 OhciTrafficHanding:1;\r
+ UINT32 EhciTrafficHanding:1;\r
+ UINT32 FusionMsgCMultiCore:1;\r
+ UINT32 FusionMsgCStage:1;\r
+/**< UsbRxMode - CG PLL multiplier for USB Rx 1.1 mode\r
+ * @par\r
+ * @li <b>0</b> - disable\r
+ * @li <b>1</b> - enable\r
+ */\r
+ UINT32 UsbRxMode:1;\r
+ UINT32 DebugOption2Dummy3:9; //\r
+\r
+ union\r
+ {\r
+ PLACEHOLDER DynamicGecRomAddressPtr; //offset 4 bytes (182-185)\r
+ VOID *DynamicGecRomAddress_Ptr;\r
+ } DYNAMICGECROM;\r
+ EC_struct Pecstruct;\r
+} AMDSBCFG;\r
+\r
+/** SMMSERVICESTRUC- Southbridge SMI service structure */\r
+typedef struct _SMMSERVICESTRUC {\r
+/** enableRegNum - Reserved */\r
+ UINT8 enableRegNum;\r
+/** enableBit - Reserved */\r
+ UINT8 enableBit;\r
+/** statusRegNum - Reserved */\r
+ UINT8 statusRegNum;\r
+/** statusBit - Reserved */\r
+ UINT8 statusBit;\r
+/** *debugMessage- Reserved */\r
+ CHAR8 *debugMessage;\r
+/** serviceRoutine - Reserved */\r
+ SMM_SERVICE_ROUTINE serviceRoutine;\r
+} SMMSERVICESTRUC;\r
+\r
+#ifndef _NB_REG8MASK_\r
+\r
+/**\r
+ * - Byte Register R/W structure\r
+ *\r
+ */\r
+ typedef struct _Reg8Mask {\r
+/** bRegIndex - Reserved */\r
+ UINT8 bRegIndex;\r
+/** bANDMask - Reserved */\r
+ UINT8 bANDMask;\r
+/** bORMask - Reserved */\r
+ UINT8 bORMask;\r
+ } REG8MASK;\r
+#endif\r
+\r
+/**\r
+ * - SATA Phy setting structure\r
+ *\r
+ */\r
+typedef struct _SATAPHYSETTING {\r
+/** wPhyCoreControl - Reserved */\r
+ UINT16 wPhyCoreControl;\r
+/** dwPhyFineTune - Reserved */\r
+ UINT32 dwPhyFineTune;\r
+} SATAPHYSETTING;\r
+\r
+/**\r
+ * _ABTblEntry - AB link register table R/W structure\r
+ *\r
+ */\r
+typedef struct _ABTblEntry {\r
+ /** regType : AB Register Type (ABCFG, AXCFG and so on) */\r
+ UINT8 regType;\r
+ /** regIndex : AB Register Index */\r
+ UINT32 regIndex;\r
+ /** regMask : AB Register Mask */\r
+ UINT32 regMask;\r
+ /** regData : AB Register Data */\r
+ UINT32 regData;\r
+} ABTBLENTRY;\r
+\r
+/**\r
+ * _AcpiRegWrite - ACPI MMIO register R/W structure\r
+ *\r
+ */\r
+typedef struct _AcpiRegWrite {\r
+ /** MmioBase : Index of Soubridge block (For instence GPIO_BASE:0x01 SMI_BASE:0x02) */\r
+ UINT8 MmioBase;\r
+ /** MmioReg : Register index */\r
+ UINT8 MmioReg;\r
+ /** DataANDMask : AND Register Data */\r
+ UINT8 DataANDMask;\r
+ /** DataOrMask : Or Register Data */\r
+ UINT8 DataOrMask;\r
+} AcpiRegWrite;\r
+\r
+/**\r
+ * PCI_ADDRESS - PCI access structure\r
+ *\r
+ */\r
+#define PCI_ADDRESS(bus, dev, func, reg) \\r
+(UINT32) ( (((UINT32)bus) << 24) + (((UINT32)dev) << 19) + (((UINT32)func) << 16) + ((UINT32)reg) )\r
+\r
+/**\r
+ * CIM_STATUS - CIMx module function return code\r
+ */\r
+typedef UINT32 CIM_STATUS;\r
+/**\r
+ * CIM_SUCCESS - Executed without error\r
+ */\r
+#define CIM_SUCCESS 0x00000000\r
+/**\r
+ * CIM_ERROR - call error\r
+ */\r
+#define CIM_ERROR 0x80000000\r
+/**\r
+ * CIM_UNSUPPORTED - function does not support\r
+ */\r
+#define CIM_UNSUPPORTED 0x80000001\r
+\r
+#pragma pack (pop)\r
+\r
+/**\r
+ * DISABLED - Define disable in module\r
+ */\r
+#define DISABLED 0\r
+/**\r
+ * ENABLED - Define enable in module\r
+ */\r
+#define ENABLED 1\r
+\r
+// mov al, code\r
+// out 80h, al\r
+// jmp $\r
+\r
+/**\r
+ * DBG_STOP - define a debug point\r
+ */\r
+#define DBG_STOP __asm _emit 0xEB __asm _emit 0xFE\r
+\r
+/**\r
+ * STOP_CODE - define a debug point\r
+ * Warning: AL gets destroyed!\r
+ */\r
+#define STOP_CODE (code) __asm __emit 0xB0 __asm __emit code __asm __emit 0xE6 \\r
+ __asm __emit 0x80 __asm _emit 0xEB __asm _emit 0xFE\r
+\r
+#endif // _AMD_SBTYPE_H_\r
--- /dev/null
+/**\r
+ * @file\r
+ *\r
+ * Southbridge SMM service function\r
+ *\r
+ * Prepare SMM service module for IBV call Southbridge SMI service routine.\r
+ *\r
+ * @xrefitem bom "File Content Label" "Release Content"\r
+ * @e project: CIMx-SB\r
+ * @e sub-project:\r
+ * @e \$Revision:$ @e \$Date:$\r
+ *\r
+ */\r
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+\r
+#include "SBPLATFORM.h"\r
+\r
+//\r
+// Declaration of local functions\r
+//\r
+\r
+/**\r
+ * Southbridge SMI service module\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+sbSmmService (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ AMDSBCFG* pTmp; //lx-dummy for /W4 build\r
+ pTmp = pConfig;\r
+}\r
+\r
+/**\r
+ * softwareSMIservice - Software SMI service\r
+ *\r
+ * @param[in] VOID Southbridge software SMI service ID.\r
+ *\r
+ */\r
+VOID\r
+softwareSMIservice (\r
+ IN VOID\r
+ )\r
+{\r
+}\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/**\r
+ * @file\r
+ *\r
+ * Function dispatcher.\r
+ *\r
+ *\r
+ *\r
+ * @xrefitem bom "File Content Label" "Release Content"\r
+ * @e project: CIMx-SB\r
+ * @e sub-project:\r
+ * @e \$Revision:$ @e \$Date:$\r
+ *\r
+ */\r
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+\r
+/*----------------------------------------------------------------------------------------\r
+ * M O D U L E S U S E D\r
+ *----------------------------------------------------------------------------------------\r
+ */\r
+\r
+#include "SBPLATFORM.h"\r
+\r
+/*----------------------------------------------------------------------------------------\r
+ * P R O T O T Y P E S O F L O C A L F U N C T I O N S\r
+ *----------------------------------------------------------------------------------------\r
+ */\r
+\r
+\r
+/*----------------------------------------------------------------------------------------\r
+ * D E F I N I T I O N S A N D M A C R O S\r
+ *----------------------------------------------------------------------------------------\r
+ */\r
+\r
+\r
+\r
+/// module header\r
+VOLATILE AMD_MODULE_HEADER mNbModuleHeader = {\r
+ 'DOM$', ///< Standard AMD module signature\r
+ CIMX_SB_ID, ///< Chipset ID\r
+ CIMX_SB_REVISION, ///< CIMx version\r
+ AmdSbDispatcher, ///< Pointer to the module entry\r
+ NULL ///< Pointer link to next module header\r
+};\r
--- /dev/null
+/**\r
+ * @file\r
+ *\r
+ * Config Southbridge USB controller\r
+ *\r
+ * Init USB features.\r
+ *\r
+ * @xrefitem bom "File Content Label" "Release Content"\r
+ * @e project: CIMx-SB\r
+ * @e sub-project:\r
+ * @e \$Revision:$ @e \$Date:$\r
+ *\r
+ */\r
+/*\r
+ *****************************************************************************\r
+ *\r
+ * This file is part of the coreboot project.\r
+ *\r
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.\r
+ *\r
+ * This program is free software; you can redistribute it and/or modify\r
+ * it under the terms of the GNU General Public License as published by\r
+ * the Free Software Foundation; version 2 of the License.\r
+ *\r
+ * This program is distributed in the hope that it will be useful,\r
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+ * GNU General Public License for more details.\r
+ *\r
+ * You should have received a copy of the GNU General Public License\r
+ * along with this program; if not, write to the Free Software\r
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA\r
+ * ***************************************************************************\r
+ *\r
+ */\r
+\r
+\r
+#include "SBPLATFORM.h"\r
+\r
+//\r
+// Declaration of local functions\r
+//\r
+\r
+/**\r
+ * EhciInitAfterPciInit - Config USB controller after PCI emulation\r
+ *\r
+ * @param[in] Value Controller PCI config address (bus# + device# + function#)\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ */\r
+VOID EhciInitAfterPciInit (IN UINT32 Value, IN AMDSBCFG* pConfig);\r
+/**\r
+ * OhciInitAfterPciInit - Config USB OHCI controller after PCI emulation\r
+ *\r
+ * @param[in] Value Controller PCI config address (bus# + device# + function#)\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ */\r
+VOID OhciInitAfterPciInit (IN UINT32 Value, IN AMDSBCFG* pConfig);\r
+\r
+/**\r
+ * SetEhciP11Wr - FIXME\r
+ *\r
+ * @param[in] Value Controller PCI config address (bus# + device# + function#)\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ */\r
+UINT32 SetEhciPllWr (IN UINT32 Value, IN AMDSBCFG* pConfig);\r
+\r
+\r
+/**\r
+ * usbInitBeforePciEnum - Config USB controller before PCI emulation\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+usbInitBeforePciEnum (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ // Disabled All USB controller\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, BIT7, 0);\r
+ // Clear PM_IO 0x65[4] UsbResetByPciRstEnable, Set this bit so that usb gets reset whenever there is PCIRST.\r
+ // Enable UsbResumeEnable (USB PME) * Default value\r
+ // In SB700 USB SleepCtrl set as BIT10+BIT9, but SB800 default is BIT9+BIT8 (6 uframes)\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint16 | S3_SAVE, ~BIT2, BIT2 + BIT7 + BIT8 + BIT9);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, 0, pConfig->USBMODE.UsbModeReg);\r
+}\r
+\r
+/**\r
+ * usbInitAfterPciInit - Config USB controller after PCI emulation\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+usbInitAfterPciInit (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGED, AccWidthUint8, ~BIT1, BIT1);\r
+\r
+ usb1EhciInitAfterPciInit (pConfig);\r
+ usb2EhciInitAfterPciInit (pConfig);\r
+ usb3EhciInitAfterPciInit (pConfig);\r
+ usb1OhciInitAfterPciInit (pConfig);\r
+ usb2OhciInitAfterPciInit (pConfig);\r
+ usb3OhciInitAfterPciInit (pConfig);\r
+ usb4OhciInitAfterPciInit (pConfig);\r
+\r
+ if ( pConfig->UsbPhyPowerDown ) {\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint8, ~BIT0, BIT0);\r
+ } else\r
+ {\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF0, AccWidthUint8, ~BIT0, 0);\r
+ }\r
+\r
+}\r
+\r
+/**\r
+ * usb1EhciInitAfterPciInit - Config USB1 EHCI controller after PCI emulation\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+usb1EhciInitAfterPciInit (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT32 ddDeviceId;\r
+ ddDeviceId = (USB1_EHCI_BUS_DEV_FUN << 16);\r
+ EhciInitAfterPciInit (ddDeviceId, pConfig);\r
+}\r
+\r
+/**\r
+ * usb2EhciInitAfterPciInit - Config USB2 EHCI controller after PCI emulation\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+usb2EhciInitAfterPciInit (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT32 ddDeviceId;\r
+ ddDeviceId = (USB2_EHCI_BUS_DEV_FUN << 16);\r
+ EhciInitAfterPciInit (ddDeviceId, pConfig);\r
+}\r
+\r
+/**\r
+ * usb3EhciInitAfterPciInit - Config USB3 EHCI controller after PCI emulation\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+usb3EhciInitAfterPciInit (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT32 ddDeviceId;\r
+ ddDeviceId = (USB3_EHCI_BUS_DEV_FUN << 16);\r
+ EhciInitAfterPciInit (ddDeviceId, pConfig);\r
+}\r
+\r
+VOID\r
+EhciInitAfterPciInit (\r
+ IN UINT32 Value,\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT32 ddBarAddress;\r
+ UINT32 ddVar;\r
+ //Get BAR address\r
+ ReadPCI ((UINT32) Value + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress);\r
+ if ( (ddBarAddress != - 1) && (ddBarAddress != 0) ) {\r
+ //Enable Memory access\r
+ RWPCI ((UINT32) Value + SB_EHCI_REG04, AccWidthUint8, 0, BIT1);\r
+ if (pConfig->BuildParameters.EhciSsid != NULL ) {\r
+ RWPCI ((UINT32) Value + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.EhciSsid);\r
+ }\r
+ //USB Common PHY CAL & Control Register setting\r
+ ddVar = 0x00020F00;\r
+ WriteMEM (ddBarAddress + SB_EHCI_BAR_REGC0, AccWidthUint32, &ddVar);\r
+ // RPR IN AND OUT DATA PACKET FIFO THRESHOLD\r
+ // EHCI BAR 0xA4 //IN threshold bits[7:0]=0x40 //OUT threshold bits[23:16]=0x40\r
+ RWMEM (ddBarAddress + SB_EHCI_BAR_REGA4, AccWidthUint32, 0xFF00FF00, 0x00400040);\r
+ // RPR EHCI Dynamic Clock Gating Feature\r
+ RWMEM (ddBarAddress + SB_EHCI_BAR_REGBC, AccWidthUint32, ~BIT12, 0);\r
+ // RPR Enable adding extra flops to PHY rsync path\r
+ // Step 1:\r
+ // EHCI_BAR 0xB4 [6] = 1\r
+ // EHCI_BAR 0xB4 [7] = 0\r
+ // EHCI_BAR 0xB4 [12] = 0 ("VLoad")\r
+ // All other bit field untouched\r
+ // Step 2:\r
+ // EHCI_BAR 0xB4[12] = 1\r
+ RWMEM (ddBarAddress + SB_EHCI_BAR_REGB4, AccWidthUint32, ~(BIT6 + BIT7 + BIT12), 0x00);\r
+ RWMEM (ddBarAddress + SB_EHCI_BAR_REGB4, AccWidthUint32, ~BIT12, BIT12);\r
+ //Set EHCI_pci_configx50[6]='1' to disable EHCI MSI support\r
+ //RPR recommended setting "EHCI Async Park Mode"\r
+ //Set EHCI_pci_configx50[23]='0' to enable "EHCI Async Park Mode support"\r
+ //RPR Enabling EHCI Async Stop Enhancement\r
+ //Set EHCI_pci_configx50[29]='1' to disableEnabling EHCI Async Stop Enhancement\r
+ RWPCI ((UINT32) Value + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(BIT23), BIT29 + BIT23 + BIT8 + BIT6);\r
+ // RPR recommended setting "EHCI Advance PHY Power Savings"\r
+ // Set EHCI_pci_configx50[31]='1'\r
+ // Fix for EHCI controller driver yellow sign issue under device manager\r
+ // when used in conjunction with HSET tool driver. EHCI PCI config 0x50[20]=1\r
+ RWPCI ((UINT32) Value + SB_EHCI_REG50 + 2, AccWidthUint16 | S3_SAVE, (UINT16)0xFFFF, BIT15);\r
+ // RPR USB Delay A-Link Express L1 State\r
+ // RPR PING Response Fix Enable EHCI_PCI_Config x54[1] = 1\r
+ // RPR Empty-list Detection Fix Enable EHCI_PCI_Config x54[3] = 1\r
+ RWPCI ((UINT32) Value + SB_EHCI_REG54, AccWidthUint32 | S3_SAVE, ~BIT0, BIT0);\r
+ if ( pConfig->BuildParameters.UsbMsi) {\r
+ RWPCI ((UINT32) Value + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~BIT6, 0x00);\r
+ }\r
+ }\r
+}\r
+\r
+/**\r
+ * usb1OhciInitAfterPciInit - Config USB1 OHCI controller after PCI emulation\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+usb1OhciInitAfterPciInit (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT32 ddDeviceId;\r
+ ddDeviceId = (USB1_OHCI_BUS_DEV_FUN << 16);\r
+ OhciInitAfterPciInit (ddDeviceId, pConfig);\r
+}\r
+\r
+/**\r
+ * usb2OhciInitAfterPciInit - Config USB2 OHCI controller after PCI emulation\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+usb2OhciInitAfterPciInit (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT32 ddDeviceId;\r
+ ddDeviceId = (USB2_OHCI_BUS_DEV_FUN << 16);\r
+ OhciInitAfterPciInit (ddDeviceId, pConfig);\r
+}\r
+\r
+/**\r
+ * usb3OhciInitAfterPciInit - Config USB3 OHCI controller after PCI emulation\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+usb3OhciInitAfterPciInit (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT32 ddDeviceId;\r
+ ddDeviceId = (USB3_OHCI_BUS_DEV_FUN << 16);\r
+ OhciInitAfterPciInit (ddDeviceId, pConfig);\r
+}\r
+\r
+/**\r
+ * usb4OhciInitAfterPciInit - Config USB4 OHCI controller after PCI emulation\r
+ *\r
+ *\r
+ *\r
+ * @param[in] pConfig Southbridge configuration structure pointer.\r
+ *\r
+ */\r
+VOID\r
+usb4OhciInitAfterPciInit (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT32 ddDeviceId;\r
+ ddDeviceId = (USB4_OHCI_BUS_DEV_FUN << 16);\r
+ OhciInitAfterPciInit (ddDeviceId, pConfig);\r
+ if (pConfig->BuildParameters.Ohci4Ssid != NULL ) {\r
+ RWPCI ((USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.Ohci4Ssid);\r
+ }\r
+}\r
+\r
+VOID\r
+OhciInitAfterPciInit (\r
+ IN UINT32 Value,\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ // Disable the MSI capability of USB host controllers\r
+ RWPCI ((UINT32) Value + SB_OHCI_REG40 + 1, AccWidthUint8 | S3_SAVE, 0xFF, BIT0);\r
+ RWPCI ((UINT32) Value + SB_OHCI_REG50, AccWidthUint8 | S3_SAVE, ~(BIT5 + BIT12), 0x00);\r
+ // RPR USB SMI Handshake\r
+ RWPCI ((UINT32) Value + SB_OHCI_REG50 + 1, AccWidthUint8 | S3_SAVE, ~BIT4, 0x00);\r
+ // SB02186\r
+ RWPCI ((UINT32) Value + SB_OHCI_REG50 + 1, AccWidthUint8 | S3_SAVE, 0xFC, 0x00);\r
+ if (Value != (USB4_OHCI_BUS_DEV_FUN << 16)) {\r
+ if ( pConfig->BuildParameters.OhciSsid != NULL ) {\r
+ RWPCI ((UINT32) Value + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.OhciSsid);\r
+ }\r
+ }\r
+ //RPR recommended setting to, enable fix to cover the corner case S3 wake up issue from some USB 1.1 devices\r
+ //OHCI 0_PCI_Config 0x50[30] = 1\r
+ RWPCI ((UINT32) Value + SB_OHCI_REG50 + 3, AccWidthUint8 | S3_SAVE, ~BIT6, BIT6);\r
+ if ( pConfig->BuildParameters.UsbMsi) {\r
+ RWPCI ((UINT32) Value + SB_OHCI_REG40 + 1, AccWidthUint8 | S3_SAVE, ~BIT0, 0x00);\r
+ RWPCI ((UINT32) Value + SB_OHCI_REG50, AccWidthUint8 | S3_SAVE, ~BIT5, BIT5);\r
+ }\r
+}\r
+\r
+\r
+UINT32\r
+SetEhciPllWr (\r
+ IN UINT32 Value,\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT32 ddRetureValue;\r
+ UINT32 ddBarAddress;\r
+ UINT16 dwVar;\r
+ UINT16 dwData;\r
+ UINT8 portSC;\r
+ ddRetureValue = 0;\r
+ dwData = 0;\r
+ // Memory, and etc.\r
+ //_asm { jmp $};\r
+ RWPCI ((UINT32) Value + 0xC4, AccWidthUint8, 0xF0, 0x00);\r
+ RWPCI ((UINT32) Value + 0x04, AccWidthUint8, 0xFF, 0x02);\r
+ // Get Bar address\r
+ ReadPCI ((UINT32) Value + 0x10, AccWidthUint32, &ddBarAddress);\r
+ for (portSC = 0x64; portSC < 0x75; portSC += 0x04 ) {\r
+ // Get OHCI command registers\r
+ ReadMEM (ddBarAddress + portSC, AccWidthUint16, &dwVar);\r
+ if ( dwVar & BIT6 ) {\r
+ ddRetureValue = ddBarAddress + portSC;\r
+ RWMEM (ddBarAddress + portSC, AccWidthUint16, ~BIT6, 0);\r
+ for (;;) {\r
+ SbStall (5);\r
+ ReadMEM (ddBarAddress + portSC, AccWidthUint16, &dwData);\r
+ if (dwData == 0x1005) break;\r
+ }\r
+ dwData = 0;\r
+ }\r
+ }\r
+ return ddRetureValue;\r
+}\r
+\r
+VOID\r
+usbSetPllDuringS3 (\r
+ IN AMDSBCFG* pConfig\r
+ )\r
+{\r
+ UINT32 resumeEhciPortTmp;\r
+ UINT32 resumeEhciPort;\r
+ resumeEhciPortTmp = 0;\r
+ resumeEhciPort = 0;\r
+// UINT32 ddDeviceId;\r
+//if Force Port Resume == 1\r
+// {\r
+// clear Force Port Resume;\r
+// while (!(PORTSC == 0x1005)){wait 5 us; read PORTSC;}\r
+// }\r
+ if (pConfig->USBMODE.UsbModeReg & BIT1) {\r
+ resumeEhciPortTmp = SetEhciPllWr (USB1_EHCI_BUS_DEV_FUN << 16, pConfig);\r
+ if (resumeEhciPortTmp > 0) resumeEhciPort = resumeEhciPortTmp;\r
+ }\r
+ if (pConfig->USBMODE.UsbModeReg & BIT3) {\r
+ resumeEhciPortTmp = SetEhciPllWr (USB2_EHCI_BUS_DEV_FUN << 16, pConfig);\r
+ if (resumeEhciPortTmp > 0) resumeEhciPort = resumeEhciPortTmp;\r
+ }\r
+ if (pConfig->USBMODE.UsbModeReg & BIT5) {\r
+ resumeEhciPortTmp = SetEhciPllWr (USB3_EHCI_BUS_DEV_FUN << 16, pConfig);\r
+ if (resumeEhciPortTmp > 0) resumeEhciPort = resumeEhciPortTmp;\r
+ }\r
+\r
+ RWPCI ((UINT32) (USB1_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, 0);\r
+ RWPCI ((UINT32) (USB2_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, 0);\r
+ RWPCI ((UINT32) (USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, 0);\r
+ RWPCI ((UINT32) (USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, 0);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF3, AccWidthUint8, 0, 0x20);\r
+ SbStall (10);\r
+ RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGF3, AccWidthUint8, 0, 0x00);\r
+ RWPCI ((UINT32) (USB1_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, BIT29);\r
+ RWPCI ((UINT32) (USB2_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, BIT29);\r
+ RWPCI ((UINT32) (USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, BIT29);\r
+ RWPCI ((UINT32) (USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32, ~BIT29, BIT29);\r
+\r
+ if (resumeEhciPort > 0) {\r
+ RWMEM (resumeEhciPort, AccWidthUint8, ~BIT7, BIT7);\r
+ SbStall (4000);\r
+ RWMEM (resumeEhciPort, AccWidthUint8, ~BIT6, BIT6);\r
+ }\r
+\r
+ RWPCI ((UINT32) (USB1_EHCI_BUS_DEV_FUN << 16) + 0xC4, AccWidthUint8, 0xF0, 0x03);\r
+ RWPCI ((UINT32) (USB2_EHCI_BUS_DEV_FUN << 16) + 0xC4, AccWidthUint8, 0xF0, 0x03);\r
+ RWPCI ((UINT32) (USB3_EHCI_BUS_DEV_FUN << 16) + 0xC4, AccWidthUint8, 0xF0, 0x03);\r
+\r
+}\r
+\r
projects / coreboot.git / commitdiff