libpayload: Add iterators for CMOS variables

Provide functions that pick the first CMOS variable defined
in the cmos layout, and from there, the next one.

Change-Id: Ie98146de7f6273089fc6fc0b232a4b94337cf8a3
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/587
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

libpayload: Expose options_checksum_valid

options_checksum_valid can be used as a fast test to
identify invalid CMOS data by checking the checksum.

Change-Id: I44635d4c5d389579ad82435907ba8658e1bd44bb
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/586
Reviewed-by: Bernhard Urban <lewurm@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

libpayload: Provide interpretation of CMOS data structures

Add new functions that allow using string based key/value access to
CMOS, including support for enums.

Change-Id: Ibe238eff4c5230e5f61004c88221cd34393873aa
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/585
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

libpayload: Add access to CMOS images in memory space

Provide access to CMOS images in RAM or CBFS, such as cmos.defaults

Change-Id: Ifa70dea6206d94c0c271caf9ae1152fc76b5d51a
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/584
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

i3100: configure pci irqs

without it, you can't boot from PCI devices like scsi controllers
which require an interrupt set. So preconfigure all pci devices.

Change-Id: I2cd781227701e8363d83bd90e0e36994359fc194
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/603
Tested-by: build bot (Jenkins)

libpayload: Refactor highlevel CMOS access

This will allow using libpayload functions to access CMOS data in
template files in RAM or CBFS.

Change-Id: I323ed625e657cbdc1fae8c279a82ee578e83ad00
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/583
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

CIMX wrapper: remove redudant traversing sb800 and sb900 CIMX dir

AGESA and CIMX build changed from commit 2a830d0b,
sb800 and sb900 CIMX dir already traversed in vendorcode Makefile.

Change-Id: I5101b22e140725337bf5074b9170e582c8e3bf40
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/602
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

SB700 southbridge: AMD SB700/SP5100 southbridge CIMX code

Support AMD SB700 and SP5100 chipsets.

Change-Id: I0955abf7f48a79483f624b46a61b22711315f888
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/560
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

RD890 Northbridge: AMD RD890/SR56X0 Northbridge CIMX code

Change-Id: If9908ffeb5b707a660db38dc44f5118347cbcc06
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/557
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Add Intel i5000 Memory Controller Hub

Change-Id: Ic169f3f61babfcfa2ddcb84fc0267ebcf8c5f3bb
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/491
Tested-by: build bot (Jenkins)

i3100: add sata_ports_implemented option

BIOS needs to set the bit mask which ports are iplemented on the
board. Without setting this option, seabios fails to boot from
SATA.

Change-Id: I21de3fde3a9cff7c590226f70fa549274f36e2a8
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/601
Tested-by: build bot (Jenkins)

i3100: Add init sequence

i3100 misses the magic SATA init sequence, which makes all
requests fail. Captured from the vendor BIOS, which writes
those bits on all configurations.

Change-Id: I293b7d9cd681181311ecaced6d7df9b2706c711f
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/600
Tested-by: build bot (Jenkins)

X86: fix cpu_phys_address_size()

CPUs with CPUID level >= 0x80000008 can return
the number of physical address bits.

Change-Id: I1c0523b6a091c476af838d173ed9030280360d7f
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/599
Tested-by: build bot (Jenkins)

X60/T60: Add option to enable/disable bluetooth

Change-Id: I9761a8a9a7cc708fe95169cb8b79b413b97ee523
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/598
Tested-by: build bot (Jenkins)

X60: fix docking

Fix ordering of power/reset/undock procedure to prevent
crashes seen with the old code. Also call dlpc_init()
only once.

Change-Id: I27d1f42e845fcccde40e6ca5af4a7762edab5d36
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/597
Tested-by: build bot (Jenkins)

mainboard/lenovo/t60, x60: Disable CHECK_SLFRCS_ON_RESUME

This makes resume from S3 work.

Change-Id: I472baf2fbde46bfac223ce39fc81b8e09849fb7f
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/591
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>

northbridge/intel/i945: CHECK_SLFRCS_ON_RESUME Kconfig option

Originally brought up by Sven Schnelle in March 2011
http://patchwork.coreboot.org/patch/2801/
http://www.coreboot.org/pipermail/coreboot/2011-March/064277.html

On some mainboards it may be neccessary to reset early during resume
from S3 if the SLFRCS register indicates that a memory channel is not
guaranteed to be in self-refresh.

On other mainboards, such as Lenovo X60 and T60, the check always
creates false positives, effectively making it impossible to resume.

The SLFRCS register is documented on page 197 of

Mobile Intel® 945 Express Chipset Family Datasheet
Document Number: 309219-006

which is publically available, and the register indicates if a memory
channel is guaranteed to be in self-refresh mode (if bit = 1), or that
a memory channel *may or may not be* in self-refresh mode (if bit = 0).

The register can thus only be used to positively learn that memory is
in self-refresh. It is not known for sure that memory is *not* in
self-refresh. The register is reset by the PWROK signal, which *should*
go low during S3, and go high again when resuming, so it is unsurprising
that SLFRCS has already been cleared when we read the register.

Sven's measurements of the CKE signal on a ThinkPad shows that memory
remains in self-refresh indefinitely, until coreboot re-initializes the
memory controller, even when SLFRCS bits were = 0.

Boards which require a warm reset when SLFRCS bits are cleared must now
explicitly enable the check in the mainboard Kconfig file.

This commit selects the new option in all existing i945 mainboards.
A follow-up commit will remove the option for ThinkPads.

Change-Id: I02320675efb8fde05c371ef243ba5093a4da6d11
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/590
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>

X60/T60: fix default baudrate

Value required to get 115200 is actually 0, not 5.

Change-Id: Id1385822bf2213c035c4f378a72168ed6676ad03
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/592
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)

pcengines: align VENDOR_ and BOARD_ names for PC engines

Coming changes to abuild require that VENDOR_ and BOARD_ names have
common suffixes.

Change-Id: I44cf759dd3b2d02c525eb325dc9c5c989f172ac5
Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
Reviewed-on: http://review.coreboot.org/548
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

vga: removed inclusion of .c files

Add local vga.h for prototypes.

Change-Id: I5ff627c6420d4b7fd1bc9a537f406ef6d9597522
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/588
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Make Geode GX2 VGA setup work.

Add MSR register write for VGA memory setup
Add missing license
Add bit explanation

Change-Id: I1cb36eeccd84f0056c829f50d9864047654ce906
Signed-off-by: Nils Jacobs <njacobs8@adsltotaal.nl>
Reviewed-on: http://review.coreboot.org/580
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

pci_ops_mmconf: Move conditional compilation to Makefile

Moved the conditional compilation out of the source file

Change-Id: Ic4045006f39d70f4a0bc37d1bd5e073ed8477c68
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-on: http://review.coreboot.org/578
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

libpayload: Allow using CBFS functions on images in RAM

Two new functions allow switching the CBFS functions from using RAM
or ROM, with ROM as default.

Change-Id: I04d67ad622d25c5728ae9a63f5b8a3dc9bbacce6
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/550
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

AGESA F15: AMD family15 AGESA code

AMD AGESA code to support Orochi platform family15 model 00-0fh processores,
AMD C32, G34, and AM3r2 Sockets are supported.

Change-Id: If79392c104ace25f7e01db794fa205f47746bcad
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/554
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

dumpmmcr: Fix compilation warnings in printf

cf., `man 3 printf`

Change-Id: Ib78937a3e1c1eecf884bde0860594cbdb574f1fe
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-on: http://review.coreboot.org/582
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)

Mahogany Fam10 MPtable fix

Make changes MPtable to match ACPI tables.

Change-Id: I387f301370582fcb5e0d348d793333a919d2f373
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/575
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

RD890: pci_ids update

RD890 CIMX support AMD RD890TV, RX780, RD780, SR56x0, RD890 and 990FX
chipsets, add their pci device id respectively.

Change-Id: I30c62c5802279ff2ee8da1cae41395e6899339bb
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/558
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

AMD Mahogany Fam10 ACPI table fixes.

Fix the ACPI IRQ routing. Also. fix the SSDT generations and TOM2 fixup.

Change-Id: I03e6de7bb58440058306c9c9888eb2961748c385
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/574
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

pci_ops_conf: Indentation fixes

Indentation fixes in src/arch/x86/lib/pci_ops_conf{1,2}.c

Change-Id: I56e8ff6d2ee3a0b871b40577e10c99dea4b3b1bd
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-on: http://review.coreboot.org/576
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

pci_ops_mmconf: Indentation fixes

Indentation fixes in src/arch/x86/lib/pci_ops_mmconf.c

Change-Id: If8337bae06295db16ed1c129ab76dea37eb465ae
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-on: http://review.coreboot.org/577
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

post code: Replaced hard-coded post code with macro

Added a macro in the post code list, which replaces hard coded
value in cpu/x86/cache/cache.c

Change-Id: I27cb27827272584a8a17a41c111e2dc155196a97
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-on: http://review.coreboot.org/572
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

trivial: spelling fixes in comments

Few spelling fixes in entry16.inc

Change-Id: Iad3d18eee3f498171cb766589aaebefdcf0e9767
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-on: http://review.coreboot.org/571
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

adm1026: removed prototype

Removed the prototype and restructured the code

Change-Id: I13a648acf7bae30635e0469e301ce5635d9d7a8c
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-on: http://review.coreboot.org/570
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Leave SSE and MMX instructions enabled in coreboot

In order to use SSE+MMX optimized payloads we don't want to disable SSE+MMX
instructions in the CPU after romstage.

Change-Id: I51aeb01f04492ad7bc8b1fe181a4ae17fe0ca61e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/553
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Clean up AMD romstage.c serial output

This cleans up the strings in romstage.c, removing the ugly "got past".
Also, cleaned up comments and some spacing.

Change-Id: I0124df76eb442f8a0009a31a8632e4fd67ed7782
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/539
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Add subsystem callbacks for VT8237x and VT890 family of chipsets

Change-Id: Id34615f0c229d276d72cdf984cf82ea8cc1a85bb
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/523
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Remove duplicated line of code in AMD wrappers.

This line was unnecessary and was duplicated on several mainboards.

Change-Id: I438da05c770ded0bd32256f1c157cabcc383667a
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/541
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Remove old AMD #define

The #define REQUIRED_CALLOUTS is no longer used on these platforms.

Change-Id: I536eb94119f1bc8f81e59ebefacdd4e04d0ed3ef
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/540
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Clean up AMD romstage.c whitespace indent issues

Change-Id: I1713f1a3b548cb8e8ea5cf57eef95486ceb05ab9
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/538
Tested-by: build bot (Jenkins)
Reviewed-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

libpayload: style: compare null-pointers with NULL, not 0

Change-Id: I5efbfb75e2894bc8d8e50c8737cfee9738d15eda
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/551
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>

Add coreboot version to id area

There was no good way to extract the build version from an image.

This change will be mostly backward compatible: The only assumption
that could break is that the board name string ends directly before
the 3 dwords that represent .id's "header".

Change-Id: I325491a0c42911d9d6ecd59e21ee1b756c987693
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/537
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)

Unify ID_SECTION_OFFSET and mark it deprecated

We used to put the id section at -0x10, with some boards overriding
this to avoid collisions with romstraps.
Hardcode the location at -0x80, at the possible expense of some space
(0x70 bytes).
This also makes the section easier to find in a binary image.

At some point, CONFIG_ID_SECTION_OFFSET can be removed, so this option
is moved to src/Kconfig.deprecated_options.

Change-Id: I6ce2d6e94e57717939bda070bfe0c9df80ca2a89
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/549
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>

lib: add ram_check_nodie

The current implementation calls die() if memory checking fails.
This isn't always what we want: one might want to print error registers,
or do some other error handling. Introduce ram_check_nodie() for that
reason. It returns 0 if ram check succeeded, otherwise 1.

Change-Id: Ib9a9279120755cf63b5b3ba5e0646492c3c29ac2
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/532
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

W83627HF: remove unused function

When CONFIG_EXPERT is set, compilation fails with:

src/superio/winbond/w83627hf/superio.c:61:13: error: ‘w83627hf_16_bit_addr_qual’ defined but not used [-Werror=unused-function]
cc1: all warnings being treated as errors

This function isn't used in the code, so just remove it.

Change-Id: I117e221fb3c3a20a7d7e7e2e86d7dbfdffc2cbff
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/533
Tested-by: build bot (Jenkins)

MTRR: get physical address size from CPUID

The current code uses static values for the physical address size
supported by a CPU. This isn't always the right value: I.e. on
model_6[ef]x Core (2) Duo CPUs physical address size is 36, while
Xeons from the same family have 38 bits, which results in invalid
MTRR setup. Fix this by getting the right number from CPUID.

Change-Id: If019c3d9147c3b86357f0ef0d9fda94d49d811ca
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/529
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Add missing HAVE_HARD_RESET

Change-Id: I6b612dbd3eb6e8cc45f1c7abca85732fb64de98c
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/531
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)

i945: fix tsc udelay()

The comparision is the wrong way round: as long as tsc
is below tsc1, the timeout is not reached

Change-Id: I75de74ef750b5a45be0156efaf10d7239a0b1136
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/530
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

libpayload: Remove bitfield use from EHCI data structures

We agreed that bitfields are a Bad Idea[tm].

Change-Id: If4c4cb748af340e2721b89fea8e035da0632971f
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/480
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Peter Stuge <peter@stuge.se>

libpayload: Remove bitfield use from UHCI data structures

We agreed that bitfields are a Bad Idea[tm].

Change-Id: I1b2bcda28c52ad10bbe9429e04d126b555f7828a
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/478
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Peter Stuge <peter@stuge.se>

libpayload: Remove bitfield use from OHCI data structures

We agreed that bitfields are a Bad Idea[tm].

Change-Id: Ic04f151091c359912835b8b3db488d2d41bd4bbb
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/479
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Peter Stuge <peter@stuge.se>

Un-perl commit-msg hook

To simplify installation on mingw a bit (even though git remains a pain),
drop the perl dependency the commit-msg hook introduced to the coreboot
development environment.
It's replaced by awk which we use elsewhere already (and is a more lightweight
utility in any case)

Change-Id: I67adfe1ec43c898735d4bae4819ceb53e83c303b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/78
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>

Fix Geode GX2 + LX caching for tiny bootblock.

Change-Id: If681a33deb7df752b37c6a8a20482d3c374af936
Signed-off-by: Nils Jacobs <njacobs8@adsltotaal.nl>
Reviewed-on: http://review.coreboot.org/528
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Philip Prindeville <philipp@redfish-solutions.com>

ACPI: mark empty get_cst_entries() weak

This function prevents the linker from choosing the right
get_cst_entries(), preventing writing the _CST tables.

Change-Id: I4bc0168aee110171faeaa081f217dfd1536bb821
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/496
Tested-by: build bot (Jenkins)

rs780: correct comment in switching_gpp_configurations()

Change-Id: I6417a92523eea7307d080669fbc4e16ee28c8a6c
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/524
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

adm1027: add return statement

Adds a missing return statment which will stop misleading the users

Change-Id: I53741f1136b396e9493ce959b54efc00c9b09764
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-on: http://review.coreboot.org/522
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

inteltool: Add support for dumping AMB registers

Change-Id: I98615725afdb315caa67b2226224e3eb2a0e4393
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/525
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

.gitignore ectool, inteltool, msrtool, nvramtool and superiotool

Change-Id: I06e69d97ef3646f79104ec316ce932cc53894c92
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/485
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Eliminate magic numbers

Use sizeof() on vendor and part# rather than explicit memory length.

Change-Id: I2b7e0e4a8df6448d027cc61867382f161eb990d3
Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
Reviewed-on: http://review.coreboot.org/504
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Cleanup access to vendor/part # info

Instead of macros to access MAINBOARD record, use convenience functions.

Store pointers to MAINBOARD and HEADER for use outside of CB code.

Change-Id: I074e3a0df7d25726cbd942538bfdc5a63dd17e12
Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
Reviewed-on: http://review.coreboot.org/502
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Update geode GX2 tree to match LX.

Change-Id: I5b99c531e44ea09990b9da0b97213fb7945f34ee
Signed-off-by: Nils Jacobs <njacobs8@adsltotaal.nl>
Reviewed-on: http://review.coreboot.org/512
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

rs780: use bitwise rather than boolean not

Change-Id: Ie3872c57990f9784aafda14f8c7fc842b3a65260
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/518
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>

Indentation: Various indentation fixes

Fixed indentation using indent tool in the src/drivers/i2c tree

Change-Id: I5b396e5753544aff13ac5d16afc59e193a6b1da1
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-on: http://review.coreboot.org/506
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>

Fix Fam14 AGESA ACPI table generation

The AGESA wrapper init late call generates the SSDT and other ACPI tables. The
call was failing without heap space allocated causing the ASSERT messages in
the output. I think are there may still be other issues in integrating the
SSDT table with the DSDT, but now it is there to debug.

The changes were made in Persimmon and copied to the other Fam14 mainboards.
Change-Id: I2cfd14e07cb46d2f46f5a8cd21c4c9aab44e4ffd
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/517
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

Clean up AMD Fam14 SSDT

The old SSDT ACPI code would only include the AGESA or the coreboot SSDT. Now
include both. AGESA generates the Pstate SSDT and the second coreboot SSDT is
for TOM and TOM2. Now, generate the coreboot SSDT instead of patching it. This
fixes some ACPI errors in Linux and Windows bluescreens.

The Persimmon acpi_tables.c is where the main changes were made and then
replicated in the other Fam14 boards. Please test the other mainbords if you
have one.

Change-Id: I808c863597e024e3e8aeec0821e8618d96cc96a6
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/516
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

Fix Fam14 mainboard whitespace

Fix whitespace and tab issues on fam14 mainbords in preperations for upcoming
changes

Change-Id: I6d63d428dde0a5d9748027e603b03de25d3be472
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/515
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

rs780: power down GPPSB SB lane pads in correct PCIe core

Change-Id: I059d5b155cae051f31cc2495f8a47d53e01af808
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/519
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>

Add missing EOT marker.

Omitted from commit 3d1d6bb4ecb15a12f48f871c623882bee9c0c576

Change-Id: Id3e94d615d50f0673cc5e3fde77ed6748d26ebd3
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Reviewed-on: http://review.coreboot.org/514
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
Reviewed-by: Philip Prindeville <pprindeville@gmail.com>

F14 mainboard: mptable update

Add GNB internal graphic interrupt,
correct southbridge hd audio device interrupt. and remove the
dead code already commented out.

south_station, union_station, inagua, persimmon and e350m1 mainboard
are included herein.

Change-Id: Ic7618d80e0432ed0e22d1c16e1adb8ba6cea2e59
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Reviewed-on: http://review.coreboot.org/451
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

F14 mainboard: update acpi interrupt routing in pic and apic mode

Add interrupt routing for APU GNB internal Graphic and HD audio device, and
other pcie bridge device in GNB.

south_station, union_station, inagua, persimmon and e350m1 mainboard
are included herein.

Change-Id: I4b6e0fce8d34637c03de8ebfdadea008c98e193b
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Reviewed-on: http://review.coreboot.org/452
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

White space and coding style fixes.

Change-Id: I14f39b5666fc18e8183723ec78a40a849d337736
Signed-off-by: Nils Jacobs <njacobs8@adsltotaal.nl>
Reviewed-on: http://review.coreboot.org/511
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>

Fix Fam10 MMCONF_SUPPORT_DEFAULT setting.

I misunderstood how kconfig select works. It needs to be selected with a config option. Moved the select to the correct location.

Change-Id: If9b1e21e6cbc5af4671efb76cf87dd18dbbe2234
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/487
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

trivial:change the value type of POST_PORT in Kconfig from int to hex

trivial change in src/console/Kconfig

Change-Id: Ib6bb4ccfabaa3af18b48a23a51a576b872d807a8
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-on: http://review.coreboot.org/505
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Sconfig: parse Kconfig options from devicetree.cb

Mainboard and chip Kconfig files have several build options that
are redundant with information in devicetree.cb. This patch enables
sconfig to auto-generate equivalent configuration.

  sconfig -s

Generates mainboard's static.c file, as before.

  sconfig -b

This operation creates mainboard's bootblock init code. By default,
for every chip listed in mainboard/devicetree.cb, if there is a
chip/bootblock.c file, the init function is called.
A mainboard/bootblock.c file can be added to override default
behaviour.

  sconfig -k

This operation generates select -options for component paths.

Change-Id: I808d44af552dbc5e0565d6a0f4f72c7be9f5740e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/472
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Only BSP CPU writes CMOS in bootblock code

CMOS accesses are not safe for multi-processor and only the BSP CPU
should count reboots and test CMOS sanity.

A questionable single byte CMOS read access from AP CPUs remains.
AP CPUs should always select the same romstage prefix as BSP CPU.

Change-Id: I29118e33c07c0080c94abb90f703e38312c72432
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/446
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

libpayload: remove uhci_reg_maskX

Not that good an idea to start with.

Coccinelle patch:
@@
@@
-void
(
-uhci_reg_mask8
|
-uhci_reg_mask16
|
-uhci_reg_mask32
)
- (...) { ... }

@@
@@
-void
(
-uhci_reg_mask8
|
-uhci_reg_mask16
|
-uhci_reg_mask32
)
- (...);

@@
expression ctrl, reg, ormask;
@@
-uhci_reg_mask32 (ctrl, reg, ~0, ormask)
+uhci_reg_write32 (ctrl, reg, uhci_reg_read32 (ctrl, reg) | ormask)

@@
expression ctrl, reg, ormask;
@@
-uhci_reg_mask16 (ctrl, reg, ~0, ormask)
+uhci_reg_write16 (ctrl, reg, uhci_reg_read16 (ctrl, reg) | ormask)

@@
expression ctrl, reg, ormask;
@@
-uhci_reg_mask8 (ctrl, reg, ~0, ormask)
+uhci_reg_write8 (ctrl, reg, uhci_reg_read8 (ctrl, reg) | ormask)

@@
expression ctrl, reg, andmask;
@@
-uhci_reg_mask32 (ctrl, reg, andmask, 0)
+uhci_reg_write32 (ctrl, reg, uhci_reg_read32 (ctrl, reg) & andmask)

@@
expression ctrl, reg, andmask;
@@
-uhci_reg_mask16 (ctrl, reg, andmask, 0)
+uhci_reg_write16 (ctrl, reg, uhci_reg_read16 (ctrl, reg) & andmask)

@@
expression ctrl, reg, andmask;
@@
-uhci_reg_mask16 (ctrl, reg, andmask, 0)
+uhci_reg_write16 (ctrl, reg, uhci_reg_read16 (ctrl, reg) & andmask)

Change-Id: Id0eb8327293831e54249d43fd06d50963c793699
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/477
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Let lib_get_sysinfo() pass through the success of get_coreboot_info()

The return status of get_coreboot_info() might be handy to a platform
driver calling lib_get_sysinfo() to test for the presence of coreboot.

Change-Id: I0176c93ee92c9dff733112026ee50f2ca797bdff
Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
Reviewed-on: http://review.coreboot.org/503
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Fix missing cast back to void *

MEM_RANGE_PTR() also needs to return a pointer to untyped memory.

Change-Id: I0ec64ad7bdb136d5e1a999bff3df6fa66eb29bf1
Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
Reviewed-on: http://review.coreboot.org/500
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Fix missing VM mapping

When processing FORWARD records, we weren't accounting for the pointer
being in the physical address space and not the virtual space instead.

Change-Id: I35ef637fbec7886d4cfeac5fd650a17eae8d555a
Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
Reviewed-on: http://review.coreboot.org/499
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Use void pointers for untyped memory

To avoid unnecessary casts, we can use untyped pointers when accessing
individual records.

Change-Id: I1d628d6e25f1e53b4fee34e7c2c4688a789c45a3
Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
Reviewed-on: http://review.coreboot.org/498
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Use convenience function to checksum

That coreboot uses the IP checksum is an artifact, not a deliberate
requirement to be compatible with the Internet Protocole suite. Use
a wrapper to abstract the computation of coreboot's checksum.

Change-Id: I6491b9ba5efb9ffe5cb12a6172653a6ac80a1370
Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
Reviewed-on: http://review.coreboot.org/497
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Replace UNPACK_CB64 macro with inline

Having submitted a module based on coreboot to LKML for acceptance,
it was requested that fewer macros and more inlines be used (because
of their superior type-checking when performing pointer casts, etc).

This is the first of several changes to make the relevant parts of
coreboot comply to linux code standards.

Change-Id: Iffe7061fa62fa639e0cb6ccb9125eb3403d06b1a
Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
Reviewed-on: http://review.coreboot.org/495
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

south_station: Enable GNB hd audio

Enable HD audio over HDMI.
Tested in Ubuntu-11.10 with ATI Catalyst Proprietary Driver installed.

Change-Id: I013c2c15ee56a7b134d980da1aa1856778a1eb4c
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Reviewed-on: http://review.coreboot.org/450
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

Add RS780 defaut graphics ID to AMD Mahogany mainboard.

Added the default ID to the mainboard Kconfig.

Change-Id: Ie5d39ccdda9d4f5a86214b5bd9ca629070ff152a
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/488
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)

Respect linker order

Linking fails when using -Wl,--as-needed and/or esp. when forcing --as-needed
through a compiler specs file.
A proper compile/link command would look like: $(CC) $(CFLAGS) $(LDFLAGS) -o foo
$(OBJS) $(LIBS). So the *FLAGS must be passed *before* the objects while the
libraries/dependencies must be passed *after* the objects.
For more details see: http://www.gentoo.org/proj/en/qa/asneeded.xml

Change-Id: I5a5b05e1cab8a2d88ce56c92d9b2f991ca1ee6c0
Signed-off-by: Christian Ruppert <idl0r@qasl.de>
Reviewed-on: http://review.coreboot.org/494
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

kbd: wait longer for self-test on keyboard reset

Some keyboards take pretty long to respond to a reset command, some even
delay the ACK to the command. To make the keyboard driver more robust,
increase the timeout for this special command. Also do an interface test
after the self-test to ensure the keyboard is functioning properly.

Another point is to reenable the keyboard *after* the scancode was set,
not before. We also set the system bit when enabling the keyboard
because this seems to be what older operating systems do expect.

One of the problematic keyboards, which will work with this patch
applied, is the DELL RT7D20. Without the patch an overly optimistic
operating system, read Linux 2.4, will not recognise the keyboard
because coreboot didn't fully initialize it.

Change-Id: I28c8e05bdde61f71b7de084c96bc2447c1b9575e
Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
Reviewed-on: http://review.coreboot.org/486
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Persimmon audio codec verb patch.

Verb data is required for the HDA audio codec in the sb800 southbridge. Verb
data is not required for mainboards that use G-Series HDMI. It is also a setting
the may be boards specific. This fixes issues with Windows audio on Persimmon.

Change-Id: I067506871e92078d122cf79872363d8937d47e50
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/490
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

.gitignore util/crossgcc/build-* and unpacked source directories

Change-Id: I85b9dffbbe0c7f1ae8cc2b584196775ba2f816df
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/484
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Lenovo X60/T60: add first_battery setting

The EC allows to select the order in which batteries are (dis)charged.
Make this setting available to the user.

Change-Id: Id2a98192565419dbb53f3a7cf0b2c46b672a3ed8
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/475
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Peter Stuge <peter@stuge.se>

asus k8v-x: explicitly set RAM and bus voltages

Change-Id: I9426cafc252ee765d723af569c4a90e090d313d9
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/482
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>

k8: add CONFIG_K8_FORCE_2T_DRAM_TIMING and enable it for asus k8v-x

Change-Id: Ia457f92f6fb7e287defb838db07f12d0f1766757
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/481
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>

Fix console output in real mode int10 implementation.

Checking RBIL, int10 AH=0x10 does never output a character.
The two output functions are AH=0x09 and AH=0x0e.

Change-Id: Id7f4d260b63024748ef771f949e8b60f934bacbc
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/483
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

libpayload: add set_option() function

It allows to change CMOS values from payloads

Change-Id: I4872fc27476923adafe13504126235b92b30de85
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/445
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Fix CMOS handling for non-USE_OPTION_TABLE configuration

The read_option macro still emitted CMOS_VSTART_*/CMOS_VEND_* symbols,
which fail without an option table (as no option_table.h defines them).

Discard them by using a macro instead of a static inline function.

Change-Id: I8d001f971681277a344b6788725746491546b607
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/442
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Use MMCONF for all AMD family 10 CPUs.

This fixes problems in AP init when multiple APs are trying to access
PCI config space. All Fam10 CPUs setup and support MMCONF.

Change-Id: I00a25bbf4e4152c89024f14a3c4c1c36b48d0128
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/455
Tested-by: build bot (Jenkins)
Reviewed-by: Alec Ari <neotheuser@ymail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Change DSDT Table ID for M4A785T-M board

Change the DSDT Table ID for M4A785T-M
from M4A785-M to M4A785T-M.

This fixes a small copypasta.

This is an updated patch set.

Change-Id: I43ee024222cf04d03685ffaee616971100cc9e6c
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/474
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Fix ldscript for bootblock .rom section

Allocation size for the section was miscalculated, so the section
did not honour its upper-bound address.

Also align the section start to 4 bytes, so it starts with code
instead of pad bytes.

Change-Id: Ic2a43981836a0873b50abecfcad2def7b6586a5d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/453
Tested-by: build bot (Jenkins)
Reviewed-by: Alec Ari <neotheuser@ymail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Fix AMD 8132 and 8151 southbridge builds

Untested, changes ramstage build for boards:
  supermicro/h8qme_fam10
  amd/serengeti_cheetah
  amd/serengeti_cheetah_fam10

AMD 8132 was not built for any mainboard due to a typo.

AMD Serengeti Cheetah:
  Chip 8151 is referenced in devicetree.cb but was not built.

AMD Serengeti Cheetah Family10:
  There are indications the board has 8151, but it is not listed
  in the devicetree.cb. The 8151 chip is not added in the build.

Change-Id: I03acdfcc3f3440bd32e81a9a696159903bbbcb50
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/471
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

Bootblock does not need a unique boot_cpu()

Detection of a CPU being a BSP CPU is not dependent of the existence
of northbridge and/or southbridge init code in the bootblock.

Even if CONFIG_LOGICAL_CPUS==0, boot_cpu() can get executed on an AP
CPU of a hyper-threading CPU and needs to return actual BSP bit from
MSR.

Change-Id: I9187f954bb357ba1dbd459cfe11cc96cb7567968
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/447
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

RS780: print the vgainfo

With this commit the vgainfo is printed and looks like that on the serial console:
vgainfo:
  ulBootUpEngineClock:50000
  ulBootUpUMAClock:66700
  ulBootUpSidePortClock:0
  ulMinSidePortClock:0
  ulSystemConfig:0
  ulBootUpReqDisplayVector:0
  ulOtherDisplayMisc:0
  ulDDISlot1Config:0
  ulDDISlot2Config:0
  ucMemoryType:0
  ucUMAChannelNumber:1
  ucDockingPinBit:0
  ucDockingPinPolarity:0
  ulDockingPinCFGInfo:0
  ulCPUCapInfo: 2
  usNumberOfCyclesInPeriod:0
  usMaxNBVoltage:0
  usMinNBVoltage:0
  usBootUpNBVoltage:0
  ulHTLinkFreq:20000
  usMinHTLinkWidth:8
  usMaxHTLinkWidth:8
  usUMASyncStartDelay:100
  usUMADataReturnTime:300
  usLinkStatusZeroTime:600
  ulHighVoltageHTLinkFreq:20000
  ulLowVoltageHTLinkFreq:20000
  usMaxUpStreamHTLinkWidth:8
  usMaxDownStreamHTLinkWidth:8
  usMinUpStreamHTLinkWidth:8
  usMinDownStreamHTLinkWidth:8

Change-Id: I17c2a13ab52a0f78588f812d4f42f45f9a7b7524
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/456
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

adding support for the Asus K8V-X

This pulls it all together and adds the real board-specific code.

Confirmed to be working:
- IDE
- SATA
- floppy
- USB1.1
- USB2.0
- PS/2 keyboard
- PS/2 mouse
- serial
- parport
- sound
- ethernet
- PCI slots
- AGP
- powernow
- fan speed monitoring
- flashrom write

Change-Id: Ifb97714c2f009d688be0ca3c38ddc01599ffd799
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/390
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Tested-by: build bot (Jenkins)