};
PCIe_DDI_DESCRIPTOR DdiList [] = {
- // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
+ /* Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) DP1 HDMI */
{
- 0, //Descriptor flags
- PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
- //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
- {ConnectorTypeDP, Aux1, Hdp1}
+ 0,
+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2)
},
- // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
+ /* Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) DP0 VGA */
{
- DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
- PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
- //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
- {ConnectorTypeDP, Aux2, Hdp2}
+ DESCRIPTOR_TERMINATE_LIST,
+ PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
+ PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux1, Hdp1)
}
};
//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE
//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE
//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0
-#define BLDCFG_CFG_GNB_HD_AUDIO FALSE//TRUE
+#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
//#define BLDCFG_CFG_ABM_SUPPORT FALSE
//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0
//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0