Support AMD SB700 and SP5100 chipsets.
Change-Id: I0955abf7f48a79483f624b46a61b22711315f888
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/560
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
+subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += sb900
subdirs-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890
--- /dev/null
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include "Platform.h"
+
+/*++
+
+Routine Description:
+
+ Locate ACPI table
+
+Arguments:
+
+ Signature - table signature
+
+Returns:
+
+ pointer to ACPI table
+
+--*/
+void* ACPI_LocateTable(
+ UINT32 Signature
+)
+{
+ UINT32 i;
+ UINT32* RsdPtr = (UINT32*)0xe0000;
+ UINT32* Rsdt = NULL;
+ DESCRIPTION_HEADER* CurrentTable;
+ do{
+// if (*RsdPtr == ' DSR' && *(RsdPtr+1) == ' RTP'){
+ if ((*RsdPtr == Int32FromChar ('R', 'S', 'D', ' ')) && (*(RsdPtr+1) == Int32FromChar ('R', 'T', 'P', ' '))){
+ Rsdt = (UINT32*)((RSDP*)RsdPtr)->RsdtAddress;
+ break;
+ }
+ RsdPtr+=4;
+ }while (RsdPtr <= (UINT32*)0xffff0);
+ if(Rsdt != NULL && ACPI_GetTableChecksum(Rsdt)==0){
+ for (i = 0;i < (((DESCRIPTION_HEADER*)Rsdt)->Length - sizeof(DESCRIPTION_HEADER))/4;i++){
+ CurrentTable = (DESCRIPTION_HEADER*)*(UINT32*)((UINT8*)Rsdt + sizeof(DESCRIPTION_HEADER) + i*4);
+ if (CurrentTable->Signature == Signature) return CurrentTable;
+ }
+ }
+ return NULL;
+}
+
+/*++
+
+Routine Description:
+
+ Update table checksum
+
+Arguments:
+
+ TablePtr - table pointer
+
+Returns:
+
+ none
+
+--*/
+void ACPI_SetTableChecksum(
+ void* TablePtr
+)
+{
+ UINT8 Checksum = 0;
+ ((DESCRIPTION_HEADER*)TablePtr)->Checksum = 0;
+ Checksum = ACPI_GetTableChecksum(TablePtr);
+ ((DESCRIPTION_HEADER*)TablePtr)->Checksum = 0x100 - Checksum;
+}
+
+/*++
+
+Routine Description:
+
+ Get table checksum
+
+Arguments:
+
+ TablePtr - table pointer
+
+Returns:
+
+ none
+
+--*/
+UINT8 ACPI_GetTableChecksum(
+ void* TablePtr
+)
+{
+ return GetByteSum(TablePtr,((DESCRIPTION_HEADER*)TablePtr)->Length);
+}
+
--- /dev/null
+/*;********************************************************************************
+;
+; Copyright (C) 2012 Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; * Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; * Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; * Neither the name of Advanced Micro Devices, Inc. nor the names of
+; its contributors may be used to endorse or promote products derived
+; from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*********************************************************************************/
+
+#ifndef _AMD_ACPILIB_H_
+#define _AMD_ACPILIB_H_
+
+typedef struct _RSDP{
+ UINT64 Signature;
+ UINT8 Checksum;
+ UINT8 OEMID[6];
+ UINT8 Revision;
+ UINT32 RsdtAddress;
+ UINT32 Length;
+ UINT64 XsdtAddress;
+ UINT8 ExtendedChecksum;
+ UINT8 Reserved[3];
+}RSDP;
+
+typedef struct _DESCRIPTION_HEADER{
+ UINT32 Signature;
+ UINT32 Length;
+ UINT8 Revision;
+ UINT8 Checksum;
+ UINT8 OEMID[6];
+ UINT8 OEMTableID[8];
+ UINT32 OEMRevision;
+ UINT32 CreatorID;
+ UINT32 CreatorRevision;
+}DESCRIPTION_HEADER;
+
+void* ACPI_LocateTable(UINT32 Signature);
+void ACPI_SetTableChecksum(void* TablePtr);
+UINT8 ACPI_GetTableChecksum(void* TablePtr);
+
+#endif //ifndef _AMD_ACPILIB_H_
--- /dev/null
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+
+#include "Platform.h"
+
+VOID
+ReadIO (
+ IN UINT16 Address,
+ IN UINT8 OpFlag,
+ IN VOID* Value
+ )
+{
+ OpFlag = OpFlag & 0x7f;
+ switch ( OpFlag ) {
+ case AccWidthUint8:
+ *(UINT8*)Value = ReadIo8 (Address);
+ break;
+ case AccWidthUint16:
+ *(UINT16*)Value = ReadIo16 (Address);
+ break;
+ case AccWidthUint32:
+ *(UINT32*)Value = ReadIo32 (Address);
+ break;
+ default:
+ break;
+ }
+}
+
+VOID
+WriteIO (
+ IN UINT16 Address,
+ IN UINT8 OpFlag,
+ IN VOID* Value
+ )
+{
+ OpFlag = OpFlag & 0x7f;
+ switch ( OpFlag ) {
+ case AccWidthUint8:
+ WriteIo8 (Address, *(UINT8*)Value);
+ break;
+ case AccWidthUint16:
+ WriteIo16 (Address, *(UINT16*)Value);
+ break;
+ case AccWidthUint32:
+ WriteIo32 (Address, *(UINT32*)Value);
+ break;
+ default:
+ break;
+ }
+}
+
+VOID
+RWIO (
+ IN UINT16 Address,
+ IN UINT8 OpFlag,
+ IN UINT32 Mask,
+ IN UINT32 Data
+ )
+{
+ UINT32 Result;
+ ReadIO (Address, OpFlag, &Result);
+ Result = (Result & Mask) | Data;
+ WriteIO (Address, OpFlag, &Result);
+}
+
+
+VOID
+ReadPCI (
+ IN UINT32 Address,
+ IN UINT8 OpFlag,
+ IN VOID* Value
+ )
+{
+ OpFlag = OpFlag & 0x7f;
+
+ if ( (UINT16)Address < 0xff ) {
+ //Normal Config Access
+ UINT32 AddrCf8;
+ AddrCf8 = (1 << 31) + ((Address >> 8) & 0x0FFFF00) + (Address & 0xFC);
+ WriteIO (0xCf8, AccWidthUint32, &AddrCf8);
+ ReadIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value);
+ }
+}
+
+VOID
+WritePCI (
+ IN UINT32 Address,
+ IN UINT8 OpFlag,
+ IN VOID* Value
+ )
+{
+ OpFlag = OpFlag & 0x7f;
+ if ( (UINT16)Address < 0xff ) {
+ //Normal Config Access
+ UINT32 AddrCf8;
+ AddrCf8 = (1 << 31) + ((Address >> 8)&0x0FFFF00) + (Address & 0xFC);
+ WriteIO (0xCf8, AccWidthUint32, &AddrCf8);
+ WriteIO ((UINT16) (0xCfC + (Address & 0x3)), OpFlag, Value);
+ }
+}
+
+VOID
+RWPCI (
+ IN UINT32 Address,
+ IN UINT8 OpFlag,
+ IN UINT32 Mask,
+ IN UINT32 Data
+ )
+{
+ UINT32 Result;
+ Result = 0;
+ OpFlag = OpFlag & 0x7f;
+ ReadPCI (Address, OpFlag, &Result);
+ Result = (Result & Mask) | Data;
+ WritePCI (Address, OpFlag, &Result);
+}
+
+void
+ReadIndexPCI32 (
+UINT32 PciAddress,
+UINT32 IndexAddress,
+void* Value
+)
+{
+ WritePCI(PciAddress,AccWidthUint32,&IndexAddress);
+ ReadPCI(PciAddress+4,AccWidthUint32,Value);
+}
+
+void
+WriteIndexPCI32 (
+UINT32 PciAddress,
+UINT32 IndexAddress,
+UINT8 OpFlag,
+void* Value
+)
+{
+
+ WritePCI(PciAddress,AccWidthUint32 | (OpFlag & 0x80),&IndexAddress);
+ WritePCI(PciAddress+4,AccWidthUint32 | (OpFlag & 0x80) ,Value);
+}
+
+void
+RWIndexPCI32 (
+UINT32 PciAddress,
+UINT32 IndexAddress,
+UINT8 OpFlag,
+UINT32 Mask,
+UINT32 Data
+)
+{
+ UINT32 Result;
+ ReadIndexPCI32(PciAddress,IndexAddress,&Result);
+ Result = (Result & Mask)| Data;
+ WriteIndexPCI32(PciAddress,IndexAddress,(OpFlag & 0x80),&Result);
+
+}
+
+void
+ReadMEM (
+UINT32 Address,
+UINT8 OpFlag,
+void* Value
+)
+{
+ OpFlag = OpFlag & 0x7f;
+ switch (OpFlag){
+ case AccWidthUint8 : *((UINT8*)Value)=*((UINT8*)Address);break;
+ case AccWidthUint16: *((UINT16*)Value)=*((UINT16*)Address);break;
+ case AccWidthUint32: *((UINT32*)Value)=*((UINT32*)Address);break;
+ }
+}
+
+void
+WriteMEM (
+UINT32 Address,
+UINT8 OpFlag,
+void* Value
+)
+{
+ OpFlag = OpFlag & 0x7f;
+ switch (OpFlag){
+ case AccWidthUint8 : *((UINT8*)Address)=*((UINT8*)Value);break;
+ case AccWidthUint16: *((UINT16*)Address)=*((UINT16*)Value);break;
+ case AccWidthUint32: *((UINT32*)Address)=*((UINT32*)Value);break;
+ }
+}
+
+void
+RWMEM (
+UINT32 Address,
+UINT8 OpFlag,
+UINT32 Mask,
+UINT32 Data
+)
+{
+ UINT32 Result;
+ ReadMEM(Address,OpFlag,&Result);
+ Result = (Result & Mask)| Data;
+ WriteMEM(Address,OpFlag,&Result);
+}
+
+
+void
+RWMSR(
+UINT32 Address,
+UINT64 Mask,
+UINT64 Value
+)
+{
+ MsrWrite(Address,(MsrRead(Address)& Mask)|Value);
+}
+
+UINT32
+IsFamily10()
+{
+ CPUID_DATA Cpuid;
+ CpuidRead(0x1,(CPUID_DATA *)&Cpuid);
+
+ return Cpuid.REG_EAX & 0xff00000;
+}
+
+
+UINT8 GetNumberOfCpuCores(void)
+{
+ UINT8 Result=1;
+ Result=ReadNumberOfCpuCores();
+ return Result;
+}
+
+
+void
+Stall(
+UINT32 uSec
+)
+{
+ UINT16 timerAddr;
+ UINT32 startTime, elapsedTime;
+ ReadPMIO(SB_PMIO_REG24, AccWidthUint16, &timerAddr);
+
+ if (timerAddr ==0){
+ uSec = uSec/2;
+ while (uSec!=0){
+ ReadIO(0x80,AccWidthUint8,(UINT8 *)(&startTime));
+ uSec--;
+ }
+ }
+ else{
+ ReadIO(timerAddr, AccWidthUint32,&startTime);
+ while (1){
+ ReadIO(timerAddr, AccWidthUint32,&elapsedTime);
+ if (elapsedTime < startTime)
+ elapsedTime = elapsedTime+0xFFFFFFFF-startTime;
+ else
+ elapsedTime = elapsedTime-startTime;
+ if ((elapsedTime*28/100)>uSec)
+ break;
+ }
+ }
+}
+
+
+void
+Reset(
+)
+{
+ RWIO(0xcf9,AccWidthUint8,0x0,0x06);
+}
+
+
+CIM_STATUS
+RWSMBUSBlock(
+UINT8 Controller,
+UINT8 Address,
+UINT8 Offset,
+UINT8 BufferSize,
+UINT8* BufferPrt
+)
+{
+ UINT16 SmbusPort;
+ UINT8 i;
+ UINT8 Status;
+ ReadPCI(PCI_ADDRESS(0,0x14,0,Controller?0x58:0x10),AccWidthUint16,&SmbusPort);
+ SmbusPort &= 0xfffe;
+ RWIO(SmbusPort + 0,AccWidthUint8,0x0,0xff);
+ RWIO(SmbusPort + 4,AccWidthUint8,0x0,Address);
+ RWIO(SmbusPort + 3,AccWidthUint8,0x0,Offset);
+ RWIO(SmbusPort + 2,AccWidthUint8,0x0,0x14);
+ RWIO(SmbusPort + 5,AccWidthUint8,0x0,BufferSize);
+ if(!(Address & 0x1)){
+ for (i = 0 ;i < BufferSize;i++){
+ WriteIO(SmbusPort + 7,AccWidthUint8,&BufferPrt[i]);
+ }
+ }
+ RWIO(SmbusPort + 2,AccWidthUint8,0x0,0x54);
+ do{
+ ReadIO(SmbusPort + 0,AccWidthUint8,&Status);
+ if (Status & 0x1C) return CIM_ERROR;
+ if (Status & 0x02) break;
+ }while(!(Status & 0x1));
+
+ do{
+ ReadIO(SmbusPort + 0,AccWidthUint8,&Status);
+ }while(Status & 0x1);
+
+ if(Address & 0x1){
+ for (i = 0 ;i < BufferSize;i++){
+ ReadIO(SmbusPort + 7,AccWidthUint8,&BufferPrt[i]);
+ }
+ }
+ return CIM_SUCCESS;
+}
+
+
+
+void outPort80(UINT32 pcode)
+{
+ WriteIO(0x80, AccWidthUint8, &pcode);
+ return;
+}
+
+
+UINT8
+GetByteSum(
+ void* pData,
+ UINT32 Length
+)
+{
+ UINT32 i;
+ UINT8 Checksum = 0;
+ for (i = 0;i < Length;i++){
+ Checksum += *((UINT8*)pData+i);
+ }
+ return Checksum;
+}
+
+
+UINT32
+readAlink(
+ UINT32 Index
+){
+ UINT32 Data;
+ WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32, &Index);
+ ReadIO(ALINK_ACCESS_DATA, AccWidthUint32, &Data);
+ //Clear Index
+ Index=0;
+ WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32, &Index);
+ return Data;
+}
+
+
+void
+writeAlink(
+ UINT32 Index,
+ UINT32 Data
+){
+ WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32, &Index);
+ WriteIO(ALINK_ACCESS_DATA, AccWidthUint32, &Data);
+ //Clear Index
+ Index=0;
+ WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32, &Index);
+
+}
+
+
+/**
+ *
+ * IsServer - Determine if southbridge type is SP5100 (server) or SB7x0 (non-server)
+ *
+ * A SP5100 is determined when both following two items are true:
+ * 1) Revision >= A14;
+ * 2) A server north bridge chipset is detected;
+ *
+ * A list of server north bridge chipset:
+ *
+ * Family DeviceID
+ * ----------------------
+ * SR5690 0x5A10
+ * SR5670 0x5A12
+ * SR5650 0x5A13
+ *
+ */
+UINT8
+IsServer (void){
+ UINT16 DevID;
+
+ if (getRevisionID () < SB700_A14) {
+ return 0;
+ }
+ ReadPCI ((NB_BDF << 16) + 2, AccWidthUint16, &DevID);
+ return ((DevID == 0x5a10) || (DevID == 0x5a12) || (DevID == 0x5a13))? 1: 0;
+}
+
+/**
+ *
+ * IsLS2Mode - Determine if LS2 mode is enabled or not in northbridge.
+ *
+ */
+UINT8
+IsLs2Mode (void)
+{
+ UINT32 HT3LinkTraining0;
+
+ ReadPCI ((NB_BDF << 16) + 0xAC, AccWidthUint32, &HT3LinkTraining0);
+ return ( HT3LinkTraining0 & 0x100 )? 1: 0;
+}
--- /dev/null
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include "Platform.h"
+
+
+void
+ReadPMIO (
+UINT8 Address,
+UINT8 OpFlag,
+void* Value
+)
+{
+ UINT8 i;
+
+ OpFlag = OpFlag & 0x7f;
+ if (OpFlag == 0x02) OpFlag = 0x03;
+ for (i=0;i<=OpFlag;i++){
+ WriteIO(0xCD6, AccWidthUint8, &Address); // SB_IOMAP_REGCD6
+ Address++;
+ ReadIO(0xCD7, AccWidthUint8, (UINT8 *)Value+i); // SB_IOMAP_REGCD7
+ }
+}
+
+
+void
+WritePMIO (
+UINT8 Address,
+UINT8 OpFlag,
+void* Value
+)
+{
+ UINT8 i;
+
+ OpFlag = OpFlag & 0x7f;
+ if (OpFlag == 0x02) OpFlag = 0x03;
+ for (i=0;i<=OpFlag;i++){
+ WriteIO(0xCD6, AccWidthUint8, &Address); // SB_IOMAP_REGCD6
+ Address++;
+ WriteIO(0xCD7, AccWidthUint8, (UINT8 *)Value+i); // SB_IOMAP_REGCD7
+ }
+}
+
+
+void
+RWPMIO (
+UINT8 Address,
+UINT8 OpFlag,
+UINT32 AndMask,
+UINT32 OrMask
+)
+{
+ UINT32 Result;
+
+ OpFlag = OpFlag & 0x7f;
+ ReadPMIO(Address,OpFlag,&Result);
+ Result = (Result & AndMask)| OrMask;
+ WritePMIO(Address,OpFlag,&Result);
+}
+
+
+void
+ReadPMIO2 (
+UINT8 Address,
+UINT8 OpFlag,
+void* Value
+)
+{
+ UINT8 i;
+
+ OpFlag = OpFlag & 0x7f;
+ if (OpFlag == 0x02) OpFlag = 0x03;
+ for (i=0;i<=OpFlag;i++){
+ WriteIO(0xCD0, AccWidthUint8, &Address); // SB_IOMAP_REGCD0
+ Address++;
+ ReadIO(0xCD1, AccWidthUint8, (UINT8 *)Value+i); // SB_IOMAP_REGCD1
+ }
+}
+
+
+void
+WritePMIO2 (
+UINT8 Address,
+UINT8 OpFlag,
+void* Value
+)
+{
+ UINT8 i;
+
+ OpFlag = OpFlag & 0x7f;
+ if (OpFlag == 0x02) OpFlag = 0x03;
+ for (i=0;i<=OpFlag;i++){
+ WriteIO(0xCD0, AccWidthUint8, &Address); // SB_IOMAP_REGCD0
+ Address++;
+ WriteIO(0xCD1, AccWidthUint8, (UINT8 *)Value+i); // SB_IOMAP_REGCD1
+ }
+}
+
+
+void
+RWPMIO2 (
+UINT8 Address,
+UINT8 OpFlag,
+UINT32 AndMask,
+UINT32 OrMask
+)
+{
+ UINT32 Result;
+
+ OpFlag = OpFlag & 0x7f;
+ ReadPMIO2(Address,OpFlag,&Result);
+ Result = (Result & AndMask)| OrMask;
+ WritePMIO2(Address,OpFlag,&Result);
+}
+
+
+void
+EnterEcConfig()
+{
+ UINT16 dwEcIndexPort;
+
+ ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
+ dwEcIndexPort &= ~(UINT16)(BIT0);
+ RWIO(dwEcIndexPort, AccWidthUint8, 0x00, 0x5A);
+}
+
+void
+ExitEcConfig()
+{
+ UINT16 dwEcIndexPort;
+
+ ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
+ dwEcIndexPort &= ~(UINT16)(BIT0);
+ RWIO(dwEcIndexPort, AccWidthUint8, 0x00, 0xA5);
+}
+
+
+void
+ReadEC8 (
+UINT8 Address,
+UINT8* Value
+)
+{
+ UINT16 dwEcIndexPort;
+
+ ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
+ dwEcIndexPort &= ~(UINT16)(BIT0);
+ WriteIO(dwEcIndexPort, AccWidthUint8, &Address); // SB_IOMAP_REGCD6
+ ReadIO(dwEcIndexPort+1, AccWidthUint8, Value); // SB_IOMAP_REGCD7
+}
+
+
+void
+WriteEC8 (
+UINT8 Address,
+UINT8* Value
+)
+{
+ UINT16 dwEcIndexPort;
+
+ ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwEcIndexPort);
+ dwEcIndexPort &= ~(UINT16)(BIT0);
+ WriteIO(dwEcIndexPort, AccWidthUint8, &Address); // SB_IOMAP_REGCD6
+ WriteIO(dwEcIndexPort+1, AccWidthUint8, Value); // SB_IOMAP_REGCD7
+}
+
+
+void
+RWEC8 (
+UINT8 Address,
+UINT8 AndMask,
+UINT8 OrMask
+)
+{
+ UINT8 Result;
+ ReadEC8(Address,&Result);
+ Result = (Result & AndMask)| OrMask;
+ WriteEC8(Address, &Result);
+}
+
+
+void
+programPciByteTable (
+REG8MASK* pPciByteTable,
+UINT16 dwTableSize
+)
+{
+ UINT8 i, dbBusNo, dbDevFnNo;
+ UINT32 ddBDFR;
+
+ dbBusNo = pPciByteTable->bRegIndex;
+ dbDevFnNo = pPciByteTable->bANDMask;
+ pPciByteTable++;
+ for (i = 1; i < dwTableSize; i++){
+ if ( (pPciByteTable->bRegIndex==0xFF) && (pPciByteTable->bANDMask==0xFF) && (pPciByteTable->bORMask==0xFF) ){
+ pPciByteTable++;
+ dbBusNo = pPciByteTable->bRegIndex;
+ dbDevFnNo = pPciByteTable->bANDMask;
+ }
+ else{
+ ddBDFR = (dbBusNo << 24) + (dbDevFnNo << 16) + (pPciByteTable->bRegIndex) ;
+ TRACE((DMSG_SB_TRACE, "PFA=%X AND=%X, OR=%X\n", ddBDFR, pPciByteTable->bANDMask, pPciByteTable->bORMask));
+ RWPCI(ddBDFR, AccWidthUint8 | S3_SAVE, pPciByteTable->bANDMask, pPciByteTable->bORMask);
+ pPciByteTable++;
+ }
+ }
+}
+
+
+void
+programPmioByteTable (
+REG8MASK* pPmioByteTable,
+UINT16 dwTableSize
+)
+{
+ UINT8 i;
+ for (i = 0; i < dwTableSize; i++){
+ TRACE((DMSG_SB_TRACE, "PMIO Reg = %X AndMask = %X OrMask = %X\n",pPmioByteTable->bRegIndex,pPmioByteTable->bANDMask, pPmioByteTable->bORMask));
+ RWPMIO(pPmioByteTable->bRegIndex, AccWidthUint8 , pPmioByteTable->bANDMask, pPmioByteTable->bORMask);
+ pPmioByteTable++;
+ }
+}
+
+
+UINT8
+getClockMode (
+void
+)
+{
+ UINT8 dbTemp=0;
+
+ RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT7);
+ ReadPMIO(SB_PMIO_REGB0, AccWidthUint8, &dbTemp);
+ return(dbTemp&BIT4);
+}
+
+
+UINT16
+readStrapStatus (
+void
+)
+{
+ UINT16 dwTemp=0;
+
+ RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT7);
+ ReadPMIO(SB_PMIO_REGB0, AccWidthUint16, &dwTemp);
+ return(dwTemp);
+}
--- /dev/null
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+
+#include "Platform.h"
+
+void configureAzaliaPinCmd (AMDSBCFG* pConfig, UINT32 ddBAR0, UINT8 dbChannelNum);
+void configureAzaliaSetConfigD4Dword(CODECENTRY* tempAzaliaCodecEntryPtr, UINT32 ddChannelNum, UINT32 ddBAR0);
+
+//Pin Config for ALC880, ALC882 and ALC883:
+CODECENTRY AzaliaCodecAlc882Table[] = {
+ {0x14, 0x01014010},
+ {0x15, 0x01011012},
+ {0x16, 0x01016011},
+ {0x17, 0x01012014},
+ {0x18, 0x01A19030},
+ {0x19, 0x411111F0},
+ {0x1a, 0x01813080},
+ {0x1b, 0x411111F0},
+ {0x1C, 0x411111F0},
+ {0x1d, 0x411111F0},
+ {0x1e, 0x01441150},
+ {0x1f, 0x01C46160},
+ {0xff, 0xffffffff}
+};
+
+
+//Pin Config for ALC262
+CODECENTRY AzaliaCodecAlc262Table[] = {
+ {0x14, 0x01014010},
+ {0x15, 0x411111F0},
+ {0x16, 0x411111F0},
+// {0x17, 0x01012014},
+ {0x18, 0x01A19830},
+ {0x19, 0x02A19C40},
+ {0x1a, 0x01813031},
+ {0x1b, 0x02014C20},
+ {0x1c, 0x411111F0},
+ {0x1d, 0x411111F0},
+ {0x1e, 0x0144111E},
+ {0x1f, 0x01C46150},
+ {0xff, 0xffffffff}
+};
+
+//Pin Config for ALC0861:
+CODECENTRY AzaliaCodecAlc861Table[] = {
+ {0x01, 0x8086C601},
+ {0x0B, 0x01014110},
+ {0x0C, 0x01813140},
+ {0x0D, 0x01A19941},
+ {0x0E, 0x411111F0},
+ {0x0F, 0x02214420},
+ {0x10, 0x02A1994E},
+ {0x11, 0x99330142},
+ {0x12, 0x01451130},
+ {0x1F, 0x411111F0},
+ {0x20, 0x411111F0},
+ {0x23, 0x411111F0},
+ {0xff, 0xffffffff}
+};
+
+//Pin Config for ADI1984:
+CODECENTRY AzaliaCodecAd1984Table[] = {
+ {0x11, 0x0221401F},
+ {0x12, 0x90170110},
+ {0x13, 0x511301F0},
+ {0x14, 0x02A15020},
+ {0x15, 0x50A301F0},
+ {0x16, 0x593301F0},
+ {0x17, 0x55A601F0},
+ {0x18, 0x55A601F0},
+ {0x1A, 0x91F311F0},
+ {0x1B, 0x014511A0},
+ {0x1C, 0x599301F0},
+ {0xff, 0xffffffff}
+};
+
+
+CODECENTRY FrontPanelAzaliaCodecTableList[] = {
+ {0x19, 0x02A19040},
+ {0x1b, 0x02214020},
+ {0xff, 0xffffffff}
+};
+
+
+CODECTBLLIST azaliaCodecTableList[] = {
+ {0x010ec0880, &AzaliaCodecAlc882Table[0]},
+ {0x010ec0882, &AzaliaCodecAlc882Table[0]},
+ {0x010ec0883, &AzaliaCodecAlc882Table[0]},
+ {0x010ec0885, &AzaliaCodecAlc882Table[0]},
+ {0x010ec0262, &AzaliaCodecAlc262Table[0]},
+ {0x010ec0861, &AzaliaCodecAlc861Table[0]},
+ {0x011d41984, &AzaliaCodecAd1984Table[0]},
+ {(UINT32)0x0FFFFFFFF, (CODECENTRY*)0xFFFFFFFF}
+};
+
+
+/*-------------------------------------------------------------------------------
+; Procedure: azaliaInitAfterPciEnum
+;
+; Description: This routine detects Azalia and, if present, initializes Azalia
+; This routine is called from atiSbAfterPciInit
+;
+;
+; Exit: None
+;
+; Modified: None
+;
+;-----------------------------------------------------------------------------
+*/
+void azaliaInitAfterPciEnum (AMDSBCFG* pConfig){
+ UINT8 i, dbEnableAzalia=0, dbPinRouting, dbChannelNum=0, dbTempVariable = 0;
+ UINT16 dwTempVariable = 0;
+ UINT32 ddBAR0, ddTempVariable = 0;
+
+ if (pConfig->AzaliaController == 1) return;
+
+ if (pConfig->AzaliaController != 1){
+ RWPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT1, BIT1);
+ ReadPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0);
+
+ if (ddBAR0 != 0){ //Keep the flag as disabled if BAR is 0 or all "F"s.
+ if (ddBAR0 != 0xFFFFFFFF){
+ ddBAR0 &= ~(0x03FFF);
+ dbEnableAzalia = 1;
+ TRACE((DMSG_SB_TRACE, "CIMxSB - Enabling Azalia controller (BAR setup is ok) \n"));
+ }
+ }
+ }
+
+ if (dbEnableAzalia){ //if Azalia is enabled
+ //Get SDIN Configuration
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGF8, AccWidthUint32 | S3_SAVE, 0, ddTempVariable);
+ ddTempVariable |= (pConfig->AzaliaSdin3 << 6);
+ ddTempVariable |= (pConfig->AzaliaSdin2 << 4);
+ ddTempVariable |= (pConfig->AzaliaSdin1 << 2);
+ ddTempVariable |= pConfig->AzaliaSdin0;
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGFC, AccWidthUint8 | S3_SAVE, 0, (ddTempVariable & 0xFF));
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+3, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT2+BIT1+BIT0), 0);
+
+ i=11;
+ do{
+ ReadMEM( ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
+ dbTempVariable |= BIT0;
+ WriteMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
+ Stall(1000);
+ ReadMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
+ i--;
+ } while ( (!(dbTempVariable & BIT0)) && (i > 0) );
+
+ if (i==0){
+ TRACE((DMSG_SB_TRACE, "CIMxSB - Problem in resetting Azalia controller\n"));
+ return;
+ }
+
+ Stall(1000);
+ ReadMEM( ddBAR0+SB_AZ_BAR_REG0E, AccWidthUint16, &dwTempVariable);
+ if (dwTempVariable & 0x0F){
+ TRACE((DMSG_SB_TRACE, "CIMxSB - Atleast One Azalia CODEC found \n"));
+ //atleast one azalia codec found
+ ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGFC, AccWidthUint8, &dbPinRouting);
+ do{
+ if ( ( !(dbPinRouting & BIT0) ) && (dbPinRouting & BIT1) )
+ configureAzaliaPinCmd(pConfig, ddBAR0, dbChannelNum);
+ dbPinRouting >>= 2;
+ dbChannelNum++;
+ } while (dbChannelNum != 4);
+ }
+ else{
+ TRACE((DMSG_SB_TRACE, "CIMxSB - Azalia CODEC NOT found \n"));
+ //No Azalia codec found
+ if (pConfig->AzaliaController != 2)
+ dbEnableAzalia = 0; //set flag to disable Azalia
+ }
+ }
+
+ if (dbEnableAzalia){
+ //redo clear reset
+ do{
+ dwTempVariable = 0;
+ WriteMEM( ddBAR0+SB_AZ_BAR_REG0C, AccWidthUint16 | S3_SAVE, &dwTempVariable);
+ ReadMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
+ dbTempVariable &= ~(UINT8)(BIT0);
+ WriteMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
+ ReadMEM(ddBAR0+SB_AZ_BAR_REG08, AccWidthUint8 | S3_SAVE, &dbTempVariable);
+ } while (dbTempVariable & BIT0);
+
+ if (pConfig->AzaliaSnoop == 1)
+ RWPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG42, AccWidthUint8 | S3_SAVE, 0xFF, BIT1+BIT0);
+ }
+ else{
+ //disable Azalia controller
+ RWPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint16 | S3_SAVE, 0, 0);
+ RWPMIO(SB_PMIO_REG59, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, 0);
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGFC, AccWidthUint8 | S3_SAVE, 0, 0x55);
+ }
+}
+
+
+void configureAzaliaPinCmd (AMDSBCFG* pConfig, UINT32 ddBAR0, UINT8 dbChannelNum){
+ UINT32 ddTempVariable, ddChannelNum;
+ CODECTBLLIST* ptempAzaliaOemCodecTablePtr;
+ CODECENTRY* tempAzaliaCodecEntryPtr;
+
+ if ((pConfig->AzaliaPinCfg) != 1)
+ return;
+
+ ddChannelNum = dbChannelNum << 28;
+ ddTempVariable = 0xF0000;
+ ddTempVariable |= ddChannelNum;
+ WriteMEM(ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddTempVariable);
+ Stall(60);
+ ReadMEM(ddBAR0 + SB_AZ_BAR_REG64, AccWidthUint32 | S3_SAVE, &ddTempVariable);
+
+ if ( ((pConfig->pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) 0xFFFFFFFF)) )
+ ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) FIXUP_PTR(&azaliaCodecTableList[0]);
+ else
+ ptempAzaliaOemCodecTablePtr = (CODECTBLLIST*) pConfig->pAzaliaOemCodecTablePtr;
+
+ TRACE((DMSG_SB_TRACE, "CIMxSB - Azalia CODEC table pointer is %x \n", (UINT32)ptempAzaliaOemCodecTablePtr));
+
+ while ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF){
+ if ( ptempAzaliaOemCodecTablePtr->CodecID == ddTempVariable)
+ break;
+ else
+ ++ptempAzaliaOemCodecTablePtr;
+ }
+
+ if ( ptempAzaliaOemCodecTablePtr->CodecID != 0xFFFFFFFF){
+ TRACE((DMSG_SB_TRACE, "CIMxSB - Matching CODEC ID found \n"));
+ tempAzaliaCodecEntryPtr = (CODECENTRY*) ptempAzaliaOemCodecTablePtr->CodecTablePtr;
+ TRACE((DMSG_SB_TRACE, "CIMxSB - Matching Azalia CODEC table pointer is %x \n", (UINT32)tempAzaliaCodecEntryPtr));
+
+ if ( ((pConfig->pAzaliaOemCodecTablePtr) == NULL) || ((pConfig->pAzaliaOemCodecTablePtr) == ((CODECTBLLIST*) 0xFFFFFFFF)) )
+ tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR(tempAzaliaCodecEntryPtr);
+
+ configureAzaliaSetConfigD4Dword(tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0);
+ if (pConfig->AzaliaFrontPanel != 1){
+ if ( (pConfig->AzaliaFrontPanel == 2) || (pConfig->FrontPanelDetected == 1) ){
+ if ( ((pConfig->pAzaliaOemFpCodecTableptr) == NULL) || ((pConfig->pAzaliaOemFpCodecTableptr) == 0xFFFFFFFF))
+ tempAzaliaCodecEntryPtr = (CODECENTRY*) FIXUP_PTR(&FrontPanelAzaliaCodecTableList[0]);
+ else
+ tempAzaliaCodecEntryPtr = (CODECENTRY*) pConfig->pAzaliaOemFpCodecTableptr;
+ configureAzaliaSetConfigD4Dword(tempAzaliaCodecEntryPtr, ddChannelNum, ddBAR0);
+ }
+ }
+ }
+}
+
+
+void configureAzaliaSetConfigD4Dword(CODECENTRY* tempAzaliaCodecEntryPtr, UINT32 ddChannelNum, UINT32 ddBAR0){
+ UINT8 dbtemp1,dbtemp2, i;
+ UINT32 ddtemp=0,ddtemp2=0;
+
+ while ((tempAzaliaCodecEntryPtr->Nid) != 0xFF){
+ dbtemp1=0x20;
+ if ((tempAzaliaCodecEntryPtr->Nid) == 0x1)
+ dbtemp1=0x24;
+ ddtemp = tempAzaliaCodecEntryPtr->Nid;
+ ddtemp &= 0xff;
+ ddtemp <<= 20;
+ ddtemp |= ddChannelNum;
+ ddtemp |= (0x700 << 8);
+ for(i=4; i>0; i--){
+ do{
+ ReadMEM(ddBAR0 + SB_AZ_BAR_REG68, AccWidthUint32, &ddtemp2);
+ } while (ddtemp2 & BIT0);
+ dbtemp2 = ( (tempAzaliaCodecEntryPtr->Byte40) >> ((4-i) * 8 ) ) & 0xff;
+ ddtemp = (ddtemp & 0xFFFF0000)+ ((dbtemp1 - i) << 8) + dbtemp2;
+ WriteMEM(ddBAR0 + SB_AZ_BAR_REG60, AccWidthUint32 | S3_SAVE, &ddtemp);
+ Stall(60);
+ }
+ ++tempAzaliaCodecEntryPtr;
+ }
+}
+
--- /dev/null
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include "Platform.h"
+
+#define COM_BASE_ADDRESS 0x3f8
+#define DIVISOR 115200
+#define LF 0x0a
+#define CR 0x0d
+
+
+#ifdef CIM_DEBUG
+ #ifndef CIM_DEBUG_LEVEL
+ #define CIM_DEBUG_LEVEL 0xf
+#endif
+
+void
+TraceCode( UINT32 Level, UINT32 Code){
+
+ if (!(Level & CIM_DEBUG_LEVEL)){
+ return;
+ }
+#if CIM_DEBUG & 1
+ if (Code != 0xFF){
+ WriteIO(0x80,AccWidthUint8,&Code);
+ }
+#endif
+
+}
+
+
+void
+TraceDebug( UINT32 Level, CHAR8 *Format, ...){
+ CHAR8 temp[16];
+ va_list ArgList;
+
+ if (!(Level & CIM_DEBUG_LEVEL)){
+ return;
+ }
+
+#if CIM_DEBUG & 2
+ ArgList = va_start(ArgList,Format);
+ Format= (CHAR8*) FIXUP_PTR(Format);
+ while (1){
+ if (*Format == 0) break;
+ if (*Format == '%'){
+ int Radix = 0;
+ if(*(Format+1)=='s'||*(Format+1)=='S'){
+ SendStringPort((CHAR8*) FIXUP_PTR(va_arg(ArgList,CHAR8*)));
+ Format+=2;
+ continue;
+ }
+
+ if(*(Format+1)=='d'||*(Format+1)=='D'){
+ Radix = 10;
+ }
+ if(*(Format+1)=='x'||*(Format+1)=='X'){
+ Radix = 16;
+ }
+ if (Radix){
+ ItoA(va_arg(ArgList,int),Radix,temp);
+ SendStringPort(temp);
+ Format+=2;
+ continue;
+ }
+ }
+ SendBytePort(*Format);
+ if(*(Format)==0x0a) SendBytePort(0x0d);
+ Format++;
+ }
+ va_end(ArgList);
+#endif
+}
+
+
+void
+ItoA( UINT32 Value, int Radix, char* pstr)
+{
+ char* tsptr = pstr;
+ char* rsptr = pstr;
+ char ch1,ch2;
+ unsigned int Reminder;
+//Create String
+ do{
+ Reminder = Value%Radix;
+ Value = Value/Radix;
+ if (Reminder<0xa) *tsptr=Reminder+'0';
+ else *tsptr=Reminder-0xa+'a';
+ tsptr++;
+ } while(Value);
+//Reverse String
+ *tsptr = 0;
+ tsptr--;
+ while(tsptr>rsptr){
+ ch1 = *tsptr;
+ ch2 = *rsptr;
+ *rsptr = ch1;
+ *tsptr = ch2;
+ tsptr--;
+ rsptr++;
+ }
+}
+
+void
+InitSerialOut(){
+ UINT8 Data;
+ UINT16 Divisor;
+ Data = 0x87;
+ WriteIO(COM_BASE_ADDRESS + 0x3,AccWidthUint8, &Data);
+ Divisor = 115200 / DIVISOR;
+ Data = Divisor & 0xFF;
+ WriteIO(COM_BASE_ADDRESS + 0x00,AccWidthUint8, &Data);
+ Data = Divisor >> 8;
+ WriteIO(COM_BASE_ADDRESS + 0x01,AccWidthUint8, &Data);
+ Data = 0x07;
+ WriteIO(COM_BASE_ADDRESS + 0x3,AccWidthUint8, &Data);
+}
+
+
+void
+SendStringPort(char* pstr){
+
+ while (*pstr!=0){
+ SendBytePort(*pstr);
+ pstr++;
+ }
+}
+
+void
+SendBytePort(UINT8 Data)
+{
+ int Count = 80;
+ UINT8 Status;
+ do {
+ ReadIO((COM_BASE_ADDRESS + 0x05),AccWidthUint8, &Status);
+ if(Status == 0xff) break;
+ // Loop port is ready
+ } while ( (Status & 0x20) == 0 && (--Count) != 0);
+ WriteIO(COM_BASE_ADDRESS + 0x00,AccWidthUint8, &Data);
+}
+#endif
--- /dev/null
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include "Platform.h"
+
+void DispatcherEntry(void *pConfig){
+
+#ifdef B1_IMAGE
+ void *pB2ImagePtr = NULL;
+ CIM_IMAGE_ENTRY pB2ImageEntry;
+#endif
+
+//#if CIM_DEBUG
+// InitSerialOut();
+//#endif
+
+ TRACE((DMSG_SB_TRACE, "CIM - SB700 Entry\n"));
+
+#ifdef B1_IMAGE
+ if ((UINT32)(((STDCFG*)pConfig)->pB2ImageBase) != 0xffffffff){
+ if (((STDCFG*)pConfig)->pB2ImageBase)
+ pB2ImagePtr = CheckImage('007S',(void*)((STDCFG*)pConfig)->pB2ImageBase);
+ if (pB2ImagePtr == NULL)
+ pB2ImagePtr = LocateImage('007S');
+ if (pB2ImagePtr!=NULL){
+ TRACE((DMSG_SB_TRACE, "CIM - SB700 Redirect to B2 Image\n"));
+ ((STDCFG*)pConfig)->pImageBase = (UINT32)pB2ImagePtr;
+ pB2ImageEntry = (CIM_IMAGE_ENTRY)(*((UINT32*)pB2ImagePtr+1) + (UINT32)pB2ImagePtr);
+ (*pB2ImageEntry)(pConfig);
+ return;
+ }
+ }
+#endif
+ saveConfigPointer(pConfig);
+
+ if (((STDCFG*)pConfig)->Func == SB_POWERON_INIT)
+ sbPowerOnInit((AMDSBCFG*)pConfig);
+
+#ifndef B1_IMAGE
+ if (((STDCFG*)pConfig)->Func == SB_BEFORE_PCI_INIT)
+ sbBeforePciInit((AMDSBCFG*)pConfig);
+ if (((STDCFG*)pConfig)->Func == SB_AFTER_PCI_INIT)
+ sbAfterPciInit((AMDSBCFG*)pConfig);
+ if (((STDCFG*)pConfig)->Func == SB_LATE_POST_INIT)
+ sbLatePost((AMDSBCFG*)pConfig);
+ if (((STDCFG*)pConfig)->Func == SB_BEFORE_PCI_RESTORE_INIT)
+ sbBeforePciRestoreInit((AMDSBCFG*)pConfig);
+ if (((STDCFG*)pConfig)->Func == SB_AFTER_PCI_RESTORE_INIT)
+ sbAfterPciRestoreInit((AMDSBCFG*)pConfig);
+ if (((STDCFG*)pConfig)->Func == SB_SMM_SERVICE)
+ {
+ // sbSmmService((AMDSBCFG*)pConfig);
+ }
+ if (((STDCFG*)pConfig)->Func == SB_SMM_ACPION)
+ sbSmmAcpiOn((AMDSBCFG*)pConfig);
+#endif
+ TRACE((DMSG_SB_TRACE, "CIMx - SB Exit\n"));
+}
+
+
+void* LocateImage(UINT32 Signature){
+ void *Result;
+ UINT8 *ImagePtr = (UINT8*)(0xffffffff - (IMAGE_ALIGN-1));
+ while ((UINT32)ImagePtr>=(0xfffffff - (NUM_IMAGE_LOCATION*IMAGE_ALIGN -1))){
+ Result = CheckImage(Signature,(void*)ImagePtr);
+ if (Result != NULL)
+ return Result;
+ ImagePtr -= IMAGE_ALIGN;
+ }
+ return NULL;
+}
+
+
+void* CheckImage(UINT32 Signature, void* ImagePtr){
+ UINT8 *TempImagePtr;
+ UINT8 Sum = 0;
+ UINT32 i;
+// if ((*((UINT32*)ImagePtr) == 'ITA$' && ((CIMFILEHEADER*)ImagePtr)->ModuleLogo == Signature)){
+ if ((*((UINT32*)ImagePtr) == Int32FromChar ('$', 'A', 'T', 'I')) && (((CIMFILEHEADER*)ImagePtr)->ModuleLogo == Signature)){
+ //GetImage Image size
+ TempImagePtr = (UINT8*)ImagePtr;
+ for (i=0;i<(((CIMFILEHEADER*)ImagePtr)->ImageSize);i++){
+ Sum += *TempImagePtr;
+ TempImagePtr++;
+ }
+ if (Sum == 0)
+ return ImagePtr;
+ }
+ return NULL;
+}
+
+
+UINT32 GetPciebase(){
+ AMDSBCFG* Result;
+ Result = getConfigPointer();
+ return Result->StdHeader.pPcieBase;
+}
+
+
+void saveConfigPointer(AMDSBCFG* pConfig){
+ UINT8 dbReg, i;
+ UINT32 ddValue;
+
+ ddValue = ((UINT32) pConfig);
+ dbReg = SB_ECMOS_REG08;
+
+ for (i=0; i<=3; i++){
+ WriteIO(SB_IOMAP_REG72, AccWidthUint8, &dbReg);
+ WriteIO(SB_IOMAP_REG73, AccWidthUint8, (UINT8 *)&ddValue);
+ ddValue >>= 8;
+ dbReg++;
+ }
+}
+
+
+AMDSBCFG* getConfigPointer(){
+ UINT8 dbReg, dbValue, i;
+ UINT32 ddValue=0;
+
+ dbReg = SB_ECMOS_REG08;
+ for (i=0; i<=3; i++){
+ WriteIO(SB_IOMAP_REG72, AccWidthUint8, &dbReg);
+ ReadIO(SB_IOMAP_REG73, AccWidthUint8, &dbValue);
+ ddValue |= (dbValue<<(i*8));
+ dbReg++;
+ }
+ return( (AMDSBCFG*) ddValue);
+}
+
+/**
+ * AmdSbDispatcher - Dispatch Southbridge function
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+AGESA_STATUS
+AmdSbDispatcher (
+ IN VOID *pConfig
+ )
+{
+ AGESA_STATUS Status = AGESA_SUCCESS;
+
+ saveConfigPointer (pConfig);
+
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_POWERON_INIT ) {
+ sbPowerOnInit ((AMDSBCFG*) pConfig);
+ }
+
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_INIT ) {
+ sbBeforePciInit ((AMDSBCFG*)pConfig);
+ }
+
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_INIT ) {
+ sbAfterPciInit ((AMDSBCFG*)pConfig);
+ }
+
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_LATE_POST_INIT ) {
+ sbLatePost ((AMDSBCFG*)pConfig);
+ }
+
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_BEFORE_PCI_RESTORE_INIT ) {
+ sbBeforePciRestoreInit ((AMDSBCFG*)pConfig);
+ }
+
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_AFTER_PCI_RESTORE_INIT ) {
+ sbAfterPciRestoreInit ((AMDSBCFG*)pConfig);
+ }
+
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_SERVICE ) {
+ sbSmmService ((AMDSBCFG*)pConfig);
+ }
+
+ if ( ((AMD_CONFIG_PARAMS*)pConfig)->Func == SB_SMM_ACPION ) {
+ sbSmmAcpiOn ((AMDSBCFG*)pConfig);
+ }
+
+ return Status;
+}
--- /dev/null
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include "Platform.h"
+
+#ifndef NO_EC_SUPPORT
+
+REG8MASK sb710PorInitPciTable[] = {
+ // SMBUS Device(Bus 0, Dev 20, Func 0)
+ {0x00, SMBUS_BUS_DEV_FUN, 0},
+ {SB_SMBUS_REG43, ~(UINT8)BIT3, 0x00}, //Make some hidden registers of smbus visible.
+ {SB_SMBUS_REG38, (UINT8)~(BIT7+BIT5+BIT4+BIT3+BIT2+BIT1), 0x0D},
+ {SB_SMBUS_REG38+1, ~(UINT8)(BIT2+BIT1), BIT3 },
+ {SB_SMBUS_REGE1, 0xFF, BIT1},
+ {SB_SMBUS_REG43, 0xFF, BIT3}, //Make some hidden registers of smbus invisible.
+ {0xFF, 0xFF, 0xFF},
+
+ // LPC Device(Bus 0, Dev 20, Func 3)
+ {0x00, LPC_BUS_DEV_FUN, 0},
+ {SB_LPC_REGB8+3, ~(UINT8)(BIT1), BIT7+BIT2},
+ {0xFF, 0xFF, 0xFF},
+};
+
+REG8MASK sb710PorPmioInitTbl[]={
+ // index andmask ormask
+ {SB_PMIO_REGD7, 0xFF, BIT5},
+ {SB_PMIO_REGBB, 0xFF, BIT5},
+};
+
+
+void ecPowerOnInit(BUILDPARAM *pBuildOptPtr, AMDSBCFG* pConfig){
+ UINT8 dbVar0, i=0;
+
+ if (!(isEcPresent()))
+ return; //return if EC is not enabled
+
+ for(i=0;i<0xFF;i++){
+ ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG40, AccWidthUint8 | S3_SAVE, &dbVar0);
+ if ( dbVar0 & BIT7 ) break; //break if EC is ready
+ Stall(500); //wait for EC to become ready
+ }
+
+ if (getRevisionID() >= SB700_A14){
+ programPciByteTable( (REG8MASK*)FIXUP_PTR(&sb710PorInitPciTable[0]), sizeof(sb710PorInitPciTable)/sizeof(REG8MASK) );
+ programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sb710PorPmioInitTbl[0]), (sizeof(sb710PorPmioInitTbl)/sizeof(REG8MASK)) );
+ }
+
+ RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBA), AccWidthUint8 | S3_SAVE, 0xFF, BIT2); //Enable SPI Prefetch in EC
+
+ //Enable config mode
+ EnterEcConfig();
+
+ //Do settings for mailbox - logical device 0x09
+ RWEC8(0x07, 0x00, 0x09); //switch to device 9 (Mailbox)
+ RWEC8(0x60, 0x00, (pBuildOptPtr->EcLdn9MailBoxAddr >> 8)); //set MSB of Mailbox port
+ RWEC8(0x61, 0x00, (pBuildOptPtr->EcLdn9MailBoxAddr & 0xFF)); //set LSB of Mailbox port
+ RWEC8(0x30, 0x00, 0x01); //;Enable Mailbox Registers Interface, bit0=1
+
+ if (pBuildOptPtr->EcKbd == CIMX_OPTION_ENABLED){
+ RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+3), AccWidthUint8 | S3_SAVE, 0xFF, BIT7+BIT3);
+ //Enable KBRST#, IRQ1 & IRQ12, GateA20 Function signal from IMC
+ RWPMIO(SB_PMIO_REGBB, AccWidthUint8, 0xFF, BIT3+BIT2+BIT1+BIT0);
+ //Disable LPC Decoding of port 60/64
+ RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG47), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT5, 0);
+ //Enable logical device 0x07 (Keyboard controller)
+ RWEC8(0x07, 0x00, 0x07);
+ RWEC8(0x30, 0x00, 0x01);
+ }
+
+ if (pBuildOptPtr->EcChannel0 == CIMX_OPTION_ENABLED){
+ //Logical device 0x08
+ RWEC8(0x07, 0x00, 0x08);
+ RWEC8(0x60, 0x00, 0x00);
+ RWEC8(0x61, 0x00, 0x62);
+ RWEC8(0x30, 0x00, 0x01); //;Enable Device 8
+ }
+ //Logical device 0x05
+ RWEC8(0x07, 0x00, 0x05); //Select logical device 05, IR controller
+ RWEC8(0x60, 0x00, pBuildOptPtr->EcLdn5MailBoxAddr >> 8);
+ RWEC8(0x61, 0x00, (pBuildOptPtr->EcLdn5MailBoxAddr & 0xFF));
+ RWEC8(0x70, 0xF0, (pBuildOptPtr->EcLdn5Irq)); //Set IRQ to 05h
+ RWEC8(0x30, 0x00, 0x01); //Enable logical device 5, IR controller
+
+ RWPMIO(SB_PMIO_REGBB, AccWidthUint8, 0xFF, BIT4); //Enable EC(IMC) to generate SMI to BIOS
+ ExitEcConfig();
+}
+
+
+void ecInitBeforePciEnum(AMDSBCFG* pConfig){
+ if (!(isEcPresent()))
+ return; //return if EC is not enabled
+}
+
+
+void ecInitLatePost(AMDSBCFG* pConfig){
+ if (!(isEcPresent()) )
+ return; //return if EC is not enabled
+ //Enable config mode
+ EnterEcConfig(); //Enable config mode
+ //for future use
+ ExitEcConfig();
+}
+
+#endif
--- /dev/null
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include "Platform.h"
+
+void fcInitBeforePciEnum(AMDSBCFG* pConfig){
+
+ TRACE((DMSG_SB_TRACE, "Entering PreInit Flash \n"));
+ RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)BIT1, 00);
+
+ //Enable IDE and disable flash
+ //Enable IDE and disable flash
+ RWPMIO(SB_PMIO_REG59, AccWidthUint8, ~(UINT32)(BIT1+BIT0), 0);
+ RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)(BIT3), BIT0); //Configure GPIO3 as IDE_RST# and release RST
+ if (pConfig->IdeController){
+ //Disabling IDE controller
+ RWPCI((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG04, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT2+BIT1+BIT0), 0);
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGAE, AccWidthUint8 | S3_SAVE, 0xFF, BIT3);
+ }
+ else{
+ //Enable IDE controller
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGAE, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT3), 0);
+ }
+
+ //RPR 8.2 Enable IDE Data bus DD7 Pull down Resistor if IDE is enabled and FC is disabled
+ RWPMIO2(SB_PMIO2_REGE5, AccWidthUint8, 0xFF, BIT2);
+ //Slowdown the clock to FC if FC is not enabled, this is a power savings feature
+ RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)(BIT4), BIT4);
+ RWPMIO(SB_PMIO_REGBC, AccWidthUint8, 0xC0, 0);
+}
--- /dev/null
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include "Platform.h"
+
+UINT32 GetFixUp(){
+ STDCFG* Result;
+ Result = (STDCFG*) getConfigPointer();
+ return Result->pImageBase;
+}
--- /dev/null
+#*****************************************************************************
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+# * Neither the name of Advanced Micro Devices, Inc. nor the names of
+# its contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#*****************************************************************************
+
+# CIMX Root directory
+CIMX_ROOT = $(src)/vendorcode/amd/cimx
+
+SB_CIMX_INC = -I$(src)/mainboard/$(MAINBOARDDIR)
+SB_CIMX_INC += -I$(src)/southbridge/amd/cimx/sb700
+SB_CIMX_INC += -I$(CIMX_ROOT)/sb700
+
+romstage-y += ACPILIB.c
+romstage-y += AMDLIB.c
+romstage-y += AMDSBLIB.c
+romstage-y += AZALIA.c
+romstage-y += DEBUG.c
+romstage-y += DISPATCHER.c
+romstage-y += EC.c
+romstage-y += FLASH.c
+romstage-y += SATA.c
+romstage-y += SBCMN.c
+romstage-y += SBCMNLIB.c
+romstage-y += SBMAIN.c
+romstage-y += SBPOR.c
+romstage-y += SMM.c
+romstage-y += USB.c
+
+ramstage-y += ACPILIB.c
+ramstage-y += AMDLIB.c
+ramstage-y += AMDSBLIB.c
+ramstage-y += AZALIA.c
+ramstage-y += DEBUG.c
+ramstage-y += DISPATCHER.c
+ramstage-y += EC.c
+ramstage-y += FLASH.c
+ramstage-y += SATA.c
+ramstage-y += SBCMN.c
+ramstage-y += SBCMNLIB.c
+ramstage-y += SBMAIN.c
+ramstage-y += SBPOR.c
+ramstage-y += SMM.c
+ramstage-y += USB.c
+ramstage-y += LEGACY.c
+
+SB_CIMX_CFLAGS =
+export CIMX_ROOT
+export SB_CIMX_INC
+export SB_CIMX_CFLAGS
+CC := $(CC) $(SB_CIMX_CFLAGS) $(SB_CIMX_INC)
+
+#######################################################################
+
--- /dev/null
+/*;********************************************************************************
+;
+; Copyright (C) 2012 Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; * Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; * Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; * Neither the name of Advanced Micro Devices, Inc. nor the names of
+; its contributors may be used to endorse or promote products derived
+; from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*********************************************************************************/
+#ifndef _AMD_SB_CIMx_OEM_H_
+#define _AMD_SB_CIMx_OEM_H_
+
+#define BIOS_SIZE 0x04 //04 - 1MB
+#define LEGACY_FREE 0x00
+
+/**
+ * PCIEX_BASE_ADDRESS - Define PCIE base address
+ *
+ * @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000
+ */
+#ifdef MOVE_PCIEBAR_TO_F0000000
+ #define PCIEX_BASE_ADDRESS 0xF7000000
+#else
+ #define PCIEX_BASE_ADDRESS 0xE0000000
+#endif
+
+
+#define SMBUS0_BASE_ADDRESS 0xB00
+#define SMBUS1_BASE_ADDRESS 0xB20
+#define SIO_PME_BASE_ADDRESS 0xE00
+#define SPI_BASE_ADDRESS 0xFEC10000
+
+#define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 // Watchdog Timer Base Address
+#define HPET_BASE_ADDRESS 0xFED00000 // HPET Base address
+
+#define PM1_EVT_BLK_ADDRESS 0x800 // AcpiPm1EvtBlkAddr;
+#define PM1_CNT_BLK_ADDRESS 0x804 // AcpiPm1CntBlkAddr;
+#define PM1_TMR_BLK_ADDRESS 0x808 // AcpiPmTmrBlkAddr;
+#define CPU_CNT_BLK_ADDRESS 0x810 // CpuControlBlkAddr;
+#define GPE0_BLK_ADDRESS 0x820 // AcpiGpe0BlkAddr;
+#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr;
+#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr;
+
+#define EC_LDN5_MAILBOX_ADDRESS 0x550
+#define EC_LDN5_IRQ 0x05
+#define EC_LDN9_MAILBOX_ADDRESS 0x3E
+
+#define SATA_IDE_MODE_SSID 0x43901002
+#define SATA_RAID_MODE_SSID 0x43921002
+#define SATA_RAID5_MODE_SSID 0x43931002
+#define SATA_AHCI_SSID 0x43911002
+#define OHCI0_SSID 0x43971002
+#define OHCI1_SSID 0x43981002
+#define EHCI0_SSID 0x43961002
+#define OHCI2_SSID 0x43971002
+#define OHCI3_SSID 0x43981002
+#define EHCI1_SSID 0x43961002
+#define OHCI4_SSID 0x43991002
+
+#define SMBUS_SSID 0x43851002
+#define IDE_SSID 0x439C1002
+#define AZALIA_SSID 0x43831002
+#define LPC_SSID 0x439D1002
+#define P2P_SSID 0x43841002
+
+#define RESERVED_VALUE 0x00
+
+#endif //ifndef _AMD_SB_CIMx_OEM_H_
--- /dev/null
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include "Platform.h"
+
+//Table for class code of SATA Controller in different modes
+UINT32 sataIfCodeTable[] = {
+ 0x01018f00, //sata class ID of IDE
+ 0x01040000, //sata class ID of RAID
+ 0x01060100, //sata class ID of AHCI
+ 0x01018a00, //sata class ID of Legacy IDE
+ 0x01018f00, //sata class ID of IDE to AHCI mode
+ 0x01060100, //sata class ID of AMD-AHCI mode
+ 0x01018f00 //sata class ID of IDE to AMD-AHCI mode
+};
+
+//Table for device id of SATA Controller in different modes
+UINT16 sataDeviceIDTable[] = {
+ 0x4390, //sata device ID of IDE
+ 0x4392, //sata device ID of RAID
+ 0x4391, //sata class ID of AHCI
+ 0x4390, //sata device ID of Legacy IDE
+ 0x4390, //sata device ID of IDE->AHCI mode
+ 0x4394, //sata device ID for AMD-AHCI mode
+ 0x4390 //sata device ID of IDE->AMDAHCI mode
+};
+
+
+void sataInitBeforePciEnum(AMDSBCFG* pConfig){
+ UINT32 ddValue, *tempptr;
+ UINT16 *pDeviceIdptr, dwDeviceId;
+ UINT8 dbValue, dbOrMask, dbAndMask;
+
+
+ dbAndMask=0;
+ dbOrMask=0;
+ // Enable/Disable Combined mode & do primary/secondary selections, enable/disable
+ if (pConfig->SataIdeCombinedMode == CIMX_OPTION_DISABLED) dbAndMask= BIT3; //Clear BIT3
+ if (pConfig->SataIdeCombMdPriSecOpt == 1) dbOrMask = BIT4; //Set BIT4
+ if (pConfig->SataSmbus == 0) dbOrMask = BIT1;
+
+ RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGAD), AccWidthUint8 | S3_SAVE, ~(dbAndMask), dbOrMask);
+
+ if (pConfig->SataController == 0){
+ // SATA Controller Disabled & set Power Saving mode to disabled
+ RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGAD), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, BIT1);
+ return;
+ }
+
+ restrictSataCapabilities(pConfig);
+
+ // Get the appropriate class code from the table and write it to PCI register 08h-0Bh
+ // Set the appropriate SATA class based on the input parameters
+ dbValue=pConfig->SataClass;
+ tempptr= (UINT32 *) FIXUP_PTR (&sataIfCodeTable[0]);
+ ddValue=tempptr[dbValue];
+
+ // BIT0: Enable write access to PCI header (reg 08h-0Bh) by setting SATA PCI register 40h, bit 0
+ // BIT4:disable fast boot
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT4+BIT0);
+
+ // Write the class code to SATA PCI register 08h-0Bh
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, ddValue);
+
+ if (pConfig->SataClass == LEGACY_IDE_MODE) //SATA = Legacy IDE
+ //Set PATA controller to native mode
+ RWPCI(((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG09), AccWidthUint8 | S3_SAVE, 0x00, 0x08F);
+
+ //Change the appropriate device id
+ if (pConfig->SataClass == AMD_AHCI_MODE) {
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 3), AccWidthUint8 | S3_SAVE, 0xff, BIT0);
+ }
+ pDeviceIdptr= (UINT16 *) FIXUP_PTR (&sataDeviceIDTable[0]);
+
+ ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, &dwDeviceId);
+ if ( !((dwDeviceId==SB750_SATA_DEFAULT_DEVICE_ID) && (pConfig->SataClass == RAID_MODE)) ){
+ //if not (SB750 & RAID mode), then program the device id
+ dwDeviceId=pDeviceIdptr[dbValue];
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, dwDeviceId);
+ }
+
+ if (pConfig->AcpiS1Supported)
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG34), AccWidthUint8 | S3_SAVE, 00, 0x70);//Disable SATA PM & MSI capability
+ else
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG60+1), AccWidthUint8 | S3_SAVE, 00, 0x70);//Disable SATA MSI capability
+
+ if (getRevisionID() >= SB700_A13){
+ //Enable test/enhancement mode for A13
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40+3), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT5, 00);
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG48), AccWidthUint32 | S3_SAVE, ~(UINT32)(BIT24+BIT21), 0xBF80);
+ }
+
+ if (getRevisionID() >= SB700_A14){
+ //Fix for TT SB01352 - LED Stays On When ODD Attached To Slave Port In IDE Mode
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG48), AccWidthUint8 | S3_SAVE, 0xFF, BIT6);
+ }
+
+ // Disable write access to PCI header
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, 0);
+
+ // RPR 6.5 SATA PHY Programming Sequence
+ RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG86, AccWidthUint16 | S3_SAVE, 0x00, 0x2C00);
+ RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG88, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016);
+ RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG8C, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016);
+ RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG90, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016);
+ RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG94, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016);
+ RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG98, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016);
+ RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG9C, AccWidthUint32 | S3_SAVE, 0x00, 0x01B48016);
+ RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REGA0, AccWidthUint32 | S3_SAVE, 0x00, 0xA07AA07A);
+ RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REGA4, AccWidthUint32 | S3_SAVE, 0x00, 0xA07AA07A);
+ RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REGA8, AccWidthUint32 | S3_SAVE, 0x00, 0xA07AA07A);
+
+ CallBackToOEM(SATA_PHY_PROGRAMMING, NULL, pConfig);
+}
+
+void sataInitAfterPciEnum(AMDSBCFG* pConfig){
+ UINT32 ddAndMask=0, ddOrMask=0, ddBar5=0;
+ UINT8 dbVar, dbPortNum;
+
+ if (pConfig->SataController == 0) return; //return if SATA controller is disabled.
+
+ //Enable write access to pci header, pm capabilities
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
+
+ //Disable AHCI enhancement function (RPR 7.2)
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8 | S3_SAVE, 0xFF, BIT7);
+
+ restrictSataCapabilities(pConfig);
+
+ ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5);
+
+ if ( (ddBar5 == 0) || (ddBar5 == -1) ) {
+ //assign temporary BAR5
+ if ( (pConfig->TempMMIO == 0) || (pConfig->TempMMIO == -1))
+ ddBar5 = 0xFEC01000;
+ else
+ ddBar5=pConfig->TempMMIO;
+
+ WritePCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5);
+ }
+
+ ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar);
+ RWPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8,0xFF, 0x03); //memory and io access enable
+
+ ddBar5 &= 0xFFFFFC00; //Clear Bits 9:0
+ if (!pConfig->SataPortMultCap)
+ ddAndMask |= BIT12;
+ if (!pConfig->SataAggrLinkPmCap)
+ ddAndMask |= BIT11;
+ if (pConfig->SataSscPscCap)
+ ddOrMask |= BIT1;
+
+ RWMEM((ddBar5 + SB_SATA_BAR5_REGFC),AccWidthUint32 | S3_SAVE, ~ddAndMask, ddOrMask);
+
+
+ //Clear HPCP and ESP by default
+ RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, 0xFFFC0FC0, 0);
+
+ if (pConfig->SataHpcpButNonESP !=0) {
+ RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, 0xFFFFFFC0, pConfig->SataHpcpButNonESP);
+ }
+
+ // SATA ESP port setting
+ // These config bits are set for SATA driver to identify which ports are external SATA ports and need to
+ // support hotplug. If a port is set as an external SATA port and need to support hotplug, then driver will
+ // not enable power management(HIPM & DIPM) for these ports.
+ if (pConfig->SataEspPort !=0) {
+ RWMEM((ddBar5 + SB_SATA_BAR5_REGFC),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT20);
+ RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, ~(pConfig->SataEspPort), 0);
+ RWMEM((ddBar5 + SB_SATA_BAR5_REGF8),AccWidthUint32 | S3_SAVE, ~(UINT32)(BIT17+BIT16+BIT15+BIT14+BIT13+BIT12),(pConfig->SataEspPort << 12));
+ }
+
+ if ( ((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE) )
+ RWPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG50+2), AccWidthUint8, ~(UINT32)(BIT3+BIT2+BIT1), BIT2+BIT1); //set MSI to 8 messages
+
+ if ( ((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE) && ((pConfig->SataIdeCombinedMode) == CIMX_OPTION_DISABLED) ){
+ RWMEM((ddBar5 + SB_SATA_BAR5_REG00),AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT2+BIT1+BIT0), BIT2+BIT0);
+ RWMEM((ddBar5 + SB_SATA_BAR5_REG0C),AccWidthUint8 | S3_SAVE, 0xC0, 0x3F);
+ }
+
+ for (dbPortNum=0;dbPortNum<=5;dbPortNum++){
+ if (pConfig->SataPortMode & (1 << dbPortNum)){
+ //downgrade to GEN1
+ RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0x0F, 0x10);
+ RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFF, 0x01);
+ Stall(1000);
+ RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFE, 0x00);
+ }
+ }
+
+ //If this is not S3 resume and also if SATA set to one of IDE mode, then implement drive detection workaround.
+ if ( !(pConfig->S3Resume) && ( ((pConfig->SataClass) != AHCI_MODE) && ((pConfig->SataClass) != RAID_MODE) && ((pConfig->SataClass) != AMD_AHCI_MODE) ) )
+ sataDriveDetection(pConfig, ddBar5);
+
+ if ( (pConfig->SataPhyWorkaround==1) || ( (pConfig->SataPhyWorkaround==0) && (getRevisionID() < SB700_A13)) )
+ sataPhyWorkaround(pConfig, ddBar5);
+
+ // Set the handshake bit for IDE driver to detect the disabled IDE channel correctly.
+ // Set IDE PCI Config 0x63 [3] if primary channel disabled, [4] if secondary channel disabled.
+ if (pConfig->SataIdeCombinedMode == CIMX_OPTION_DISABLED)
+ RWPCI( ((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG63), AccWidthUint8 , 0xF9, (0x02 << (pConfig->SataIdeCombMdPriSecOpt)) );
+
+ WritePCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar);
+
+ //Disable write access to pci header, pm capabilities
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, 0);
+}
+
+
+void sataDriveDetection(AMDSBCFG* pConfig, UINT32 ddBar5){
+ UINT32 ddVar0;
+ UINT8 dbPortNum, dbVar0;
+ UINT16 dwIoBase, dwVar0;
+
+ TRACE((DMSG_SB_TRACE, "CIMx - Entering sata drive detection procedure\n\n"));
+ TRACE((DMSG_SB_TRACE, "SATA BAR5 is %X \n", ddBar5));
+
+ if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE) ){
+ for (dbPortNum=0;dbPortNum<4;dbPortNum++){
+ ReadMEM(ddBar5+ SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint32, &ddVar0);
+ if ( ( ddVar0 & 0x0F ) == 0x03){
+ if ( dbPortNum & BIT0)
+ //this port belongs to secondary channel
+ ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG18), AccWidthUint16, &dwIoBase);
+ else
+ //this port belongs to primary channel
+ ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG10), AccWidthUint16, &dwIoBase);
+
+ //if legacy ide mode, then the bar registers don't contain the correct values. So we need to hardcode them
+ if (pConfig->SataClass == LEGACY_IDE_MODE)
+ dwIoBase = ( (0x170) | ( (~((dbPortNum & BIT0) << 7)) & 0x80 ) );
+
+ if ( dbPortNum & BIT1)
+ //this port is slave
+ dbVar0=0xB0;
+ else
+ //this port is master
+ dbVar0=0xA0;
+ dwIoBase &= 0xFFF8;
+ WriteIO(dwIoBase+6, AccWidthUint8, &dbVar0);
+
+ //Wait in loop for 30s for the drive to become ready
+ for (dwVar0=0;dwVar0<3000;dwVar0++){
+ ReadIO(dwIoBase+7, AccWidthUint8, &dbVar0);
+ if ( (dbVar0 & 0x88) == 0)
+ break;
+ Stall(10000);
+ }
+ } //end of if ( ( ddVar0 & 0x0F ) == 0x03)
+ } //for (dbPortNum=0;dbPortNum<4;dbPortNum++)
+ } //if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE) )
+}
+
+
+//This patch is to workaround the SATA PHY logic hardware issue in the SB700.
+//Internally this workaround is called as 7NewA
+void sataPhyWorkaround(AMDSBCFG* pConfig, UINT32 ddBar5){
+
+ UINT8 dbPortNum, dbVar0;
+
+ if (pConfig->Gen1DeviceShutdownDuringPhyWrknd == 0x01){
+ for (dbPortNum=0;dbPortNum<=5;dbPortNum++){
+ ReadMEM(ddBar5+ SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint8, &dbVar0);
+ if ( (dbVar0 & 0xF0) == 0x10){
+ RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40+2, AccWidthUint8 | S3_SAVE, 0xFF, (01 << dbPortNum));
+ }
+
+ }
+ }
+
+ RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)(BIT4+BIT3), BIT4+BIT3);//set PMIO_D0[4:3] = 11b // this is to tell SATA PHY to use the internal 100MHz clock
+ RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG86, AccWidthUint8 | S3_SAVE, 0x00, 0x40);// set SATA PCI_CFG 0x86[7:0] = 0x40 //after the reset is done, perform this to turn on the diff clock path into SATA PHY
+ Stall(2000);// Wait for 2ms
+ RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)(BIT4+BIT3), 00);//13. set PMIO_D0[4:3] = 00b
+ Stall(20000);// Wait 20ms
+ forceOOB(ddBar5);// Force OOB
+
+ RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40+2, AccWidthUint8 | S3_SAVE, ~(0x03F), 00);
+}
+
+
+void forceOOB(UINT32 ddBar5){
+ UINT8 dbPortNum;
+ for (dbPortNum=0;dbPortNum<=5;dbPortNum++)
+ RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFF, 0x01);
+ Stall(2000);
+ for (dbPortNum=0;dbPortNum<=5;dbPortNum++)
+ RWMEM(ddBar5+ SB_SATA_BAR5_REG12C + dbPortNum * 0x80, AccWidthUint8, 0xFE, 0x00);
+ Stall(2000);// Wait for 2ms
+}
+
+/*++
+
+Routine Description:
+
+ SATA Late Configuration
+
+ if the mode is selected as IDE->AHCI
+ { 1. Set class ID to AHCI
+ 2. Enable AHCI interrupt
+ }
+
+Arguments:
+
+ pConfig - SBconfiguration
+
+Returns:
+
+ void
+
+--*/
+void sataInitLatePost(AMDSBCFG* pConfig){
+ UINT32 ddBar5;
+ UINT8 dbVar;
+
+ //Return immediately is sata controller is not enabled
+ if (pConfig->SataController == 0) return;
+
+ restrictSataCapabilities(pConfig);
+
+ //Get BAR5 value
+ ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5);
+
+ //Assign temporary BAR if is not already assigned
+ if ( (ddBar5 == 0) || (ddBar5 == -1) ){
+ //assign temporary BAR5
+ if ( (pConfig->TempMMIO == 0) || (pConfig->TempMMIO == -1))
+ ddBar5 = 0xFEC01000;
+ else
+ ddBar5=pConfig->TempMMIO;
+ WritePCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5);
+ }
+
+ ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar);
+ //Enable memory and io access
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, 0xFF, 0x03);
+ //Enable write access to pci header, pm capabilities
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0);
+
+ shutdownUnconnectedSataPortClock(pConfig, ddBar5);
+
+ if ( (pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE)){
+ //program the AHCI class code
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG08), AccWidthUint32 | S3_SAVE, 0, 0x01060100);
+ //Set interrupt enable bit
+ RWMEM((ddBar5 + 0x04),AccWidthUint8,~(UINT32)0,BIT1);
+ //program the correct device id for AHCI mode
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, 0, 0x4391);
+
+ if (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE)
+ //program the correct device id for AMD-AHCI mode
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 3), AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
+ }
+
+ //Disable write access to pci header and pm capabilities
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, 0);
+ //Clear error status
+ RWMEM((ddBar5 + SB_SATA_BAR5_REG130),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
+ RWMEM((ddBar5 + SB_SATA_BAR5_REG1B0),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
+ RWMEM((ddBar5 + SB_SATA_BAR5_REG230),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
+ RWMEM((ddBar5 + SB_SATA_BAR5_REG2B0),AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, 0xFFFFFFFF);
+ //Restore memory and io access bits
+ WritePCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG04), AccWidthUint8, &dbVar );
+}
+
+
+void shutdownUnconnectedSataPortClock(AMDSBCFG* pConfig, UINT32 ddBar5){
+ UINT8 dbPortNum, dbPortSataStatus, NumOfPorts=0;
+ UINT8 UnusedPortBitMap;
+ UINT8 SataType;
+ UINT8 ClockOffEnabled ;
+
+ UnusedPortBitMap = 0;
+
+ // First scan for all unused SATA ports
+ for (dbPortNum = 5; dbPortNum <= 5; dbPortNum--) {
+ ReadMEM (ddBar5 + SB_SATA_BAR5_REG128 + (dbPortNum * 0x80), AccWidthUint8, &dbPortSataStatus);
+ if ((!(dbPortSataStatus & 0x01)) && (!((pConfig->SataEspPort) & (1 << dbPortNum)))) {
+ UnusedPortBitMap |= (1 << dbPortNum);
+ }
+ }
+
+ // Decide if we need to shutdown the clock for all unused ports
+ SataType = pConfig->SataClass;
+ ClockOffEnabled = (pConfig->SataClkAutoOff && ((SataType == NATIVE_IDE_MODE) || (SataType == LEGACY_IDE_MODE) || \
+ (SataType == IDE_TO_AHCI_MODE) || (SataType == IDE_TO_AMD_AHCI_MODE))) || \
+ (pConfig->SataClkAutoOffAhciMode && ((SataType == AHCI_MODE) || (SataType == AMD_AHCI_MODE)));
+
+ if (ClockOffEnabled) {
+ //Shutdown the clock for the port and do the necessary port reporting changes.
+ TRACE((DMSG_SB_TRACE, "Shutting down clock for SATA ports %X \n", UnusedPortBitMap));
+ RWPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, UnusedPortBitMap);
+ RWMEM(ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, ~UnusedPortBitMap, 00);
+ }
+
+ // If all ports are in disabled state, report at least one
+ ReadMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, &dbPortSataStatus);
+ if ( (dbPortSataStatus & 0x3F) == 0) {
+ dbPortSataStatus = 1;
+ RWMEM (ddBar5 + SB_SATA_BAR5_REG0C, AccWidthUint8, ~(0x3F), dbPortSataStatus);
+ }
+
+ // Decide if we need to hide unused ports from being seen by OS (this saves OS startup time)
+ if (pConfig->SataHideUnusedPort && ClockOffEnabled) {
+ dbPortSataStatus &= ~UnusedPortBitMap; // Mask off unused ports
+ for (dbPortNum = 0; dbPortNum <= 6; dbPortNum++) {
+ if (dbPortSataStatus & (1 << dbPortNum))
+ NumOfPorts++;
+ }
+ if (NumOfPorts == 0 ) {
+ NumOfPorts = 0x01;
+ }
+ RWMEM (ddBar5 + SB_SATA_BAR5_REG00, AccWidthUint8, 0xE0, NumOfPorts - 1);
+ }
+}
+
+
+void restrictSataCapabilities(AMDSBCFG* pConfig){
+ //Restrict capabilities
+ if ( ((getSbCapability(Sb_Raid0_1_Capability)== 0x02) && (pConfig->SataClass == RAID_MODE)) || \
+ ((getSbCapability(Sb_Raid5_Capability)== 0x02) && (pConfig->SataClass == RAID_MODE)) || \
+ ((getSbCapability(Sb_Ahci_Capability)== 0x02) && ((pConfig->SataClass == AHCI_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE)))){
+ pConfig->SataClass = NATIVE_IDE_MODE;
+ }
+}
--- /dev/null
+/*;********************************************************************************
+;
+; Copyright (C) 2012 Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; * Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; * Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; * Neither the name of Advanced Micro Devices, Inc. nor the names of
+; its contributors may be used to endorse or promote products derived
+; from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*********************************************************************************/
+
+#ifndef _AMD_SB700_H_
+#define _AMD_SB700_H_
+
+#pragma pack(push,1)
+
+#define CIMx_Version 0x0660
+#define RC_Information 0x00
+#define Additional_Changes_Indicator 0x00
+
+#define SB_POWERON_INIT 0x001
+#define OUTDEBUG_PORT 0x002
+#define SB_BEFORE_PCI_INIT 0x010
+#define SB_AFTER_PCI_INIT 0x020
+#define SB_LATE_POST_INIT 0x030
+#define SB_BEFORE_PCI_RESTORE_INIT 0x040
+#define SB_AFTER_PCI_RESTORE_INIT 0x050
+#define SB_SMM_SERVICE 0x060
+#define SB_SMM_ACPION 0x061
+
+#ifndef OEM_CALLBACK_BASE
+ #define OEM_CALLBACK_BASE 0x100
+#endif
+
+//0x00 - 0x0F callback functions are reserved for bootblock
+#define SATA_PHY_PROGRAMMING OEM_CALLBACK_BASE + 0x10
+#define PULL_UP_PULL_DOWN_SETTINGS OEM_CALLBACK_BASE + 0x20
+
+#define CFG_ADDR_PORT 0xCF8
+#define CFG_DATA_PORT 0xCFC
+#define ATI_AZALIA_ExtBlk_Addr 0x0F8
+#define ATI_AZALIA_ExtBlk_DATA 0x0FC
+
+#define ALINK_ACCESS_INDEX 0x0CD8
+#define ALINK_ACCESS_DATA ALINK_ACCESS_INDEX + 4
+
+/*------------------------------------------------------------------
+; I/O Base Address - Should be set by host BIOS
+;------------------------------------------------------------------ */
+#define DELAY_PORT 0x0E0
+
+/*------------------------------------------------------------------
+; DEBUG_PORT = 8-bit I/O Port Address for POST Code Display
+;------------------------------------------------------------------ */
+#define SB7XX_DEVICE_ID 0x4385
+
+#define SB700_A11 0x39
+#define SB700_A12 0x3A
+#define SB700_A13 0x3B
+#define SB700_A14 0x3C
+#define SB700_A15 0x3D
+
+#define SATA_BUS_DEV_FUN ((0x11 << 3) + 0)
+#define FC_BUS_DEV_FUN ((0x11 << 3) + 1)
+#define USB1_OHCI0_BUS_DEV_FUN ((0x12 << 3) + 0)
+#define USB1_OHCI1_BUS_DEV_FUN ((0x12 << 3) + 1)
+#define USB2_OHCI0_BUS_DEV_FUN ((0x13 << 3) + 0)
+#define USB2_OHCI1_BUS_DEV_FUN ((0x13 << 3) + 1)
+#define USB3_OHCI_BUS_DEV_FUN ((0x14 << 3) + 5)
+#define USB1_EHCI_BUS_DEV_FUN ((0x12 << 3) + 2)
+#define USB2_EHCI_BUS_DEV_FUN ((0x13 << 3) + 2)
+
+#define SMBUS_BUS_DEV_FUN ((0x14 << 3) + 0)
+#define IDE_BUS_DEV_FUN ((0x14 << 3) + 1)
+#define AZALIA_BUS_DEV_FUN ((0x14 << 3) + 2)
+#define LPC_BUS_DEV_FUN ((0x14 << 3) + 3)
+#define SBP2P_BUS_DEV_FUN ((0x14 << 3) + 4)
+#define NB_BDF ((0 << 3) + 0)
+#define HT_LINK_BUS_DEV_FUN ((0x18 << 3) + 0)
+#define DCT1_BUS_DEV_FUN ((0x18 << 3) + 2)
+#define DCT2_BUS_DEV_FUN ((0x19 << 3) + 2)
+#define DCT3_BUS_DEV_FUN ((0x1A << 3) + 2)
+#define DCT4_BUS_DEV_FUN ((0x1B << 3) + 2)
+
+
+//Sata Controller Mode
+#define NATIVE_IDE_MODE 0
+#define RAID_MODE 1
+#define AHCI_MODE 2
+#define LEGACY_IDE_MODE 3
+#define IDE_TO_AHCI_MODE 4
+#define AMD_AHCI_MODE 5
+#define IDE_TO_AMD_AHCI_MODE 6
+
+//Sata Port Configuration
+#define SIX_PORTS 0
+#define FOUR_PORTS 1
+
+#define SB750_SATA_DEFAULT_DEVICE_ID 0x4393
+
+#define SB_AX_INDXC_REG30 0x30
+#define SB_AX_DATAC_REG34 0x34
+#define SB_AX_INDXP_REG38 0x38
+#define SB_AX_DATAP_REG3C 0x3C
+
+#define AX_INDXC 0
+#define AX_INDXP 1
+#define AXCFG 2
+#define ABCFG 3
+
+#define SB_AB_REG02 0x02
+#define SB_AB_REG04 0x04
+#define SB_AB_REG40 0x40 //
+#define SB_AB_REG54 0x54 //;miscCtr54
+#define SB_AB_REG58 0x58 //;RAB Control - RW - 32 bits - [RegAddr:58]
+#define SB_AB_REG60 0x60 //;DMA Prefetch Enable Port 0 - RW - 32 bits - [RegAddr:60]
+#define SB_AB_REG64 0x64 //;DMA Prefetch Flush Port 0 - RW - 32 bits - [RegAddr:64]
+#define SB_AB_REG6C 0x6C //;DMA Prefetch Flush Port 0 - RW - 32 bits - [RegAddr:6C]
+#define SB_AB_REG80 0x80 //;DMA Prefetch Control Port 1 - RW - 32 bits - [RegAddr:80]
+#define SB_AB_REG88 0x88 //;DMA Prefetch Control Port 2 - RW - 32 bits - [RegAddr:88]
+#define SB_AB_REG8C 0x8C //;AB Enhancement - RW - 16 bits - [RegAddr:88]
+#define SB_AB_REG90 0x90 //;BIF Control - RW - 32 bits - [RegAddr:90]
+#define SB_AB_REG94 0x94 //;MSI Control - RW - 32 bits
+#define SB_AB_REG98 0x98 //;BIF Control 1 - RW - 32 bits
+#define SB_AB_REG9C 0x9C //;
+#define SB_AB_REG10050 BIT16+0x50
+#define SB_AB_REG10054 BIT16+0x54 //;AL_Arb_Ctl, AL_Clk_Ctl
+#define SB_AB_REG10060 BIT16+0x60 //;DMA Prefetch Enable Port 0 - RW - 32 bits - [RegAddr:10060]
+#define SB_AB_REG10064 BIT16+0x64 //;DMA Prefetch Flush Port 0 - RW - 32 bits - [RegAddr:64]
+#define SB_AB_REG10090 BIT16+0x90 //;
+#define SB_AB_REG1009C BIT16+0x9C //;
+
+
+#define SB_PMIO_REG00 0x000 // MiscControl
+#define SB_PMIO_REG01 0x001 // MiscStatus
+#define SB_PMIO_REG02 0x002 // SmiWakeUpEventEnable1
+#define SB_PMIO_REG03 0x003 // SmiWakeUpEventEnable2
+#define SB_PMIO_REG04 0x004 // SmiWakeUpEventEnable3
+#define SB_PMIO_REG05 0x005 // SmiWakeUpEventStatus1
+#define SB_PMIO_REG06 0x006 // SmiWakeUpEventStatus2
+#define SB_PMIO_REG07 0x007 // SmiWakeUpEventStatus3
+#define SB_PMIO_REG08 0x008 // InactiveTmrEventEnable1
+#define SB_PMIO_REG09 0x009 // InactiveTmrEventEnable2
+#define SB_PMIO_REG0A 0x00A // InactiveTmrEventEnable3
+#define SB_PMIO_REG0B 0x00B // PmTmr1InitValue
+#define SB_PMIO_REG0C 0x00C // PmTmr1CurValue
+#define SB_PMIO_REG0D 0x00D // PwrLedExtEvent
+#define SB_PMIO_REG0E 0x00E // AcpiControl
+#define SB_PMIO_REG0F 0x00F // AcpiStatus
+#define SB_PMIO_REG10 0x010 // AcpiEn
+#define SB_PMIO_REG11 0x011 // S1AgpStpEn
+#define SB_PMIO_REG12 0x012 // PmTmr2InitValue
+#define SB_PMIO_REG13 0x013 // PmTmr2CurValue
+#define SB_PMIO_REG14 0x014 // Programlo0RangeLo
+#define SB_PMIO_REG15 0x015 // ProgramIo0Rangei
+#define SB_PMIO_REG16 0x016 // ProgramIo1RangeLo
+#define SB_PMIO_REG17 0x017 // ProgramIo1Rangei
+#define SB_PMIO_REG18 0x018 // ProgramIo2RangeLo
+#define SB_PMIO_REG19 0x019 // ProgramIo2Rangei
+#define SB_PMIO_REG1A 0x01A // ProgramIo3RangeLo
+#define SB_PMIO_REG1B 0x01B // ProgramIo3Rangei
+#define SB_PMIO_REG1C 0x01C // ProgramIoEnable
+#define SB_PMIO_REG1D 0x01D // IOMonitorStatus
+#define SB_PMIO_REG1E 0x01E // InactiveTmrEventEnable4
+#define SB_PMIO_REG20 0x020 // AcpiPm1EvtBlkLo
+#define SB_PMIO_REG21 0x021 // AcpiPm1EvtBlki
+#define SB_PMIO_REG22 0x022 // AcpiPm1CntBlkLo
+#define SB_PMIO_REG23 0x023 // AcpiPm1CntBlki
+#define SB_PMIO_REG24 0x024 // AcpiPmTmrBlkLo
+#define SB_PMIO_REG25 0x025 // AcpiPmTmrBlki
+#define SB_PMIO_REG26 0x026 // CpuControlLo
+#define SB_PMIO_REG27 0x027 // CpuControli
+#define SB_PMIO_REG28 0x028 // AcpiGpe0BlkLo
+#define SB_PMIO_REG29 0x029 // AcpiGpe0Blki
+#define SB_PMIO_REG2A 0x02A // AcpiSmiCmdLo
+#define SB_PMIO_REG2B 0x02B // AcpiSmiCmdi
+#define SB_PMIO_REG2C 0x02C // AcpiPmaCntBlkLo
+#define SB_PMIO_REG2D 0x02D // AcpiPmaCntBlki
+#define SB_PMIO_REG2E 0x02E // AcpiSsCntBlkLo
+#define SB_PMIO_REG2F 0x02F // AcpiSsCntBlki
+#define SB_PMIO_REG30 0x030 // GEvtConfig0
+#define SB_PMIO_REG31 0x031 // GEvtConfig1
+#define SB_PMIO_REG32 0x032 // GPMConfig0
+#define SB_PMIO_REG33 0x033 // GPMConfig1
+#define SB_PMIO_REG34 0x034 // GPMConfig2
+#define SB_PMIO_REG35 0x035 // GPMConfig3
+#define SB_PMIO_REG36 0x036 // GEvtLevelConfig
+#define SB_PMIO_REG37 0x037 // GPMLevelConfig0
+#define SB_PMIO_REG38 0x038 // GPMLevelConfig1
+#define SB_PMIO_REG39 0x039 // GEvtStatus
+#define SB_PMIO_REG3A 0x03A // PMEStatus0
+#define SB_PMIO_REG3B 0x03B // PMEStatus1
+#define SB_PMIO_REG3C 0x03C // OtersConfig
+#define SB_PMIO_REG3E 0x03E // VRT_T1
+#define SB_PMIO_REG3F 0x03F // VRT_T2
+#define SB_PMIO_REG40 0x040 // Fan0DutyCycle
+#define SB_PMIO_REG41 0x041 // Fan0Control
+#define SB_PMIO_REG42 0x042 // Fan1DutyCycle
+#define SB_PMIO_REG43 0x043 // Reserved for internal use
+#define SB_PMIO_REG50 0x050 // PM_Enable
+#define SB_PMIO_REG51 0x051 // TPRESET1
+#define SB_PMIO_REG52 0x052 // TPRESET2
+#define SB_PMIO_REG53 0x053 // TESTENABLE
+#define SB_PMIO_REG54 0x054 // PWRBTTN_CLR
+#define SB_PMIO_REG55 0x055 // SoftPciRst
+#define SB_PMIO_REG56 0x056 // Reserved
+#define SB_PMIO_REG59 0x059 // Ac97Mask
+#define SB_PMIO_REG60 0x060 // Options_0
+#define SB_PMIO_REG61 0x061 // Options_1
+#define SB_PMIO_REG62 0x062 // Sadow_SCI
+#define SB_PMIO_REG63 0x063 // SwitcVoltageTime
+#define SB_PMIO_REG64 0x064 // SwitchGI_Time
+#define SB_PMIO_REG65 0x065 // UsbPMControl
+#define SB_PMIO_REG66 0x066 // MiscEnable66
+#define SB_PMIO_REG67 0x067 // MiscEnable67
+#define SB_PMIO_REG68 0x068 // MiscEnable68
+#define SB_PMIO_REG69 0x069 // WatcDogTimerControl
+#define SB_PMIO_REG6C 0x06C // WatcDogTimerBase0
+#define SB_PMIO_REG6D 0x06D // WatcDogTimerBase1
+#define SB_PMIO_REG6E 0x06E // WatcDogTimerBase2
+#define SB_PMIO_REG6F 0x06F // WatcDogTimerBase3
+#define SB_PMIO_REG70 0x070 // S_LdtStartTime
+#define SB_PMIO_REG71 0x071 // FidVidOption
+#define SB_PMIO_REG72 0x072 // Spare4
+#define SB_PMIO_REG73 0x073 // Spare5
+#define SB_PMIO_REG74 0x074 // PwrFailSadow
+#define SB_PMIO_REG75 0x075 // Tpreset1b
+#define SB_PMIO_REG76 0x076 // S0S3ToS5Enable0
+#define SB_PMIO_REG77 0x077 // S0S3ToS5Enable1
+#define SB_PMIO_REG78 0x078 // S0S3ToS5Enable2
+#define SB_PMIO_REG79 0x079 // S0S3ToS5Enable3
+#define SB_PMIO_REG7A 0x07A // NoStatusControl0
+#define SB_PMIO_REG7B 0x07B // NoStatusControl1
+#define SB_PMIO_REG7C 0x07C // MiscEnable7C
+#define SB_PMIO_REG80 0x080 // SMAF0
+#define SB_PMIO_REG81 0x081 // SMAF1
+#define SB_PMIO_REG82 0x082 // SMAF2
+#define SB_PMIO_REG83 0x083 // SMAF3
+#define SB_PMIO_REG84 0x084 // WakePinCntl
+#define SB_PMIO_REG85 0x085 // CF9Rst
+#define SB_PMIO_REG86 0x086 // ThermTrotCntl
+#define SB_PMIO_REG87 0x087 // LdtStpCmd
+#define SB_PMIO_REG88 0x088 // LdtStartTime
+#define SB_PMIO_REG89 0x089 // AgpStartTime
+#define SB_PMIO_REG8A 0x08A // LdtAgpTimeCntl
+#define SB_PMIO_REG8B 0x08B // StutterTime
+#define SB_PMIO_REG8C 0x08C // StpClkDlyTime
+#define SB_PMIO_REG8D 0x08D // AbPmeCntl
+#define SB_PMIO_REG8E 0x08E // FakeAsr
+#define SB_PMIO_REG8F 0x08F // FakeAsrEn
+#define SB_PMIO_REG90 0x090 // GEVENTOUT
+#define SB_PMIO_REG91 0x091 // GEVENTEnable
+#define SB_PMIO_REG92 0x092 // GEVENTIN
+#define SB_PMIO_REG95 0x095 // GPM98EN
+#define SB_PMIO_REG9A 0x09A // EnanceControl
+#define SB_PMIO_REG9E 0x09E // EnanceControl
+#define SB_PMIO_REG9F 0x09F // EnanceControl
+#define SB_PMIO_REGA0 0x0A0 // Programlo4RangeLo
+#define SB_PMIO_REGA1 0x0A1 // ProgramIo4Rangei
+#define SB_PMIO_REGA2 0x0A2 // Programlo5RangeLo
+#define SB_PMIO_REGA3 0x0A3 // ProgramIo5Rangei
+#define SB_PMIO_REGA4 0x0A4 // Programlo6RangeLo
+#define SB_PMIO_REGA5 0x0A5 // ProgramIo6Rangei
+#define SB_PMIO_REGA6 0x0A6 // Programlo7RangeLo
+#define SB_PMIO_REGA7 0x0A7 // ProgramIo7Rangei
+#define SB_PMIO_REGA8 0x0A8 // PIO7654Enable
+#define SB_PMIO_REGA9 0x0A9 // PIO7654Status
+#define SB_PMIO_REGB0 0x0B0
+#define SB_PMIO_REGB1 0x0B1
+#define SB_PMIO_REGB2 0x0B2 // MiscControl3
+#define SB_PMIO_REGB4 0x0B4 // HPET BAR
+#define SB_PMIO_REGB6 0x0B6
+#define SB_PMIO_REGB7 0x0B7
+#define SB_PMIO_REGBB 0x0BB // IMC_ACPI_Enable
+#define SB_PMIO_REGBC 0x0BC //
+#define SB_PMIO_REGBD 0x0BD //
+#define SB_PMIO_REGC9 0x0C9 // MultiK8Control
+#define SB_PMIO_REGCA 0x0CA //
+#define SB_PMIO_REGCB 0x0CB //
+#define SB_PMIO_REGCC 0x0CC //
+#define SB_PMIO_REGCD 0x0CD //
+#define SB_PMIO_REGD0 0x0D0 //
+#define SB_PMIO_REGD2 0x0D2 //
+#define SB_PMIO_REGD4 0x0D4 //
+#define SB_PMIO_REGD7 0x0D7 //
+
+
+#define SB_RTC_REG00 0x00 // Seconds - RW
+#define SB_RTC_REG01 0x01 // Seconds Alarm - RW
+#define SB_RTC_REG02 0x02 // Minutes - RW
+#define SB_RTC_REG03 0x03 // Minutes Alarm - RW
+#define SB_RTC_REG04 0x04 // ours - RW
+#define SB_RTC_REG05 0x05 // ours Alarm- RW
+#define SB_RTC_REG06 0x06 // Day of Week - RW
+#define SB_RTC_REG07 0x07 // Date of Mont - RW
+#define SB_RTC_REG08 0x08 // Mont - RW
+#define SB_RTC_REG09 0x09 // Year - RW
+#define SB_RTC_REG0A 0x0A // Register A - RW
+#define SB_RTC_REG0B 0x0B // Register B - RW
+#define SB_RTC_REG0C 0x0C // Register C - R
+#define SB_RTC_REG0D 0x0D // DateAlarm - RW
+#define SB_RTC_REG32 0x32 // AltCentury - RW
+#define SB_RTC_REG48 0x48 // Century - RW
+#define SB_RTC_REG50 0x50 // Extended RAM Address Port - RW
+#define SB_RTC_REG53 0x53 // Extended RAM Data Port - RW
+#define SB_RTC_REG7E 0x7E // RTC Time Clear - RW
+#define SB_RTC_REG7F 0x7F // RTC RAM Enable - RW
+
+#define B_ECMOS_REG00 0x00 // scratc-reg
+ //;BIT0=0 AsicDebug is enabled
+ //;BIT1=0 SLT S3 runs
+#define SB_ECMOS_REG01 0x01
+#define SB_ECMOS_REG02 0x02
+#define SB_ECMOS_REG03 0x03
+#define SB_ECMOS_REG04 0x04
+#define SB_ECMOS_REG05 0x05
+#define SB_ECMOS_REG06 0x06
+#define SB_ECMOS_REG07 0x07
+#define SB_ECMOS_REG08 0x08 // save 32BIT Pysical address of Config structure
+#define SB_ECMOS_REG09 0x09
+#define SB_ECMOS_REG0A 0x0A
+#define SB_ECMOS_REG0B 0x0B
+
+#define SB_ECMOS_REG0C 0x0C //;save MODULE_ID
+#define SB_ECMOS_REG0D 0x0D //;Reserve for NB
+
+#define SB_IOMAP_REG00 0x000 // Dma_C 0
+#define SB_IOMAP_REG02 0x002 // Dma_C 1
+#define SB_IOMAP_REG04 0x004 // Dma_C 2
+#define SB_IOMAP_REG06 0x006 // Dma_C 3
+#define SB_IOMAP_REG08 0x008 // Dma_Status
+#define SB_IOMAP_REG09 0x009 // Dma_WriteRest
+#define SB_IOMAP_REG0A 0x00A // Dma_WriteMask
+#define SB_IOMAP_REG0B 0x00B // Dma_WriteMode
+#define SB_IOMAP_REG0C 0x00C // Dma_Clear
+#define SB_IOMAP_REG0D 0x00D // Dma_MasterClr
+#define SB_IOMAP_REG0E 0x00E // Dma_ClrMask
+#define SB_IOMAP_REG0F 0x00F // Dma_AllMask
+#define SB_IOMAP_REG20 0x020 // IntrCntrlReg1
+#define SB_IOMAP_REG21 0x021 // IntrCntrlReg2
+#define SB_IOMAP_REG40 0x040 // TimerC0
+#define SB_IOMAP_REG41 0x041 // TimerC1
+#define SB_IOMAP_REG42 0x042 // TimerC2
+#define SB_IOMAP_REG43 0x043 // Tmr1CntrlWord
+#define SB_IOMAP_REG61 0x061 // Nmi_Status
+#define SB_IOMAP_REG70 0x070 // Nmi_Enable
+#define SB_IOMAP_REG71 0x071 // RtcDataPort
+#define SB_IOMAP_REG72 0x072 // AlternatRtcAddrPort
+#define SB_IOMAP_REG73 0x073 // AlternatRtcDataPort
+#define SB_IOMAP_REG80 0x080 // Dma_Page_Reserved0
+#define SB_IOMAP_REG81 0x081 // Dma_PageC2
+#define SB_IOMAP_REG82 0x082 // Dma_PageC3
+#define SB_IOMAP_REG83 0x083 // Dma_PageC1
+#define SB_IOMAP_REG84 0x084 // Dma_Page_Reserved1
+#define SB_IOMAP_REG85 0x085 // Dma_Page_Reserved2
+#define SB_IOMAP_REG86 0x086 // Dma_Page_Reserved3
+#define SB_IOMAP_REG87 0x087 // Dma_PageC0
+#define SB_IOMAP_REG88 0x088 // Dma_Page_Reserved4
+#define SB_IOMAP_REG89 0x089 // Dma_PageC6
+#define SB_IOMAP_REG8A 0x08A // Dma_PageC7
+#define SB_IOMAP_REG8B 0x08B // Dma_PageC5
+#define SB_IOMAP_REG8C 0x08C // Dma_Page_Reserved5
+#define SB_IOMAP_REG8D 0x08D // Dma_Page_Reserved6
+#define SB_IOMAP_REG8E 0x08E // Dma_Page_Reserved7
+#define SB_IOMAP_REG8F 0x08F // Dma_Refres
+#define SB_IOMAP_REG92 0x092 // FastInit
+#define SB_IOMAP_REGA0 0x0A0 // IntrCntrl2Reg1
+#define SB_IOMAP_REGA1 0x0A1 // IntrCntrl2Reg2
+#define SB_IOMAP_REGC0 0x0C0 // Dma2_C4Addr
+#define SB_IOMAP_REGC2 0x0C2 // Dma2_C4Cnt
+#define SB_IOMAP_REGC4 0x0C4 // Dma2_C5Addr
+#define SB_IOMAP_REGC6 0x0C6 // Dma2_C5Cnt
+#define SB_IOMAP_REGC8 0x0C8 // Dma2_C6Addr
+#define SB_IOMAP_REGCA 0x0CA // Dma2_C6Cnt
+#define SB_IOMAP_REGCC 0x0CC // Dma2_C7Addr
+#define SB_IOMAP_REGCE 0x0CE // Dma2_C7Cnt
+#define SB_IOMAP_REGD0 0x0D0 // Dma_Status
+#define SB_IOMAP_REGD2 0x0D2 // Dma_WriteRest
+#define SB_IOMAP_REGD4 0x0D4 // Dma_WriteMask
+#define SB_IOMAP_REGD6 0x0D6 // Dma_WriteMode
+#define SB_IOMAP_REGD8 0x0D8 // Dma_Clear
+#define SB_IOMAP_REGDA 0x0DA // Dma_Clear
+#define SB_IOMAP_REGDC 0x0DC // Dma_ClrMask
+#define SB_IOMAP_REGDE 0x0DE // Dma_ClrMask
+#define SB_IOMAP_REGF0 0x0F0 // NCP_Error
+#define SB_IOMAP_REG40B 0x040B // DMA1_Extend
+#define SB_IOMAP_REG4D0 0x04D0 // IntrEdgeControl
+#define SB_IOMAP_REG4D6 0x04D6 // DMA2_Extend
+#define SB_IOMAP_REGC00 0x0C00 // Pci_Intr_Index
+#define SB_IOMAP_REGC01 0x0C01 // Pci_Intr_Data
+#define SB_IOMAP_REGC14 0x0C14 // Pci_Error
+#define SB_IOMAP_REGC50 0x0C50 // CMIndex
+#define SB_IOMAP_REGC51 0x0C51 // CMData
+#define SB_IOMAP_REGC52 0x0C52 // GpmPort
+#define SB_IOMAP_REGC6F 0x0C6F // Isa_Misc
+#define SB_IOMAP_REGCD0 0x0CD0 // PMio2_Index
+#define SB_IOMAP_REGCD1 0x0CD1 // PMio2_Data
+#define SB_IOMAP_REGCD4 0x0CD4 // BIOSRAM_Index
+#define SB_IOMAP_REGCD5 0x0CD5 // BIOSRAM_Data
+#define SB_IOMAP_REGCD6 0x0CD6 // PM_Index
+#define SB_IOMAP_REGCD7 0x0CD7 // PM_Data
+#define SB_IOMAP_REGCF9 0x0CF9 // CF9Rst reg
+
+
+#define SB_CM_REG02 0x002 // TempStatus (via SB_IOMAP_REGC50)
+#define SB_CM_REG03 0x003 // TempInterrupt (via SB_IOMAP_REGC50)
+
+#define SB_SATA_REG00 0x000 // Vendor ID - R- 16 bits
+#define SB_SATA_REG02 0x002 // Device ID - RW -16 bits
+#define SB_SATA_REG04 0x004 // PCI Command - RW - 16 bits
+#define SB_SATA_REG06 0x006 // PCI Status - RW - 16 bits
+#define SB_SATA_REG08 0x008 // Revision ID/PCI Class Code - R - 32 bits - Offset: 08
+#define SB_SATA_REG0C 0x00C // Cace Line Size - R/W - 8bits
+#define SB_SATA_REG0D 0x00D // Latency Timer - RW - 8 bits
+#define SB_SATA_REG0E 0x00E // eader Type - R - 8 bits
+#define SB_SATA_REG0F 0x00F // BIST - R - 8 bits
+#define SB_SATA_REG10 0x010 // Base Address Register 0 - RW - 32 bits
+#define SB_SATA_REG14 0x014 // Base Address Register 1 - RW- 32 bits
+#define SB_SATA_REG18 0x018 // Base Address Register 2 - RW - 32 bits
+#define SB_SATA_REG1C 0x01C // Base Address Register 3 - RW - 32 bits
+#define SB_SATA_REG20 0x020 // Base Address Register 4 - RW - 32 bits
+#define SB_SATA_REG24 0x024 // Base Address Register 5 - RW - 32 bits
+#define SB_SATA_REG2C 0x02C // Subsystem Vendor ID - R - 16 bits
+#define SB_SATA_REG2D 0x02D // Subsystem ID - R - 16 bits
+#define SB_SATA_REG30 0x030 // Expansion ROM Base Address - 32 bits
+#define SB_SATA_REG34 0x034 // Capabilities Pointer - R - 32 bits
+#define SB_SATA_REG3C 0x03C // Interrupt Line - RW - 8 bits
+#define SB_SATA_REG3D 0x03D // Interrupt Pin - R - 8 bits
+#define SB_SATA_REG3E 0x03E // Min Grant - R - 8 bits
+#define SB_SATA_REG3F 0x03F // Max Latency - R - 8 bits
+#define SB_SATA_REG40 0x040 // Configuration - RW - 32 bits
+#define SB_SATA_REG44 0x044 // Software Data Register - RW - 32 bits
+#define SB_SATA_REG48 0x048
+#define SB_SATA_REG50 0x050 // Message Capability - R - 16 bits
+#define SB_SATA_REG52 0x052 // Message Control - R/W - 16 bits
+#define SB_SATA_REG54 0x054 // Message Address - R/W - 32 bits
+#define SB_SATA_REG58 0x058 // Message Data - R/W - 16 bits
+#define SB_SATA_REG5C 0x05C // RAMBIST Control Register - R/W - 8 bits
+#define SB_SATA_REG5D 0x05D // RAMBIST Status0 Register - R - 8 bits
+#define SB_SATA_REG5E 0x05E // RAMBIST Status1 Register - R - 8 bits
+#define SB_SATA_REG60 0x060 // Power Management Capabilities - R - 32 bits
+#define SB_SATA_REG64 0x064 // Power Management Control + Status - RW - 32 bits
+#define SB_SATA_REG68 0x068 // MSI Program Weigt - R/W - 8 bits
+#define SB_SATA_REG69 0x069 // PCI Burst Timer - R/W - 8 bits
+#define SB_SATA_REG70 0x070 // PCI Bus Master - IDE0 - RW - 32 bits
+#define SB_SATA_REG74 0x074 // PRD Table Address - IDE0 - RW - 32 bits
+#define SB_SATA_REG78 0x078 // PCI Bus Master - IDE1 - RW - 32 bits
+#define SB_SATA_REG7C 0x07C // PRD Table Address - IDE1 - RW - 32 bits
+#define SB_SATA_REG80 0x080 // Data Transfer Mode - IDE0 - RW - 32 bits
+#define SB_SATA_REG84 0x084 // Data Transfer Mode - IDE1 - RW - 32 bits
+#define SB_SATA_REG86 0x086 // PY Global Control
+#define SB_SATA_REG87 0x087
+#define SB_SATA_REG88 0x088 // PHY Port0 Control - Port0 PY fine tune(0:23)
+#define SB_SATA_REG8A 0x08A
+#define SB_SATA_REG8C 0x08C // PHY Port1 Control - Port0 PY fine tune(0:23)
+#define SB_SATA_REG8E 0x08E
+#define SB_SATA_REG90 0x090 // PHY Port2 Control - Port0 PY fine tune(0:23)
+#define SB_SATA_REG92 0x092
+#define SB_SATA_REG94 0x094 // PHY Port3 Control - Port0 PY fine tune(0:23)
+#define SB_SATA_REG96 0x096
+#define SB_SATA_REG98 0x098 // EEPROM Memory Address - Command + Status - RW - 32 bits
+#define SB_SATA_REG9C 0x09C // EEPROM Memory Data - RW - 32 bits
+#define SB_SATA_REGA0 0x0A0 //
+#define SB_SATA_REGA4 0x0A4 //
+#define SB_SATA_REGA5 0x0A5 //;
+#define SB_SATA_REGA8 0x0A8 //
+#define SB_SATA_REGAD 0x0AD //;
+#define SB_SATA_REGB0 0x0B0 // IDE1 Task File Configuration + Status - RW - 32 bits
+#define SB_SATA_REGB5 0x0B5 //;
+#define SB_SATA_REGBD 0x0BD //;
+#define SB_SATA_REGC0 0x0C0 // BA5 Indirect Address - RW - 32 bits
+#define SB_SATA_REGC4 0x0C4 // BA5 Indirect Access - RW - 32 bits
+
+#define SB_SATA_BAR5_REG00 0x000 // PCI Bus Master - IDE0 - RW - 32 bits
+#define SB_SATA_BAR5_REG04 0x004 // PRD Table Address - IDE0 - RW - 32 bits
+#define SB_SATA_BAR5_REG08 0x008 // PCI Bus Master - IDE1 - RW - 32 bits
+#define SB_SATA_BAR5_REG0C 0x00C // PRD Table Address - IDE1 - RW - 32 bits
+#define SB_SATA_BAR5_REG10 0x010 // PCI Bus Master2 - IDE0 - RW - 32 bits
+#define SB_SATA_BAR5_REG18 0x018 // PCI Bus Master2 - IDE1 - RW - 32 bits
+#define SB_SATA_BAR5_REG20 0x020 // PRD Address - IDE0 - RW - 32 bits
+#define SB_SATA_BAR5_REG24 0x024 // PCI Bus Master Byte Count - IDE0- RW - 32 bits
+#define SB_SATA_BAR5_REG28 0x028 // PRD Address - IDE1 - RW - 32 bits
+#define SB_SATA_BAR5_REG2C 0x02C // PCI Bus Master Byte Count - IDE1 - RW - 32 bits
+#define SB_SATA_BAR5_REG40 0x040 // FIFO Valid Byte Count and Control - IDE0 - RW - 32 bits
+#define SB_SATA_BAR5_REG44 0x044 // FIFO Valid Byte Count and Control - IDE1 - RW - 32 bits
+#define SB_SATA_BAR5_REG48 0x048 // System Configuration Status - Command - RW - 32 bits
+#define SB_SATA_BAR5_REG4C 0x04C // System Software Data Register - RW - 32 bits
+#define SB_SATA_BAR5_REG50 0x050 // FLAS Memory Address - Command + Status - RW - 32 bits
+#define SB_SATA_BAR5_REG54 0x054 // FLAS Memory Data - RW - 32 bits
+#define SB_SATA_BAR5_REG58 0x058 // EEPROM Memory Address - Command + Status - RW - 32 bits
+#define SB_SATA_BAR5_REG5C 0x05C // EEPROM Memory Data - RW - 32 bits
+#define SB_SATA_BAR5_REG60 0x060 // FIFO Port - IDE0 - RW - 32 bits
+#define SB_SATA_BAR5_REG68 0x068 // FIFO Pointers1- IDE0 - RW - 32 bits
+#define SB_SATA_BAR5_REG6C 0x06C // FIFO Pointers2- IDE0 - RW - 32 bits
+#define SB_SATA_BAR5_REG70 0x070 // FIFO Port - IDE1- RW - 32 bits
+#define SB_SATA_BAR5_REG78 0x078 // FIFO Pointers1- IDE1- RW - 32 bits
+#define SB_SATA_BAR5_REG7C 0x07C // FIFO Pointers2- IDE1- RW - 32 bits
+#define SB_SATA_BAR5_REG80 0x080 // IDE0 Task File Register 0- RW - 32 bits
+#define SB_SATA_BAR5_REG84 0x084 // IDE0 Task File Register 1- RW - 32 bits
+#define SB_SATA_BAR5_REG88 0x088 // IDE0 Task File Register 2- RW - 32 bits
+#define SB_SATA_BAR5_REG8C 0x08C // IDE0 Read Aead Data - RW - 32 bits
+#define SB_SATA_BAR5_REG90 0x090 // IDE0 Task File Register 0 - Command Buffering - RW - 32 bits
+#define SB_SATA_BAR5_REG94 0x094 // IDE0 Task File Register 1 - Command Buffering - RW - 32 bits
+#define SB_SATA_BAR5_REG9C 0x09C // IDE0 Virtual DMA/PIO Read Aead Byte Count - RW - 32 bits
+#define SB_SATA_BAR5_REGA0 0x0A0 // IDE0 Task File Configuration + Status - RW - 32 bits
+#define SB_SATA_BAR5_REGB4 0x0B4 // Data Transfer Mode -IDE0 - RW - 32 bits
+#define SB_SATA_BAR5_REGC0 0x0C0 // IDE1 Task File Register 0 - RW - 32 bits
+#define SB_SATA_BAR5_REGC4 0x0C4 // IDE1 Task File Register 1 - RW - 32 bits
+#define SB_SATA_BAR5_REGC8 0x0C8 // IDE1 Task File Register 2 - RW - 32 bits
+#define SB_SATA_BAR5_REGCC 0x0CC // Read/Write Aead Data - RW - 32 bits
+#define SB_SATA_BAR5_REGD0 0x0D0 // IDE1 Task File Register 0 - Command Buffering - RW - 32 bits
+#define SB_SATA_BAR5_REGD4 0x0D4 // IDE1 Task File Register 1 - Command Buffering - RW - 32 bits
+#define SB_SATA_BAR5_REGDC 0x0DC // IDE1 Virtual DMA/PIO Read Aead Byte Count - RW - 32 bits
+#define SB_SATA_BAR5_REGE0 0x0E0 // IDE1 Task File Configuration + Status - RW - 32 bits
+#define SB_SATA_BAR5_REGF4 0x0F4 // Data Transfer Mode - IDE1 - RW - 32 bits
+#define SB_SATA_BAR5_REGF8 0x0F8 // PORT Configuration
+#define SB_SATA_BAR5_REGFC 0x0FC
+
+#define SB_SATA_BAR5_REG100 0x0100 //;Serial ATA SControl - RW - 32 bits - [Offset: 100h (channel 1) / 180
+#define SB_SATA_BAR5_REG104 0x0104 //;Serial ATA Sstatus - RW - 32 bits - [Offset: 104h (channel 1) / 184h (cannel
+#define SB_SATA_BAR5_REG108 0x0108 //;Serial ATA Serror - RW - 32 bits - [Offset: 108h (channel 1) / 188h (cannel
+#define SB_SATA_BAR5_REG10C 0x010C //;Serial ATA Sdevice - RW - 32 bits - [Offset: 10Ch (channel 1) / 18Ch (cannel
+#define SB_SATA_BAR5_REG110 0x0110 // Port-N Interrupt Status
+#define SB_SATA_BAR5_REG144 0x0144 //;Serial ATA PY Configuration - RW - 32 bits
+#define SB_SATA_BAR5_REG148 0x0148 //;SIEN - RW - 32 bits - [Offset: 148 (channel 1) / 1C8 (cannel 2)]
+#define SB_SATA_BAR5_REG14C 0x014C //;SFISCfg - RW - 32 bits - [Offset: 14C (channel 1) / 1CC (cannel 2)]
+#define SB_SATA_BAR5_REG120 0x0120 // Port Task Fike Data
+#define SB_SATA_BAR5_REG128 0x0128 // Port Serial ATA Status
+#define SB_SATA_BAR5_REG12C 0x012C // Port Serial ATA Control
+
+#define SB_SATA_BAR5_REG130 0x0130
+#define SB_SATA_BAR5_REG1B0 0x01B0
+#define SB_SATA_BAR5_REG230 0x0230
+#define SB_SATA_BAR5_REG2B0 0x02B0
+
+#define SB_FC_REG00 0x00 // Device/Vendor ID - R
+#define SB_FC_REG04 0x04 // Command - RW
+#define SB_FC_REG10 0x10 // BAR
+
+#define SB_FC_MMIO_REG70 0x070
+#define SB_FC_MMIO_REG200 0x200
+
+#define SB_OHCI_REG00 0x00 // Device/Vendor ID - R
+#define SB_OHCI_REG04 0x04 // Command - RW
+#define SB_OHCI_REG06 0x06 // Status - R
+#define SB_OHCI_REG08 0x08 // Revision ID/Class Code - R
+#define SB_OHCI_REG0C 0x0C // Miscellaneous - RW
+#define SB_OHCI_REG10 0x10 // Bar_OCI - RW
+#define SB_OHCI_REG2C 0x2C // Subsystem Vendor ID/ Subsystem ID - RW
+#define SB_OHCI_REG34 0x34 // Capability Pointer - R
+#define SB_OHCI_REG3C 0x3C // Interrupt Line - RW
+#define SB_OHCI_REG3D 0x3D // Interrupt Line - RW
+
+#define SB_OHCI_REG40 0x40 // Config Timers - RW
+#define SB_OHCI_REG4C 0x4C // MSI Weigt - RW
+#define SB_OHCI_REG50 0x50 // ATI Misc Control - RW
+#define SB_OHCI_REG51 0x51
+#define SB_OHCI_REG58 0x58 // Over Current Control - RW
+#define SB_OHCI_REG5C 0x5C // Over Current Control - RW
+#define SB_OHCI_REG60 0x60 // Serial Bus Release Number - R
+#define SB_OHCI_REG68 0x68 // Over Current Enable - RW
+#define SB_OHCI_REGD0 0x0D0 // MSI Control - RW
+#define SB_OHCI_REGD4 0x0D4 // MSI Address - RW
+#define SB_OHCI_REGD8 0x0D8 // MSI Data - RW
+#define SB_OHCI_BAR_REG00 0x00 // cRevision - R
+#define SB_OHCI_BAR_REG04 0x04 // cControl
+#define SB_OHCI_BAR_REG08 0x08 // cCommandStatus
+#define SB_OHCI_BAR_REG0C 0x0C // cInterruptStatus RW
+#define SB_OHCI_BAR_REG10 0x10 // cInterruptEnable
+#define SB_OHCI_BAR_REG14 0x14 // cInterruptDisable
+#define SB_OHCI_BAR_REG18 0x18 // HcCCA
+#define SB_OHCI_BAR_REG1C 0x1C // cPeriodCurrentED
+#define SB_OHCI_BAR_REG20 0x20 // HcControleadED
+#define SB_OHCI_BAR_REG24 0x24 // cControlCurrentED RW
+#define SB_OHCI_BAR_REG28 0x28 // HcBulkeadED
+#define SB_OHCI_BAR_REG2C 0x2C // cBulkCurrentED- RW
+#define SB_OHCI_BAR_REG30 0x30 // HcDoneead
+#define SB_OHCI_BAR_REG34 0x34 // cFmInterval
+#define SB_OHCI_BAR_REG38 0x38 // cFmRemaining
+#define SB_OHCI_BAR_REG3C 0x3C // cFmNumber
+#define SB_OHCI_BAR_REG40 0x40 // cPeriodicStart
+#define SB_OHCI_BAR_REG44 0x44 // HcLSThresold
+#define SB_OHCI_BAR_REG48 0x48 // HcRDescriptorA
+#define SB_OHCI_BAR_REG4C 0x4C // HcRDescriptorB
+#define SB_OHCI_BAR_REG50 0x50 // HcRStatus
+#define SB_OHCI_BAR_REG160 0x160
+
+#define SB_EHCI_REG00 0x00 // DEVICE/VENDOR ID - R
+#define SB_EHCI_REG04 0x04 // Command - RW
+#define SB_EHCI_REG06 0x06 // Status - R
+#define SB_EHCI_REG08 0x08 // Revision ID/Class Code - R
+#define SB_EHCI_REG0C 0x0C // Miscellaneous - RW
+#define SB_EHCI_REG10 0x10 // BAR - RW
+#define SB_EHCI_REG2C 0x2C // Subsystem ID/Subsystem Vendor ID - RW
+#define SB_EHCI_REG34 0x34 // Capability Pointer - R
+#define SB_EHCI_REG3C 0x3C // Interrupt Line - RW
+#define SB_EHCI_REG3D 0x3D // Interrupt Line - RW
+#define SB_EHCI_REG40 0x40 // Config Timers - RW
+#define SB_EHCI_REG4C 0x4C // MSI Weigt - RW
+#define SB_EHCI_REG50 0x50 // ATI Misc Control - RW
+#define SB_EHCI_REG54 0x54 // ATI Misc Control - RW
+#define SB_EHCI_REG58 0x58 // Over Current Control - R
+#define SB_EHCI_REG60 0x60 // SBRN - R
+#define SB_EHCI_REG61 0x61 // FLADJ - RW
+#define SB_EHCI_REG62 0x62 // PORTWAKECAP - RW
+#define SB_EHCI_REGD0 0x0D0 // MSI Control - RW
+#define SB_EHCI_REGD4 0x0D4 // MSI Address - RW
+#define SB_EHCI_REGD8 0x0D8 // MSI Data - RW
+#define SB_EHCI_REGDC 0x0DC // PME Control - RW
+#define SB_EHCI_REGE0 0x0E0 // PME Data / Status - RW
+#define SB_EHCI_BAR_REG00 0x00 // CAPLENGT - R
+#define SB_EHCI_BAR_REG02 0x002 // CIVERSION- R
+#define SB_EHCI_BAR_REG04 0x004 // CSPARAMS - R
+#define SB_EHCI_BAR_REG08 0x008 // CCPARAMS - R
+#define SB_EHCI_BAR_REG0C 0x00C // CSP-PORTROUTE - R
+#define SB_EHCI_BAR_REG20 0x020 // USBCMD - RW - 32 bits
+#define SB_EHCI_BAR_REG24 0x024 // USBSTS - RW - 32 bits
+#define SB_EHCI_BAR_REG28 0x028 // USBINTR -RW - 32 bits
+#define SB_EHCI_BAR_REG2C 0x02C // FRINDEX -RW - 32 bits
+#define SB_EHCI_BAR_REG30 0x030 // CTRLDSSEGMENT -RW - 32 bits
+#define SB_EHCI_BAR_REG34 0x034 // PERIODICLISTBASE -RW - 32 bits
+#define SB_EHCI_BAR_REG38 0x038 // ASYNCLISTADDR -RW - 32 bits
+#define SB_EHCI_BAR_REG60 0x060 // CONFIGFLAG -RW - 32 bits
+#define SB_EHCI_BAR_REG64 0x064 // PORTSC(1-N_PORTS) -RW - 32 bits
+#define SB_EHCI_BAR_REG84 0x084 // Packet Buffer Thresold Values - RW - 32 bits
+#define SB_EHCI_BAR_REG88 0x088 // Packet Buffer Dept Value - RW - 32 bits
+#define SB_EHCI_BAR_REG94 0x094 // UTMI Control and Status - RW - 32 bits
+#define SB_EHCI_BAR_REG98 0x098 // Bist Control - RW - 32 bits
+#define SB_EHCI_BAR_REG9C 0x09C // ATI EOR Control - RW - 32 bits
+#define SB_EHCI_BAR_REGA4 0x0A4 // USB IN/OUT FIFO Thresold Setting
+#define SB_EHCI_BAR_REGBC 0x0BC // ECI misc Setting
+#define SB_EHCI_BAR_REGC0 0x0C0 // USB PHY Auto Calibration Setting
+
+#define SB_SMBUS_REG00 0x000 //;VendorID - R
+#define SB_SMBUS_REG02 0x002 //;DeviceID - R
+#define SB_SMBUS_REG04 0x004 // Command- RW
+#define SB_SMBUS_REG05 0x005 // Command- RW
+#define SB_SMBUS_REG06 0x006 // STATUS- RW
+#define SB_SMBUS_REG08 0x008 // Revision ID/Class Code- R
+#define SB_SMBUS_REG0A 0x00A //;
+#define SB_SMBUS_REG0B 0x00B //;
+#define SB_SMBUS_REG0C 0x00C // Cace Line Size- R
+#define SB_SMBUS_REG0D 0x00D // Latency Timer- R
+#define SB_SMBUS_REG0E 0x00E // eader Type- R
+#define SB_SMBUS_REG0F 0x00F // BIST- R
+#define SB_SMBUS_REG10 0x010 // Base Address 0- R
+#define SB_SMBUS_REG11 0x011 //;
+#define SB_SMBUS_REG12 0x012 //;
+#define SB_SMBUS_REG13 0x013 //;
+#define SB_SMBUS_REG14 0x014 // Base Address 1- R
+#define SB_SMBUS_REG18 0x018 // Base Address 2- R
+#define SB_SMBUS_REG1C 0x01C // Base Address 3- R
+#define SB_SMBUS_REG20 0x020 // Base Address 4- R
+#define SB_SMBUS_REG24 0x024 // Base Address 5- R
+#define SB_SMBUS_REG28 0x028 // Cardbus CIS Pointer- R
+#define SB_SMBUS_REG2C 0x02C // Subsystem Vendor ID- W
+#define SB_SMBUS_REG2E 0x02E // Subsystem ID- W
+#define SB_SMBUS_REG30 0x030 // Expansion ROM Base Address - R
+#define SB_SMBUS_REG34 0x034 // Capability Pointer - R
+#define SB_SMBUS_REG38 0x038
+#define SB_SMBUS_REG3C 0x03C // Interrupt Line - R
+#define SB_SMBUS_REG3D 0x03D // Interrupt Pin - R
+#define SB_SMBUS_REG3E 0x03E // Min_Gnt - R
+#define SB_SMBUS_REG3F 0x03F // Max_Lat - R
+#define SB_SMBUS_REG40 0x040 // PCI Control- RW
+#define SB_SMBUS_REG41 0x041 // MiscFunction- RW
+#define SB_SMBUS_REG42 0x042 // DmaLimit- RW
+#define SB_SMBUS_REG43 0x043 // DmaEnanceEnable RW
+#define SB_SMBUS_REG48 0x048 // ISA Address Decode Control Register #1- RW
+#define SB_SMBUS_REG49 0x049 // ISA Address Decode Control Register #2- RW
+#define SB_SMBUS_REG4A 0x04A // Scratc Pad- RW
+#define SB_SMBUS_REG50 0x050 // PciGpioOutControl- RW
+#define SB_SMBUS_REG54 0x054 // PciGpioConfig- RW
+#define SB_SMBUS_REG58 0x058 // ASFSMBusIoBase
+#define SB_SMBUS_REG59 0x059 //;
+#define SB_SMBUS_REG5C 0x05C // Smart Power Control1
+#define SB_SMBUS_REG60 0x060 // MiscEnable- RW
+#define SB_SMBUS_REG64 0x064 // Features Enable- RW
+#define SB_SMBUS_REG68 0x068 // UsbEnable - RW
+#define SB_SMBUS_REG6C 0x06C // TestMode- RW
+#define SB_SMBUS_REG70 0x070 // RunTimeTest- R
+#define SB_SMBUS_REG74 0x074 // IoApic_Conf- RW
+#define SB_SMBUS_REG78 0x078 // IoAddrEnable - R/W
+#define SB_SMBUS_REG79 0x079 //;
+#define SB_SMBUS_REG7C 0x07C // RTC Control ;VSJ-2005-06-16
+#define SB_SMBUS_REG80 0x080 // GPIO_Out_Cntrl - RW
+#define SB_SMBUS_REG81 0x081 // GPIO_Status - R
+#define SB_SMBUS_REG90 0x090 // Smbus Base Address - R
+#define SB_SMBUS_REG94 0x094 // Reserved - R
+#define SB_SMBUS_REG98 0x098 //
+#define SB_SMBUS_REGA0 0x0A0 // MoreGPIOIn +C R
+#define SB_SMBUS_REGA4 0x0A4 // MoreGPIOIn +C R
+#define SB_SMBUS_REGA8 0x0A8 // GPIOControl +C RW
+#define SB_SMBUS_REGAC 0x0AC // MiscUsbEt - RW
+#define SB_SMBUS_REGAD 0x0AD // MiscSata
+#define SB_SMBUS_REGAE 0x0AE
+#define SB_SMBUS_REGAF 0x0AF // SataIntMap - RW
+#define SB_SMBUS_REGB0 0x0B0 // MSI Mapping Capability - R
+#define SB_SMBUS_REGB4 0x0B4 //HPET BASE Address
+#define SB_SMBUS_REGBC 0x0BC // PciIntGpio - RW
+#define SB_SMBUS_REGBE 0x0BE // UsbIntMap - RW
+#define SB_SMBUS_REGC0 0x0C0 // IokHiDrvSt - RW
+#define SB_SMBUS_REGD0 0x0D0 //
+#define SB_SMBUS_REGD2 0x0D2 // I2CbusConfig - RW
+#define SB_SMBUS_REGD3 0x0D3 // I2CCommand - RW
+#define SB_SMBUS_REGD4 0x0D4 // I2CSadow1- RW
+#define SB_SMBUS_REGD5 0x0D5 // I2Csadow2- RW
+#define SB_SMBUS_REGD6 0x0D6 // I2CBusRevision - RW
+#define SB_SMBUS_REGE0 0x0E0 // MSI_Weigt
+#define SB_SMBUS_REGE1 0x0E1 // MSI_Weigt
+#define SB_SMBUS_REGF0 0x0F0 // AB_REG_BAR - RW
+#define SB_SMBUS_REGF1 0x0F1
+#define SB_SMBUS_REGF4 0x0F4 // WakeIoAddr- RW
+#define SB_SMBUS_REGF8 0x0F8 // ExtendedAddrPort- RW
+#define SB_SMBUS_REGFC 0x0FC // ExtendedDataPort- RW
+
+
+#define SB_IDE_REG00 0x00 // Vendor ID
+#define SB_IDE_REG02 0x02 // Device ID
+#define SB_IDE_REG04 0x04 // Command
+#define SB_IDE_REG06 0x06 // Status
+#define SB_IDE_REG08 0x08 // Revision ID/Class Code
+#define SB_IDE_REG09 0x09 // Class Code
+#define SB_IDE_REG0A 0x0A
+#define SB_IDE_REG0C 0x0C // Cace Link Size
+#define SB_IDE_REG0D 0x0D // Master Latency Timer
+#define SB_IDE_REG0E 0x0E // eader Type
+#define SB_IDE_REG0F 0x0F // BIST Mode Type
+#define SB_IDE_REG10 0x10 // Base Address 0
+#define SB_IDE_REG14 0x14 // Base Address 1
+#define SB_IDE_REG18 0x18 // Base Address 2
+#define SB_IDE_REG1C 0x1C // Base Address 3
+#define SB_IDE_REG20 0x20 // Bus Master Interface Base Address
+#define SB_IDE_REG2C 0x2C // Subsystem ID and Subsystem Vendor ID
+#define SB_IDE_REG34 0x34 // MSI Capabilities Pointer
+#define SB_IDE_REG3C 0x3C // Interrupt Line
+#define SB_IDE_REG3D 0x3D // Interrupt Pin
+#define SB_IDE_REG3E 0x3E // Min_gnt
+#define SB_IDE_REG3F 0x3F // Max_latency
+#define SB_IDE_REG40 0x40 // IDE PIO Timing
+#define SB_IDE_REG44 0x44 // IDE Legacy DMA (Multi-words DMA) Timing Modes
+#define SB_IDE_REG48 0x48 // IDE PIO Control
+#define SB_IDE_REG4A 0x4A // IDE PIO Mode
+#define SB_IDE_REG4C 0x4C // IDE Status
+#define SB_IDE_REG54 0x54 // IDE Ultra DMAControl
+#define SB_IDE_REG55 0x55 // IDE Ultra DMA Status
+#define SB_IDE_REG56 0x56 // IDE Ultra DMA Mode
+#define SB_IDE_REG60 0x60 // IDE PCI Retry Timing Counter
+#define SB_IDE_REG61 0x61 // PCI Error Control
+#define SB_IDE_REG62 0x62 // IDE Internal Control
+#define SB_IDE_REG63 0x63 // IDE Internal Control
+#define SB_IDE_REG64 0x64 // IDE PLL Control
+#define SB_IDE_REG68 0x68 // IDE MSI Programmable Weigt
+#define SB_IDE_REG6C 0x6C // IDE Dynamic Clocking
+#define SB_IDE_REG70 0x70 // IDE MSI Control
+#define SB_IDE_REG74 0x74 // IDE MSI Address Register
+#define SB_IDE_REG78 0x78 // IDE MSI Data Register
+
+
+#define SB_AZ_REG00 0x00 // Vendor ID - R
+#define SB_AZ_REG02 0x02 // Device ID - R/W
+#define SB_AZ_REG04 0x04 // PCI Command
+#define SB_AZ_REG06 0x06 // PCI Status - R/W
+#define SB_AZ_REG08 0x08 // Revision ID
+#define SB_AZ_REG09 0x09 // Programming Interface
+#define SB_AZ_REG0A 0x0A // Sub Class Code
+#define SB_AZ_REG0B 0x0B // Base Class Code
+#define SB_AZ_REG0C 0x0C // Cace Line Size - R/W
+#define SB_AZ_REG0D 0x0D // Latency Timer
+#define SB_AZ_REG0E 0x0E // eader Type
+#define SB_AZ_REG0F 0x0F // BIST
+#define SB_AZ_REG10 0x10 // Lower Base Address Register
+#define SB_AZ_REG14 0x14 // Upper Base Address Register
+#define SB_AZ_REG2C 0x2C // Subsystem Vendor ID
+#define SB_AZ_REG2D 0x2D // Subsystem ID
+#define SB_AZ_REG34 0x34 // Capabilities Pointer
+#define SB_AZ_REG3C 0x3C // Interrupt Line
+#define SB_AZ_REG3D 0x3D // Interrupt Pin
+#define SB_AZ_REG3E 0x3E // Minimum Grant
+#define SB_AZ_REG3F 0x3F // Maximum Latency
+#define SB_AZ_REG40 0x40 // Misc Control 1
+#define SB_AZ_REG42 0x42 // Misc Control 2 Register
+#define SB_AZ_REG43 0x43 // Misc Control 3 Register
+#define SB_AZ_REG44 0x44 // Interrupt Pin Control Register
+#define SB_AZ_REG46 0x46 // Debug Control Register
+#define SB_AZ_REG4C 0x4C
+#define SB_AZ_REG50 0x50 // Power Management Capability ID
+#define SB_AZ_REG52 0x52 // Power Management Capabilities
+#define SB_AZ_REG54 0x54 // Power Management Control/Status
+#define SB_AZ_REG60 0x60 // MSI Capability ID
+#define SB_AZ_REG62 0x62 // MSI Message Control
+#define SB_AZ_REG64 0x64 // MSI Message Lower Address
+#define SB_AZ_REG68 0x68 // MSI Message Upper Address
+#define SB_AZ_REG6C 0x6C // MSI Message Data
+
+#define SB_AZ_BAR_REG00 0x00 // Global Capabilities - R
+#define SB_AZ_BAR_REG02 0x02 // Minor Version - R
+#define SB_AZ_BAR_REG03 0x03 // Major Version - R
+#define SB_AZ_BAR_REG04 0x04 // Output Payload Capability - R
+#define SB_AZ_BAR_REG06 0x06 // Input Payload Capability - R
+#define SB_AZ_BAR_REG08 0x08 // Global Control - R/W
+#define SB_AZ_BAR_REG0C 0x0C // Wake Enable - R/W
+#define SB_AZ_BAR_REG0E 0x0E // State Cange Status - R/W
+#define SB_AZ_BAR_REG10 0x10 // Global Status - R/W
+#define SB_AZ_BAR_REG18 0x18 // Output Stream Payload Capability - R
+#define SB_AZ_BAR_REG1A 0x1A // Input Stream Payload Capability - R
+#define SB_AZ_BAR_REG20 0x20 // Interrupt Control - R/W
+#define SB_AZ_BAR_REG24 0x24 // Interrupt Status - R/W
+#define SB_AZ_BAR_REG30 0x30 // Wall Clock Counter - R
+#define SB_AZ_BAR_REG38 0x38 // Stream Syncronization - R/W
+#define SB_AZ_BAR_REG40 0x40 // CORB Lower Base Address - R/W
+#define SB_AZ_BAR_REG44 0x44 // CORB Upper Base Address - RW
+#define SB_AZ_BAR_REG48 0x48 // CORB Write Pointer - R/W
+#define SB_AZ_BAR_REG4A 0x4A // CORB Read Pointer - R/W
+#define SB_AZ_BAR_REG4C 0x4C // CORB Control - R/W
+#define SB_AZ_BAR_REG4D 0x4D // CORB Status - R/W
+#define SB_AZ_BAR_REG4E 0x4E // CORB Size - R/W
+#define SB_AZ_BAR_REG50 0x50 // RIRB Lower Base Address - RW
+#define SB_AZ_BAR_REG54 0x54 // RIRB Upper Address - RW
+#define SB_AZ_BAR_REG58 0x58 // RIRB Write Pointer - RW
+#define SB_AZ_BAR_REG5A 0x5A // RIRB Response Interrupt Count - R/W
+#define SB_AZ_BAR_REG5C 0x5C // RIRB Control - R/W
+#define SB_AZ_BAR_REG5D 0x5D // RIRB Status - R/W
+#define SB_AZ_BAR_REG5E 0x5E // RIRB Size - R/W
+#define SB_AZ_BAR_REG60 0x60 // Immediate Command Output Interface - R/W
+#define SB_AZ_BAR_REG64 0x64 // Immediate Command Input Interface - R/W
+#define SB_AZ_BAR_REG68 0x68 // Immediate Command Input Interface - R/W
+#define SB_AZ_BAR_REG70 0x70 // DMA Position Lower Base Address - R/W
+#define SB_AZ_BAR_REG74 0x74 // DMA Position Upper Base Address - R/W
+#define SB_AZ_BAR_REG2030 0x2030 // Wall Clock Counter Alias - R
+
+
+#define SB_LPC_REG00 0x00 // VID- R
+#define SB_LPC_REG02 0x02 // DID- R
+#define SB_LPC_REG04 0x04 // CMD- RW
+#define SB_LPC_REG06 0x06 // STATUS- RW
+#define SB_LPC_REG08 0x08 // Revision ID/Class Code - R
+#define SB_LPC_REG0C 0x0C // Cace Line Size - R
+#define SB_LPC_REG0D 0x0D // Latency Timer - R
+#define SB_LPC_REG0E 0x0E // eader Type - R
+#define SB_LPC_REG0F 0x0F // BIST- R
+#define SB_LPC_REG10 0x10 // Base Address Reg 0- RW*
+#define SB_LPC_REG2C 0x2C // Subsystem ID & Subsystem Vendor ID - Wo/Ro
+#define SB_LPC_REG34 0x34 // Capabilities Pointer - Ro
+#define SB_LPC_REG40 0x40 // PCI Control - RW
+#define SB_LPC_REG44 0x44 // IO Port Decode Enable Register 1- RW
+#define SB_LPC_REG45 0x45 // IO Port Decode Enable Register 2- RW
+#define SB_LPC_REG46 0x46 // IO Port Decode Enable Register 3- RW
+#define SB_LPC_REG47 0x47 // IO Port Decode Enable Register 4- RW
+#define SB_LPC_REG48 0x48 // IO/Mem Port Decode Enable Register 5- RW
+#define SB_LPC_REG49 0x49 // LPC Sync Timeout Count - RW
+#define SB_LPC_REG4A 0x4A // IO/Mem Port Decode Enable Register 6- RW
+#define SB_LPC_REG4C 0x4C // Memory Range Register - RW
+#define SB_LPC_REG50 0x50 // Rom Protect 0 - RW
+#define SB_LPC_REG54 0x54 // Rom Protect 1 - RW
+#define SB_LPC_REG58 0x58 // Rom Protect 2 - RW
+#define SB_LPC_REG5C 0x5C // Rom Protect 3 - RW
+#define SB_LPC_REG60 0x60 // PCI Memory Start Address of LPC Target Cycles -
+#define SB_LPC_REG62 0x62 // PCI Memory End Address of LPC Target Cycles -
+#define SB_LPC_REG64 0x64 // PCI IO base Address of Wide Generic Port - RW
+#define SB_LPC_REG65 0x65
+#define SB_LPC_REG66 0x66
+#define SB_LPC_REG67 0x67
+#define SB_LPC_REG68 0x68 // LPC ROM Address Range 1 (Start Address) - RW
+#define SB_LPC_REG69 0x69
+#define SB_LPC_REG6A 0x6A // LPC ROM Address Range 1 (End Address) - RW
+#define SB_LPC_REG6B 0x6B
+#define SB_LPC_REG6C 0x6C // LPC ROM Address Range 2 (Start Address)- RW
+#define SB_LPC_REG6D 0x6D
+#define SB_LPC_REG6E 0x6E // LPC ROM Address Range 2 (End Address) - RW
+#define SB_LPC_REG6F 0x6F
+#define SB_LPC_REG70 0x70 // Firmware ub Select - RW*
+#define SB_LPC_REG71 0x71
+#define SB_LPC_REG72 0x72
+#define SB_LPC_REG73 0x73
+#define SB_LPC_REG74 0x74 // Alternative Wide IO Range Enable- W/R
+#define SB_LPC_REG78 0x78 // Miscellaneous Control Bits- W/R
+#define SB_LPC_REG7C 0x7C // TPM (trusted plant form module) reg- W/R
+#define SB_LPC_REG9C 0x9C
+#define SB_LPC_REG80 0x80 // MSI Capability Register- R
+#define SB_LPC_REG8C 0x8C
+#define SB_LPC_REGA0 0x0A0 // SPI base address
+#define SB_LPC_REGA1 0x0A1 // SPI base address
+#define SB_LPC_REGA2 0x0A2 // SPI base address
+#define SB_LPC_REGA3 0x0A3 // SPI base address
+#define SB_LPC_REGA4 0x0A4
+#define SB_LPC_REGB8 0x0B8
+#define SB_LPC_REGBA 0x0BA // EcControl
+#define SB_LPC_REGBB 0x0BB // HostControl
+
+
+#define SB_P2P_REG00 0x00 // VID - R
+#define SB_P2P_REG02 0x02 // DID - R
+#define SB_P2P_REG04 0x04 // CMD- RW
+#define SB_P2P_REG06 0x06 // STATUS- RW
+#define SB_P2P_REG08 0x08 // Revision ID/Class Code- R
+#define SB_P2P_REG0C 0x0C // CSIZE- RW
+#define SB_P2P_REG0D 0x0D // LTIMER- RW
+#define SB_P2P_REG0E 0x0E // TYPE- R
+#define SB_P2P_REG18 0x18 // PBN- RW
+#define SB_P2P_REG19 0x19 // SBN- RW
+#define SB_P2P_REG1A 0x1A // SUBBN- RW
+#define SB_P2P_REG1B 0x1B // SLTIMER- RW
+#define SB_P2P_REG1C 0x1C // IOBASE- RW
+#define SB_P2P_REG1D 0x1D // IOLMT- RW
+#define SB_P2P_REG1E 0x1E // SSTATUS- RW
+#define SB_P2P_REG20 0x20 // MBASE- RW
+#define SB_P2P_REG21 0x21
+#define SB_P2P_REG22 0x22 // MLMT- RW
+#define SB_P2P_REG23 0x23
+#define SB_P2P_REG24 0x24 // PMBASE- RW
+#define SB_P2P_REG25 0x25
+#define SB_P2P_REG26 0x26 // PMLMT- RW
+#define SB_P2P_REG27 0x27
+#define SB_P2P_REG30 0x30 // IOBU16- RW
+#define SB_P2P_REG32 0x32 // IOLU16- RW
+#define SB_P2P_REG34 0x34 // ECP_PTR- R
+#define SB_P2P_REG3C 0x3C // INTLN- RW
+#define SB_P2P_REG3D 0x3D // INTPN- R
+#define SB_P2P_REG3E 0x3E // BCTRL- RW
+#define SB_P2P_REG40 0x40 // CPCTRL- R/W
+#define SB_P2P_REG41 0x41 // DCTRL- RW
+#define SB_P2P_REG42 0x42 // CLKCTRL- R/W
+#define SB_P2P_REG43 0x43 // ARCTRL- RW
+#define SB_P2P_REG44 0x44 // SMLT_PERF- RW
+#define SB_P2P_REG46 0x46 // PMLT_PERF- RW
+#define SB_P2P_REG48 0x48 // PCDMA- RW
+#define SB_P2P_REG49 0x49 // Additional Priority- Bits RW
+#define SB_P2P_REG4A 0x4A // PCICLK Enable- Bits RW
+#define SB_P2P_REG4B 0x4B // Misc Control RW
+#define SB_P2P_REG4C 0x4C // AutoClockRun control RW
+#define SB_P2P_REG50 0x50 // Dual Address Cycle Enable and PCIB_CLK_Stop
+#define SB_P2P_REG54 0x54 // MSI Mapping Capability
+#define SB_P2P_REG58 0x58 // Signature Register of Microsoft Rework
+#define SB_P2P_REG64 0x64 // Misc Control Register
+#define SB_P2P_REG65 0x65 // Misc Control Register
+
+#define SB_PMIO2_REG00 0x00
+#define SB_PMIO2_REG01 0x01
+#define SB_PMIO2_REG31 0x31
+#define SB_PMIO2_REG32 0x32
+#define SB_PMIO2_REG33 0x33
+#define SB_PMIO2_REG34 0x34
+#define SB_PMIO2_REG35 0x35
+#define SB_PMIO2_REG36 0x36
+#define SB_PMIO2_REG37 0x37
+#define SB_PMIO2_REG38 0x38
+#define SB_PMIO2_REG39 0x39
+#define SB_PMIO2_REG3A 0x3A
+#define SB_PMIO2_REG3B 0x3B
+#define SB_PMIO2_REG3C 0x3C
+#define SB_PMIO2_REG3D 0x3D
+#define SB_PMIO2_REG3E 0x3E
+#define SB_PMIO2_REG3F 0x3F
+#define SB_PMIO2_REG40 0x40
+#define SB_PMIO2_REG41 0x41
+#define SB_PMIO2_REG42 0x42
+#define SB_PMIO2_REG43 0x43
+#define SB_PMIO2_REG44 0x44
+#define SB_PMIO2_REG45 0x45
+#define SB_PMIO2_REG46 0x46
+#define SB_PMIO2_REG47 0x47
+#define SB_PMIO2_REG48 0x48
+#define SB_PMIO2_REG49 0x49
+#define SB_PMIO2_REG54 0x54
+#define SB_PMIO2_REG58 0x58
+#define SB_PMIO2_REG59 0x59
+#define SB_PMIO2_REG5A 0x5A
+#define SB_PMIO2_REG5B 0x5B
+#define SB_PMIO2_REG5C 0x5C
+#define SB_PMIO2_REG70 0x70
+#define SB_PMIO2_REGE5 0xE5
+
+#define SB_SPI_MMIO_REG0C 0x0C //SPI_Cntrl1 Register
+
+
+//Bus 0 Device 0x18 Function 0 HyperTransfer
+//Link Frequency/Revision Register 0x88/0xA8/0xC8/0xE8 - 32 bits.
+#define HT_LINK_REG89 0x89
+#define HT_LINK_REGA9 0xA9
+#define HT_LINK_REGC9 0xC9
+#define HT_LINK_REGE9 0xE9
+
+//Link Type Register 0x98/0xB8/0xD8/0xF8 - 32 bits.
+#define HT_LINK_REG98 0x98
+#define HT_LINK_REGB8 0xB8
+#define HT_LINK_REGD8 0xD8
+#define HT_LINK_REGF8 0xF8
+
+//Link Frequency Extension Register 0x9C/0xBC/0xDC/0xFC - 32 bits.
+#define HT_LINK_REG9C 0x9C
+#define HT_LINK_REGBC 0xBC
+#define HT_LINK_REGDC 0xDC
+#define HT_LINK_REGFC 0xFC
+
+//DRAM CS Base Address Register D18F2x40/x48/x50/x58
+#define DCT_REG40 0x40
+#define DCT_REG48 0x48
+#define DCT_REG50 0x50
+#define DCT_REG58 0x58
+
+//DRAM Configuration Low Register D18F2x90/x91/x92/x93
+#define DCT_REG90 0x90
+#define DCT_REG91 0x91
+#define DCT_REG92 0x92
+#define DCT_REG93 0x93
+
+#pragma pack(pop)
+
+#endif //#ifndef _AMD_SB700_H_
--- /dev/null
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include "Platform.h"
+
+
+REG8MASK sbEarlyPostByteInitTable[]={
+ // SMBUS Device(Bus 0, Dev 20, Func 0)
+ {0x00, SMBUS_BUS_DEV_FUN, 0},
+ {SB_SMBUS_REG43, ~(UINT8)BIT3, 0x00}, //Make BAR registers of smbus visible.
+ {SB_SMBUS_REG24, 0X00, (CIMx_Version & 0xFF)}, //Program the version information
+ {SB_SMBUS_REG24+1, 0x00, (CIMx_Version >> 8)},
+ {SB_SMBUS_REG24+2, 0x00, RC_Information},
+ {SB_SMBUS_REG24+3, 0x00, Additional_Changes_Indicator},
+ {SB_SMBUS_REG43, ~(UINT8)BIT3, BIT3}, //Make BAR registers of smbus invisible.
+ {SB_SMBUS_REGAE, ~(UINT8)(BIT6 + BIT5), BIT6 + BIT5}, //Disable Timer IRQ enhancement for proper operation of the 8254 timer.
+ // [6] - IoApicPicArbEn, set 1 to enable arbiter between APIC and PIC interrupts
+ {SB_SMBUS_REGAD, ~(UINT8)(BIT0+BIT1+BIT2+BIT4), BIT0+BIT3}, // Initialize SATA to default values, SATA Enabled,
+ // Combined mode enabled, SATA as primary, power saving enable
+ {SB_SMBUS_REGAF, 0xE3, 6 << 2}, // Set SATA Interrupt to INTG#
+ {SB_SMBUS_REG68, BIT3, 0 }, // First disable all usb controllers and then enable then according to setup selection
+ {0xFF, 0xFF, 0xFF},
+
+ // IDE Device(Bus 0, Dev 20, Func 1)
+ {0x00, IDE_BUS_DEV_FUN, 0},
+ {SB_IDE_REG62+1, ~(UINT8)BIT0, BIT5}, // Enabling IDE Explicit Pre-Fetch IDE PCI Config 0x62[8]=0
+ // Allow MSI capability of IDE controller to be visible. IDE PCI Config 0x62[13]=1
+ {0xFF, 0xFF, 0xFF},
+
+ // Azalia Device(Bus 0, Dev 20, Func 2)
+ {0x00, AZALIA_BUS_DEV_FUN, 0},
+ {SB_AZ_REG4C, ~(UINT8)BIT0, BIT0},
+ {0xFF, 0xFF, 0xFF},
+
+ // LPC Device(Bus 0, Dev 20, Func 3)
+ {0x00, LPC_BUS_DEV_FUN, 0},
+
+ {SB_LPC_REG40, ~(UINT8)BIT2, BIT2}, // Enabling LPC DMA Function 0x40[2]
+ {SB_LPC_REG78, ~(UINT8)BIT1, 00}, // Disables MSI capability
+ {0xFF, 0xFF, 0xFF},
+
+ // P2P Bridge(Bus 0, Dev 20, Func 4)
+ {0x00, SBP2P_BUS_DEV_FUN, 0},
+
+ {SB_P2P_REG64+1, 0xFF, BIT7+BIT6}, //Adjusting CLKRUN#, PCIB_PCI_Config 0x64[15]=01
+ //Enabling arbiter fix, PCIB_PCI_Config 0x64[14]=01
+ {SB_P2P_REG64+2, 0xFF, BIT4}, //Enabling One-Prefetch-Channel Mode, PCIB_PCI_config 0x64 [20]
+
+ {SB_P2P_REG0D, 0x00, 0x40}, //Setting Latency Timers to 0x40, Enables the PCIB to retain ownership
+ {SB_P2P_REG1B, 0x00, 0x40}, // of the bus on the Primary side and on the Secondary side when GNT# is deasserted.
+
+ {0xFF, 0xFF, 0xFF},
+
+ // SATA Device(Bus 0, Dev 17, Func 0)
+ {0x00, SATA_BUS_DEV_FUN, 0},
+ {SB_SATA_REG44, 0xff, BIT0}, // Enables the SATA watchdog timer register prior to the SATA BIOS post
+ {SB_SATA_REG40+3, 0xff, BIT5}, // RPR setting: Disable the testing/enhancement mode SATA_PCI_config 0x40 [29] = 1
+ {SB_SATA_REG48+2, 0xff, BIT5}, // RPR setting: Disable the testing/enhancement mode SATA_PCI_config 0x48 [24] = 1, [21] = 1
+ {SB_SATA_REG48+3, 0xff, BIT0},
+ {SB_SATA_REG44 + 2, 0, 0x10}, // Program watchdog timer with 16 retries before timer time-out.
+ {0xFF, 0xFF, 0xFF},
+};
+
+
+REG8MASK sbEarlyPostPmioInitTbl[]={
+ // index andmask ormask
+ {SB_PMIO_REG55, ~(UINT8)(BIT3+BIT4+BIT5), BIT5+BIT3}, //BIT3(PcieNative)=1b, BIT4(Pcie_Wak_Mask)=0b, BIT5(Pcie_WAK_Sci)=1b
+ {SB_PMIO_REG01, 0xff, BIT1},
+ {SB_PMIO_REG0E, 0xff, BIT2 + BIT3},
+ {SB_PMIO_REG10, 0x3E, (BIT6+BIT5+BIT3+BIT1)}, // RTC_En_En + TMR_En_En + GLB_EN_EN and clear EOS_EN + PciExpWakeDisEn
+ {SB_PMIO_REG61, 0xFF, 0x40}, // USB Device Support to Wakeup System from S3/S4 state, USB PME & PCI Act from NB
+ {SB_PMIO_REG59, 0xFC, 0x00 }, // Clear the flash controller bits BIT1:0
+ {SB_PMIO_REG01, 0xFF, 0x97 }, // Clear all the status
+ {SB_PMIO_REG05, 0xFF, 0xFF },
+ {SB_PMIO_REG06, 0xFF, 0xFF },
+ {SB_PMIO_REG07, 0xFF, 0xFF },
+ {SB_PMIO_REG0F, 0xFF, 0x1F },
+ {SB_PMIO_REG1D, 0xFF, 0xFF },
+ {SB_PMIO_REG39, 0xFF, 0xFF },
+ {SB_PMIO_REG7C, ~(UINT8)(BIT5+BIT3+BIT2), BIT3+BIT2}, //Turn on BLink LED
+ {SB_PMIO_REG67, 0xFF, 0x06}, // C State enable, must be set in order to exercise C state
+ {SB_PMIO_REG68, 0x38, 0x84},
+ {SB_PMIO_REG8D, 0xFF, 0x01}, // Set PM_Reg_0x8D[0] to enable PmeTurnOff/PmeMsgAck handshake to fix PCIE LAN S3/S4 wake failure
+ {SB_PMIO_REG84, 0xFD, BIT3+BIT0},
+ {SB_PMIO_REG53, 0xFF, BIT7+BIT6}, //ACPI System Clock setting, PMIO Reg 0x53[6]=1. Our reference clock
+ //is either 25 or 100Mhz and so the default acpi clock is actually
+ //running at 12.5Mhz and so the system time will run slow. We have
+ //generated another internal clock which runs at 14.318Mhz which is the
+ //correct frequency. We should set this bit to turn on this feature PMIO_REG53[6]=1
+ //PCI Clock Period, PM_IO 0x53 [7] = 1. By setting this, PCI clock period
+ //increase to 30.8 ns.
+ {SB_PMIO_REG95, ~(UINT8)(BIT2+BIT1+BIT0), BIT2+BIT1}, //USB Advanced Sleep Control, Enables USB EHCI controller
+ //to sleep for 6 uframes in stead of the standard 10us to
+ //improve power saving.
+ {SB_PMIO_REGD7, 0xFF, BIT6+BIT1},
+
+};
+
+
+// commonInitEarlyBoot - set /SMBUS/ACPI/IDE/LPC/PCIB. This settings should be done during S3 resume also
+void commonInitEarlyBoot(AMDSBCFG* pConfig) {
+ UINT16 dwTempVar;
+ CPUID_DATA CpuId;
+ CPUID_DATA CpuId_Brand;
+ UINT8 dbValue;
+ UINT32 ddValue;
+ UINT8 Family, Model, Stepping;
+
+ TRACE((DMSG_SB_TRACE, "CIMx - Entering commonInitEarlyBoot \n"));
+ CpuidRead (0x01, &CpuId);
+ CpuidRead (0x80000001, &CpuId_Brand); //BrandID
+
+ //Early post initialization of pci config space
+ programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbEarlyPostByteInitTable[0]), sizeof(sbEarlyPostByteInitTable)/sizeof(REG8MASK) );
+
+ // RPR 5.5 Clear PM_IO 0x65[4] UsbResetByPciRstEnable, Set this bit so that usb gets reset whenever there is PCIRST.
+ RWPMIO(SB_PMIO_REG65, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT4, BIT4);
+
+
+ #if 0 //KZ [083011]-It's used wrong BIOS SIZE for Coreboot.
+ //For being compatible with earlier revision, check whether ROM decoding is changed already outside CIMx before
+ //changing it.
+ ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG68, AccWidthUint16 | S3_SAVE, &dwTempVar);
+ if ( (dwTempVar == 0x08) || (dwTempVar == 0x00))
+ RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG68, AccWidthUint8 | S3_SAVE, 0, 0x0E);// Change the 1Mb below ROM decoding range to 0xE0000 to 0xFFFFF
+ #endif
+
+ if (pConfig->AzaliaController == 1)
+ RWPMIO(SB_PMIO_REG59, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, 0);
+ else
+ RWPMIO(SB_PMIO_REG59, AccWidthUint8 | S3_SAVE, 0xFF, BIT3);
+
+ //Disable or Enable PCI Clks based on input
+ RWPCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG42, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT5+BIT4+BIT3+BIT2), ((pConfig->PciClks) & 0x0F) << 2 );
+ RWPCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG4A, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT1+BIT0), ((pConfig->PciClks) >> 4) | ((pConfig->PciClk5) << 1) );
+ ReadPMIO(SB_PMIO_REG2C, AccWidthUint16, &dwTempVar); // Read Arbiter address, Arbiter address is in PMIO 2Ch
+ RWIO(dwTempVar, AccWidthUint8, 0, 0); // Write 0 to enable the arbiter
+
+ abLinkInitBeforePciEnum(pConfig); // Set ABCFG registers
+ // Set LDTSTP# duration to 10us for HydraD CPU model 8, 9 or A; or when HT link is 200MHz; or Family15 Orochi CPU C32/G34 package
+ ddValue = CpuId.REG_EAX & 0x00FF00F0;
+ dbValue = 1;
+
+ if((CpuId.REG_EAX & 0x00F00F00) == 0x00600F00) {
+ if(((CpuId_Brand.REG_EBX & 0xF0000000) == 0x30000000) || ((CpuId_Brand.REG_EBX & 0xF0000000) == 0x50000000)) {
+ //Orochi processor G34/C32, set to 10us
+ dbValue = 10;
+ }
+ else {
+ // Orochi processor AM3, set to 5us
+ dbValue = 5;
+ }
+ }
+
+ if ((pConfig->AnyHT200MhzLink) || (ddValue == 0x100080) || (ddValue == 0x100090) || (ddValue == 0x1000A0)) {
+ //any kind of CPU run HT at 200Mhz , or HydraD CPU model 8, 9 or A, set to 10us
+ dbValue = 10;
+ }
+
+
+ RWPMIO(SB_PMIO_REG8B, AccWidthUint8 | S3_SAVE, 0x00, dbValue);
+
+ // Enable/Disable watchdog timer
+ RWPMIO(SB_PMIO_REG69, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, (UINT8)(!pConfig->WatchDogTimerEnable));
+
+ // Per SB700/SP5100 RPR 2.5
+ //
+ // Enable C1e stutter timer for any system with chip revision >= A14
+ // Set SMBUS:0x5c[22:16] = 16 -- Set amount of idle time to 16ms
+ //
+
+ if (getRevisionID() >= SB700_A14) {
+ dwTempVar = 0x0010;
+
+ // Set PMIO:0xcb[5] = 1 -- AutoStutterTimerEn, set 1 to enable
+ // Set PMIO:0xcb[6] = 1 -- AutoStutterTimeSel, 1=1ms timer tick increment; 0=2us increment
+ RWPMIO(SB_PMIO_REGCB, AccWidthUint8 | S3_SAVE, 0xff, BIT6 + BIT5);
+
+ Family = (UINT8)((CpuId.REG_EAX & 0x00ff0000)>> 16);
+ Model = (UINT8)((CpuId.REG_EAX & 0x000000f0)>> 4);
+ Stepping = (UINT8) (CpuId.REG_EAX & 0x0000000f);
+
+ // For Server system (SP5100) with CPU type = Family 10h with LS2 mode enabled:
+ // Model=6 && Stepping=2 || Model=(4I5|6) && Stepping >=3 || Model=(8|9) && Stepping >= 1 || Model Ah
+ // Set SMBUS:0x5c[22:16] = 20 -- Set amount of idle time to 20ms
+ if (IsLs2Mode() && (Family == 0x10)) {
+ switch( Model ){
+ case 0x4:
+ case 0x5:
+ if( Stepping >= 3 ) dwTempVar = 0x14;
+ break;
+ case 0x6:
+ if( Stepping >= 2 ) dwTempVar = 0x14;
+ break;
+ case 0x8:
+ if( Stepping >= 1 ) dwTempVar = 0x14;
+ break;
+ case 0x9:
+ if( Stepping >= 1 ) dwTempVar = 0x14;
+ break;
+ case 0xA:
+ dwTempVar = 0x14;
+ break;
+ }
+ }
+ // Set SMBUS:0x5c[7] = 1 -- CheckC3, set 1 to check for C3 state
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG5C, AccWidthUint32 | S3_SAVE, ~(0x7F << 16), (dwTempVar << 16) + BIT7);
+ }
+
+ //Message-Triggered C1E is not supported in Family 10h G34r1 HY-D0 (0x00100F90) and Family 10h C32 HY-D0 (0x00100F80) processor.
+ ddValue = CpuId.REG_EAX;
+ if ((getRevisionID() == SB700_A15) && (pConfig->MTC1e == CIMX_OPTION_ENABLED) && (ddValue != 0x00100F90) && (ddValue != 0x00100F80)) {
+ //
+ // MTC1e: For A15 (server only) - The settings here borrow the existing legacy ACPI BM_STS and BM_RLD bits as a
+ // mechanism to break out from C1e under a non-OS controlled C3 state. Under this scheme, the logic will automatically
+ // clear the BM_STS bit whenever it enters C1e state. Whenever BM_REQ#/IDLE_EXIT# is detected, it will cause the
+ // BM_STS bit to be set and therefore causing the C state logic to exit.
+ //
+ // Set BMReqEnable (SMBUS:0x64[5]=1) to enable the pin as BM_REQ#/IDLE_EXIT# to the C state logic
+ // Set CheckOwnReq (SMBUS:0x64[4]=0) to force IDLE_EXIT# to set BM_STS and wake from C3
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64, AccWidthUint8 | S3_SAVE, 0xEF, BIT5);
+
+ // Set PCI_Active_enable (PMIO:0x61[2]=1), the secondary enable bit for SB to monitor BM_REQ#/IDLE_EXIT#
+ RWPMIO(SB_PMIO_REG61, AccWidthUint8 | S3_SAVE, 0xff, BIT2);
+
+ // Set auto_bm_rld (PMIO:0x9a[4]=1) so that assertion on BM_REQ#/IDLE_EXIT# pin will cause C state logic to break out from C1e
+ // Set auto_clr_bm_sts (PMIO:0x9a[5]=1) will cause the C state logic to automatically clear the BM_STS bit whenever it sees a C1e entry
+ RWPMIO(SB_PMIO_REG9A, AccWidthUint8 | S3_SAVE, 0xff, BIT5 + BIT4);
+
+
+ // MTC1e: The logic basically counts the number of HALT_ENTER messages. When it has received the number of HALT_ENTER
+ // messages equal to NumOfCpu (PMIO:0xc9[3:0]), it will generate an internal C1e command to the C state logic.
+ // The count increments when it sees HALT_ENTER message after it has generated the C1e command, and it treats the
+ // HALT_EXIT message as a break event.
+ //
+ // Set ServerCEn
+ RWPMIO(SB_PMIO_REGBB, AccWidthUint8 | S3_SAVE, 0xFF, BIT7);
+
+ // Enable counting HALT
+ // PMIO:0xc9[4] = CountHaltMsgEn
+ // PMIO:0xc9[3:0] = NumOfCpu, set to 1 since CPU logic will coordinate among cores and only generate one HALT message
+ RWPMIO(SB_PMIO_REGC9, AccWidthUint8 | S3_SAVE, 0xE0, BIT4 + 1);
+ }
+
+ c3PopupSetting(pConfig);
+
+ TRACE((DMSG_SB_TRACE, "CIMx - Exiting commonInitEarlyBoot \n"));
+}
+
+
+void commonInitEarlyPost(AMDSBCFG* pConfig){
+ //early post initialization of pmio space
+ programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sbEarlyPostPmioInitTbl[0]), (sizeof(sbEarlyPostPmioInitTbl)/sizeof(REG8MASK)) );
+ CallBackToOEM(PULL_UP_PULL_DOWN_SETTINGS, NULL, pConfig);
+}
+
+
+// AB-Link Configuration Table
+ABTBLENTRY abTblEntry600[]={
+ // Enabling Downstream Posted Transactions to Pass Non-Posted Transactions for the K8 Platform ABCFG 0x10090[8] = 1
+ // ABCFG 0x10090 [16] = 1, ensures the SMI# message to be sent before the IO command is completed. The ordering of
+ // SMI# and IO is important for the IO trap to work properly.
+ {ABCFG,SB_AB_REG10090 ,BIT16+BIT8 ,BIT16+BIT8 },
+ // Enabling UpStream DMA Access AXCFG: 0x04[2]=1
+ {AXCFG,SB_AB_REG04 ,BIT2 ,BIT2 },
+ // Setting B-Link Prefetch Mode ABCFG 0x80 [17] = 1 ABCFG 0x80 [18] = 1
+ {ABCFG,SB_AB_REG80 ,BIT17+BIT18 ,BIT17+BIT18 },
+ // Disable B-Link client's credit variable in downstream arbitration equation (for All Revisions)
+ // ABCFG 0x9C[0] = 1 Disable credit variable in downstream arbitration equation
+ // Enabling Additional Address Bits Checking in Downstream Register Programming
+ // ABCFG 0x9C[1] = 1
+ {ABCFG,SB_AB_REG9C ,BIT8+BIT1+BIT0 ,BIT8+BIT1+BIT0 },
+ // Enabling IDE/PCIB Prefetch for Performance Enhancement
+ // IDE prefetch ABCFG 0x10060 [17] = 1 ABCFG 0x10064 [17] = 1
+ // PCIB prefetch ABCFG 0x10060 [20] = 1 ABCFG 0x10064 [20] = 1
+ {ABCFG,SB_AB_REG10060 ,BIT17+BIT20 ,BIT17+BIT20 }, // IDE+PCIB prefetch enable
+ {ABCFG,SB_AB_REG10064 ,BIT17+BIT20 ,BIT17+BIT20 }, // IDE+PCIB prefetch enable
+ // Enabling Detection of Upstream Interrupts ABCFG 0x94 [20] = 1
+ // ABCFG 0x94 [19:0] = cpu interrupt delivery address [39:20]
+ {ABCFG,SB_AB_REG94 ,BIT20 ,BIT20+0x00FEE },
+ // Programming cycle delay for AB and BIF clock gating
+ // Enabling AB and BIF Clock Gating
+ // Enabling AB Int_Arbiter Enhancement
+ // Enabling Requester ID
+ {ABCFG,SB_AB_REG10054, 0x00FFFFFF , 0x010407FF },
+ {ABCFG,SB_AB_REG98 , 0xFFFF00FF , 0x00014700 }, // Enable the requestor ID for upstream traffic ABCFG 0x98[16]=1
+// {ABCFG,SB_AB_REG54 , 0x00FF0000 , 0x01040000 },
+ {ABCFG,SB_AB_REG54 , 0x00FF0000 , 0x00040000 },
+
+ {ABCFG,0,0,-1}, // This dummy entry is to clear ab index
+ {-1, -1, -1, -1 },
+};
+
+
+// AB-Link Configuration Table
+ABTBLENTRY abTblForA15[]={
+
+ //SMI Reordering fix
+ {ABCFG, SB_AB_REG90 ,BIT21 , BIT21 },
+ {ABCFG, SB_AB_REG9C ,BIT15+BIT9+BIT5 ,BIT15+BIT9+BIT5},
+
+ //Posted pass NP Downstream feature
+ {AX_INDXC, SB_AB_REG02, BIT9 ,BIT9 },
+ {ABCFG, SB_AB_REG9C, BIT14+BIT13+BIT12+BIT11+BIT10+BIT7+BIT6 , BIT14+BIT13+BIT12+BIT11+BIT10+BIT7+BIT6},
+ {ABCFG, SB_AB_REG1009C, BIT5+BIT4 , BIT5+BIT4},
+
+ //Posted pass NP upstream feature
+ {ABCFG, SB_AB_REG58, BIT15+BIT14+BIT13+BIT12+BIT11, BIT15+BIT14+BIT13+BIT11},
+
+ //64 bit Non-posted memory write support
+ {AX_INDXC, SB_AB_REG02, BIT10 ,BIT10 },
+
+ {ABCFG, SB_AB_REG10090, BIT12+BIT11+BIT10+BIT9 , BIT12+BIT11+BIT10+BIT9},
+
+ {ABCFG,0,0,-1}, // This dummy entry is to clear ab index
+ {-1, -1, -1, -1 },
+};
+
+
+// abLinkInitBeforePciEnum - Set ABCFG registers
+void abLinkInitBeforePciEnum(AMDSBCFG* pConfig){
+ ABTBLENTRY *pAbTblPtr;
+
+ // disable PMIO decoding when AB is set
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT2, 0);
+
+ pAbTblPtr = (ABTBLENTRY *)FIXUP_PTR(&abTblEntry600[0]);
+ abcfgTbl(pAbTblPtr);
+
+ if (getRevisionID() > SB700_A11){
+ //Enable OHCI Prefetch
+ writeAlink( (SB_AB_REG80 | (ABCFG << 30)), (readAlink((SB_AB_REG80 | (ABCFG << 30)))) | BIT0);
+ //Register bit to maintain correct ordering of SMI and IO write completion
+ writeAlink( (SB_AB_REG8C | (ABCFG << 30)), (readAlink((SB_AB_REG8C | (ABCFG << 30)))) | BIT8);
+ }
+
+ if (getRevisionID() >= SB700_A14){
+ //Enable fix for TT SB01345
+ writeAlink( (SB_AB_REG90 | (ABCFG << 30)), (readAlink((SB_AB_REG90 | (ABCFG << 30)))) | BIT17);
+ //Disable IO Write and SMI ordering enhancement
+ writeAlink( (SB_AB_REG9C | (ABCFG << 30)), (readAlink((SB_AB_REG9C | (ABCFG << 30)))) & (0xFFFFFEFF));
+ }
+
+ if (getRevisionID() >= SB700_A15) {
+ pAbTblPtr = (ABTBLENTRY *)FIXUP_PTR(&abTblForA15[0]);
+ abcfgTbl(pAbTblPtr);
+ }
+
+
+ // enable pmio decoding after ab is configured
+ // or BYTE PTR es:[ebp+SMBUS_BUS_DEV_FUN shl 12 + SB_SMBUS_REG64], BIT2
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT2, BIT2);
+}
+
+
+void abcfgTbl(ABTBLENTRY* pABTbl){
+ UINT32 ddValue;
+
+ while ((pABTbl->regType) != 0xFF){
+ TRACE((DMSG_SB_TRACE, "RegType: %X, RegNumber:%X, AndMask=%X, OrMask=%X \n",pABTbl->regType , pABTbl->regIndex, pABTbl->regMask, pABTbl->regData));
+ if (pABTbl->regType > AX_INDXP){
+ ddValue = pABTbl->regIndex | (pABTbl->regType << 30);
+ writeAlink(ddValue, ((readAlink(ddValue)) & (0xFFFFFFFF^(pABTbl->regMask)))|pABTbl->regData);
+ }
+ else{
+ ddValue = 0x30 | (pABTbl->regType << 30);
+ writeAlink(ddValue, pABTbl->regIndex);
+ ddValue = 0x34 | (pABTbl->regType << 30);
+ writeAlink(ddValue, ((readAlink(ddValue)) & (0xFFFFFFFF^(pABTbl->regMask)))|pABTbl->regData);
+ }
+ ++pABTbl;
+ }
+
+ //Clear ALink Access Index
+ ddValue = 0;
+ WriteIO(ALINK_ACCESS_INDEX, AccWidthUint32 | S3_SAVE, &ddValue);
+ TRACE((DMSG_SB_TRACE, "Exiting abcfgTbl\n"));
+}
+
+
+// programSubSystemIDs - Config Subsystem ID for all SB devices.
+void programSubSystemIDs(AMDSBCFG* pConfig, BUILDPARAM *pStaticOptions){
+ UINT32 ddTempVar;
+ UINT16 dwDeviceId;
+
+ RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci0Ssid);
+ RWPCI((USB1_OHCI1_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci1Ssid);
+ RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci2Ssid);
+ RWPCI((USB2_OHCI1_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci3Ssid);
+ RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ohci4Ssid);
+
+ RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ehci0Ssid);
+ RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->Ehci1Ssid);
+
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->SmbusSsid);
+ RWPCI((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->IdeSsid);
+ RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->LpcSsid);
+ RWPCI((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pStaticOptions->AzaliaSsid);
+
+ ddTempVar = pStaticOptions->SataIDESsid;
+ if ( ((pConfig->SataClass) == AHCI_MODE) || ((pConfig->SataClass)== IDE_TO_AHCI_MODE) )
+ ddTempVar = pStaticOptions->SataAHCISsid;
+
+ ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, &dwDeviceId);
+ if ((pConfig->SataClass) == RAID_MODE){
+ ddTempVar = pStaticOptions->SataRAIDSsid;
+ if (dwDeviceId==SB750_SATA_DEFAULT_DEVICE_ID)
+ ddTempVar = pStaticOptions->SataRAID5Ssid;
+ }
+
+ if ( ((pConfig->SataClass) == AMD_AHCI_MODE) || ((pConfig->SataClass) == IDE_TO_AMD_AHCI_MODE) ) {
+ ddTempVar = pStaticOptions->SataAHCISsid;
+ }
+ RWPCI((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG2C, AccWidthUint32 | S3_SAVE, 0x00, ddTempVar);
+}
+
+void commonInitLateBoot(AMDSBCFG* pConfig){
+ UINT8 dbValue;
+ UINT32 ddVar;
+
+ // We need to do the following setting in late post also because some bios core pci enumeration changes these values
+ // programmed during early post.
+ // RPR 4.5 Master Latency Timer
+ // Master Latency Timer PCIB_PCI_config 0x0D/0x1B = 0x40
+ // Enables the PCIB to retain ownership of the bus on the
+ // Primary side and on the Secondary side when GNT# is deasserted.
+ //mov BYTE PTR es:[ebp+SBP2P_BUS_DEV_FUN shl 12 + SB_P2P_REG0D], 40h
+ //mov BYTE PTR es:[ebp+SBP2P_BUS_DEV_FUN shl 12 + SB_P2P_REG1B], 40h
+ dbValue = 0x40;
+ WritePCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG0D, AccWidthUint8, &dbValue);
+ WritePCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG1B, AccWidthUint8, &dbValue);
+
+ //SB P2P AutoClock control settings.
+ ddVar = (pConfig->PcibAutoClkCtrlLow) | (pConfig->PcibAutoClkCtrlLow);
+ WritePCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG4C, AccWidthUint32, &ddVar);
+ ddVar = (pConfig->PcibClkStopOverride);
+ RWPCI((SBP2P_BUS_DEV_FUN << 16) + SB_P2P_REG50, AccWidthUint16, 0x3F, (UINT16) (ddVar << 6));
+
+ if (pConfig->MobilePowerSavings){
+ //If RTC clock is not driven to any chip, it should be shut-off. If system uses external RTC, then SB needs to
+ //drive out RTC clk to external RTC chip. If system uses internal RTC, then this clk can be shut off.
+ RWPMIO(SB_PMIO_REG68, AccWidthUint8, ~(UINT32)BIT4, (pConfig->ExternalRTCClock)<<4);
+ if (!getClockMode()){
+ if (!(pConfig->UsbIntClock) ){
+ //If the external clock is used, the second PLL should be shut down
+ RWPMIO(SB_PMIO_REGD0, AccWidthUint8, 0xFF, BIT0);
+ // If external clock mode is used, the 25Mhz oscillator buffer can be turned-off by setting PMIO 0xD4[7]=1
+ RWPMIO(SB_PMIO_REGD4, AccWidthUint8, 0xFF, BIT7);
+ //Disable unused clocks
+ RWPMIO(SB_PMIO_REGCA, AccWidthUint8, 0xFF, 0x7E);
+ }
+ }
+ writeAlink(0x30, SB_AB_REG40);
+ writeAlink(0x34, ((readAlink(0x34)) & 0xFFFF0000) | 0x008A);
+
+ }
+ else{
+ //Don't shutoff RTC clock
+ RWPMIO(SB_PMIO_REG68, AccWidthUint8, ~(UINT32)BIT4, 0);
+ //Dont disable second PLL
+ RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)BIT0, 0);
+ //Enable the 25Mhz oscillator
+ RWPMIO(SB_PMIO_REGD4, AccWidthUint8, ~(UINT32)BIT7, 0);
+ RWPMIO(SB_PMIO_REGCA, AccWidthUint8, 0xFF, 0x00);
+ }
+}
+
+
+void
+hpetInit (AMDSBCFG* pConfig, BUILDPARAM *pStaticOptions)
+{
+ DESCRIPTION_HEADER* pHpetTable;
+
+ if (pConfig->HpetTimer == 1) {
+ UINT8 dbTemp;
+
+ RWPMIO(SB_PMIO_REG9A, AccWidthUint8, 0xFF, BIT7);
+ // Program the HPET BAR address
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGB4, AccWidthUint32 | S3_SAVE, 0, pStaticOptions->HpetBase);
+
+ // Enable HPET MMIO decoding: SMBUS:0x43[4] = 1
+ // Enable HPET MSI support only when HpetMsiDis == 0
+ dbTemp = (pConfig->HpetMsiDis)? BIT4 : BIT7 + BIT6 + BIT5 + BIT4;
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, dbTemp);
+ // Program HPET default clock period
+ if (getRevisionID() >= SB700_A13) {
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG34, AccWidthUint32 | S3_SAVE, 0x00, 0x429B17E);
+ }
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, 0xFF, BIT3);
+ // Enable High Precision Event Timer (also called Multimedia Timer) interrupt
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + (SB_SMBUS_REG64+1), AccWidthUint8 | S3_SAVE, ~(UINT32)BIT2, BIT2);
+ }
+ else {
+ if (!(pConfig->S3Resume)) {
+// pHpetTable = (DESCRIPTION_HEADER*)ACPI_LocateTable('TEPH');
+ pHpetTable = (DESCRIPTION_HEADER*)ACPI_LocateTable(Int32FromChar ('T', 'E', 'P', 'H'));
+ if (pHpetTable != NULL) {
+// pHpetTable->Signature = 'HPET';
+ pHpetTable->Signature = Int32FromChar ('T', 'E', 'P', 'H');
+ }
+ }
+ }
+}
+
+
+void c3PopupSetting(AMDSBCFG* pConfig){
+ UINT8 dbTemp;
+ CPUID_DATA CpuId;
+
+ CpuidRead (0x01, &CpuId);
+ //RPR 2.3 C-State and VID/FID Change
+ dbTemp = GetNumberOfCpuCores();
+ if (dbTemp > 1){
+ //PM_IO 0x9A[5]=1, For system with dual core CPU, set this bit to 1 to automatically clear BM_STS when the C3 state is being initiated.
+ //PM_IO 0x9A[4]=1, For system with dual core CPU, set this bit to 1 and BM_STS will cause C3 to wakeup regardless of BM_RLD
+ //PM_IO 0x9A[2]=1, Enable pop-up for C3. For internal bus mastering or BmReq# from the NB, the SB will de-assert
+ //LDTSTP# (pop-up) to allow DMA traffic, then assert LDTSTP# again after some idle time.
+ RWPMIO(SB_PMIO_REG9A, AccWidthUint8, 0xFF, BIT5+BIT4+BIT2);
+ }
+
+ //SB700 needs to changed for RD790 support
+ //PM_IO 0x8F [4] = 0 for system with RS690
+ //Note: RS690 north bridge has AllowLdtStop built for both display and PCIE traffic to wake up the HT link.
+ //BmReq# needs to be ignored otherwise may cause LDTSTP# not to toggle.
+ //PM_IO 0x8F[5]=1, Ignore BM_STS_SET message from NB
+ RWPMIO(SB_PMIO_REG8F, AccWidthUint8, ~(UINT32)(BIT5+BIT4), BIT5);
+
+ //LdtStartTime = 10h for minimum LDTSTP# de-assertion duration of 16us in StutterMode. This is to guarantee that
+ //the HT link has been safely reconnected before it can be disconnected again. If C3 pop-up is enabled, the 16us also
+ //serves as the minimum idle time before LDTSTP# can be asserted again. This allows DMA to finish before the HT
+ //link is disconnected.
+ //Increase LDTSTOP Deassertion time for SP5100 to 20us, SB700 remains the same
+ dbTemp = (IsServer())? 0x14 : 0x10;
+ RWPMIO(SB_PMIO_REG88, AccWidthUint8, 0x00, dbTemp);
+
+ //This setting provides 16us delay before the assertion of LDTSTOP# when C3 is entered. The
+ //delay will allow USB DMA to go on in a continous manner
+ RWPMIO(SB_PMIO_REG89, AccWidthUint8, 0x00, 0x10);
+
+ //Set this bit to allow pop-up request being latched during the minimum LDTSTP# assertion time
+ RWPMIO(SB_PMIO_REG52, AccWidthUint8, 0xFF, BIT7);
+
+}
+
--- /dev/null
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include "Platform.h"
+
+UINT8 isEcPresent(){
+ UINT8 dbFlag;
+ UINT16 dwVar0;
+
+ //Read the EC configuration register base address from LPCCfg_A4[15:1]
+ //Write 0x5A to the EC config index register to unlock the access
+ //Write 0x20 to the EC config index register to select the device ID register
+ //Read the value of device ID register from the EC config data register
+ //If the value read is 0xB7, then EC is enabled.
+ //Write 0xA5 to re-lock the EC config index register if EC is enabled.
+
+ ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4, AccWidthUint16 | S3_SAVE, &dwVar0);
+ dwVar0 &= 0xFFFE;
+ RWIO(dwVar0, AccWidthUint8, 0, 0x5A);
+ RWIO(dwVar0, AccWidthUint8, 0, 0x20);
+ ReadIO(dwVar0+1, AccWidthUint8, &dbFlag);
+ RWIO(dwVar0, AccWidthUint8, 0, 0xA5);
+
+ return ( dbFlag == 0xB7);
+}
+
+void
+getSbInformation (
+SB_INFORMATION *sbInfo){
+ UINT16 dwDevId;
+ UINT8 dbRev;
+
+ ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG02, AccWidthUint16 | S3_SAVE, &dwDevId);
+ ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08, AccWidthUint8 | S3_SAVE, &dbRev);
+ sbInfo->sbModelMask = SB_MODEL_UNKNOWN;
+ if ( (dwDevId == SB7XX_DEVICE_ID) && (dbRev <= SB_Rev_Sb7xx_A14) ){
+ sbInfo->sbModelMask |= SB_MODEL_SB700;
+ sbInfo->sbModelMask |= SB_MODEL_SR5690;
+ sbInfo->sbRev = dbRev;
+ ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint8 | S3_SAVE, &dbRev);
+ if (dbRev & 01)
+ sbInfo->sbModelMask |= SB_MODEL_SB750;
+ if (isEcPresent())
+ sbInfo->sbModelMask |= SB_MODEL_SB710;
+ return;
+ }
+}
+
+
+SB_CAPABILITY_SETTING
+getSbCapability (
+SB_CAPABILITY_ITEM sbCapabilityItem
+)
+{
+ SB_CAPABILITY_SETTING sbCapSetting=SB_UNKNOWN;
+ UINT32 ddTemp0;
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, 00);
+ ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG10, AccWidthUint32, &ddTemp0);
+
+ if (sbCapabilityItem < Sb_Unknown_Capability)
+ sbCapSetting = ((ddTemp0 >> (sbCapabilityItem << 1) ) & 0x03);
+
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, 0xFF, BIT3);
+ return sbCapSetting;
+}
+
+
+void
+setSbCapability (
+SB_CAPABILITY_ITEM sbCapabilityItem, SB_CAPABILITY_SETTING sbCapSetting
+)
+{
+ UINT32 ddTemp0;
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT3, 00);
+ ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG10, AccWidthUint32, &ddTemp0);
+ if ( (sbCapabilityItem < Sb_Unknown_Capability) & (sbCapSetting < Sb_Cap_Setting_Unknown) )
+ ddTemp0 = (ddTemp0 & ~(0x03 << (sbCapabilityItem << 1))) | ( (sbCapSetting & 0x03) << (sbCapabilityItem << 1));
+ WritePCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG10, AccWidthUint32, &ddTemp0);
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, 0xFF, BIT3);
+}
--- /dev/null
+/*;********************************************************************************
+;
+; Copyright (C) 2012 Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; * Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; * Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; * Neither the name of Advanced Micro Devices, Inc. nor the names of
+; its contributors may be used to endorse or promote products derived
+; from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*********************************************************************************/
+
+#ifndef _AMD_SBLIB_H_
+#define _AMD_SBLIB_H_
+
+//SB7xx Family
+#define SB7xx_DEVICE_ID 0x4385
+#define SB700 0x00
+#define SB750 0x01
+#define SB710 0x02
+
+//SB800 Family
+#define SB800 0x10
+
+#define SB_UNKNOWN 0xFF
+
+//SB700 Revision IDs
+#define SB700_A11 0x39
+#define SB700_A12 0x3A
+#define SB700_A13 0x3B
+#define SB700_A14 0x3C
+
+#define SB_Rev_Sb7xx_A11 0x39
+#define SB_Rev_Sb7xx_A12 0x3A
+#define SB_Rev_Sb7xx_A13 0x3B
+#define SB_Rev_Sb7xx_A14 0x3C
+
+
+typedef enum {
+ Sb_Raid0_1_Capability, ///
+ Sb_Raid5_Capability, ///
+ Sb_Ahci_Capability, ///
+ Sb_Unknown_Capability
+} SB_CAPABILITY_ITEM;
+
+
+typedef enum {
+ Sb_Cap_Setting_Auto,
+ Sb_Cap_Setting_Enabled,
+ Sb_Cap_Setting_Disabled,
+ Sb_Cap_Setting_Unknown
+} SB_CAPABILITY_SETTING;
+
+
+#define SB_MODEL_SB700 BIT0
+#define SB_MODEL_SB750 BIT1
+#define SB_MODEL_SB710 BIT2
+#define SB_MODEL_SR5690 BIT3
+#define SB_MODEL_UNKNOWN BIT31
+
+typedef struct
+{
+ UINT32 sbModelMask;
+ UINT8 sbRev;
+}SB_INFORMATION;
+
+
+void getSbInformation (SB_INFORMATION *sbInfo);
+SB_CAPABILITY_SETTING getSbCapability (SB_CAPABILITY_ITEM sbCapabilityItem);
+void setSbCapability (SB_CAPABILITY_ITEM sbCapabilityItem, SB_CAPABILITY_SETTING sbCapSetting);
+
+#endif //#ifndef _AMD_SBLIB_H_
--- /dev/null
+/*;********************************************************************************
+;
+; Copyright (C) 2012 Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; * Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; * Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; * Neither the name of Advanced Micro Devices, Inc. nor the names of
+; its contributors may be used to endorse or promote products derived
+; from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*********************************************************************************/
+
+#ifndef _AMD_SBDEF_H_
+#define _AMD_SBDEF_H_
+
+//AMD Library Routines
+
+UINT64
+MsrRead (
+ IN UINT32 MsrAddress
+ );
+
+VOID
+MsrWrite (
+ IN UINT32 MsrAddress,
+ IN UINT64 Value
+ );
+
+void ReadIO(UINT16 Address, UINT8 OpFlag, void *Value);
+void WriteIO(UINT16 Address, UINT8 OpFlag, void *Value);
+void ReadPCI(UINT32 Address, UINT8 OpFlag, void *Value);
+void WritePCI(UINT32 Address,UINT8 OpFlag, void *Value);
+void RWPCI(UINT32 Address,UINT8 OpFlag,UINT32 Mask,UINT32 Data);
+void ReadIndexPCI32(UINT32 PciAddress,UINT32 IndexAddress,void* Value);
+void WriteIndexPCI32(UINT32 PciAddress,UINT32 IndexAddress,UINT8 OpFlag,void* Value);
+void RWIndexPCI32(UINT32 PciAddress,UINT32 IndexAddress,UINT8 OpFlag,UINT32 Mask,UINT32 Data);
+void RWIO (UINT16 Address, UINT8 OpFlag, UINT32 Mask, UINT32 Data);
+void ReadMEM(UINT32 Address,UINT8 OpFlag, void* Value);
+void WriteMEM(UINT32 Address,UINT8 OpFlag, void* Value);
+void RWMEM(UINT32 Address,UINT8 OpFlag,UINT32 Mask,UINT32 Data);
+UINT32 IsFamily10(void);
+UINT64 ReadMSR(UINT32 Address);
+void WriteMSR(UINT32 Address,UINT64 Value);
+void RWMSR(UINT32 Address, UINT64 Mask, UINT64 Value);
+void* LocateImage(UINT32 Signature);
+void* CheckImage( UINT32 Signature, void* ImagePtr);
+void Stall(UINT32 uSec);
+void Reset(void);
+CIM_STATUS RWSMBUSBlock(UINT8 Controller, UINT8 Address, UINT8 Offset, UINT8 BufferSize, UINT8* BufferPrt);
+void InitSerialOut(void);
+void ReadPMIO(UINT8 Address, UINT8 OpFlag, void* Value);
+void WritePMIO(UINT8 Address, UINT8 OpFlag, void* Value);
+void RWPMIO(UINT8 Address, UINT8 OpFlag, UINT32 AndMask, UINT32 OrMask);
+void ReadPMIO2(UINT8 Address, UINT8 OpFlag, void* Value);
+void WritePMIO2(UINT8 Address, UINT8 OpFlag, void* Value);
+void RWPMIO2(UINT8 Address, UINT8 OpFlag, UINT32 AndMask, UINT32 OrMask);
+void outPort80(UINT32 pcode);
+UINT8 GetNumberOfCpuCores(void);
+UINT8 ReadNumberOfCpuCores(void);
+UINT8 GetByteSum(void* pData, UINT32 Length);
+UINT32 readAlink(UINT32 Index);
+void writeAlink(UINT32 Index,UINT32 Data);
+
+//----------------------------------------------------------------------------------------------
+//----------------------------------------------------------------------------------------------
+void azaliaInitAfterPciEnum (AMDSBCFG* pConfig);
+
+void SendBytePort(UINT8 Data);
+void SendStringPort(char* pstr);
+void ItoA(UINT32 Value,int Radix,char* pstr);
+AMDSBCFG* getConfigPointer(void);
+void saveConfigPointer(AMDSBCFG* pConfig);
+
+
+UINT32 GetFixUp(void);
+
+void sataInitAfterPciEnum(AMDSBCFG* pConfig);
+void sataInitBeforePciEnum(AMDSBCFG* pConfig);
+void sataInitLatePost(AMDSBCFG* pConfig);
+void sataDriveDetection(AMDSBCFG* pConfig, UINT32 ddBar5);
+void sataPhyWorkaround(AMDSBCFG* pConfig, UINT32 ddBar5);
+void forceOOB(UINT32 ddBar5);
+void shutdownUnconnectedSataPortClock(AMDSBCFG* pConfig, UINT32 ddBar5);
+void restrictSataCapabilities(AMDSBCFG* pConfig);
+
+
+void commonInitEarlyBoot(AMDSBCFG* pConfig);
+void commonInitEarlyPost(AMDSBCFG* pConfig);
+void setRevisionID(void);
+UINT8 getRevisionID(void);
+UINT8 IsServer (void);
+UINT8 IsLs2Mode (void);
+void abLinkInitBeforePciEnum(AMDSBCFG* pConfig);
+void abcfgTbl(ABTBLENTRY* pABTbl);
+void programSubSystemIDs(AMDSBCFG* pConfig, BUILDPARAM *pStaticOptions);
+void commonInitLateBoot(AMDSBCFG* pConfig);
+void hpetInit(AMDSBCFG* pConfig, BUILDPARAM *pStaticOptions);
+void c3PopupSetting(AMDSBCFG* pConfig);
+
+void sbBeforePciInit (AMDSBCFG* pConfig);
+void sbAfterPciInit(AMDSBCFG* pConfig);
+void sbLatePost(AMDSBCFG* pConfig);
+void sbBeforePciRestoreInit(AMDSBCFG* pConfig);
+void sbAfterPciRestoreInit(AMDSBCFG* pConfig);
+void sbSmmAcpiOn(AMDSBCFG* pConfig);
+UINT32 GetPciebase(void);
+UINT32 CallBackToOEM(UINT32 Func, UINTN Data,AMDSBCFG* pConfig);
+void sbSmmService(AMDSBCFG* pConfig);
+void softwareSMIservice(void);
+
+void sbPowerOnInit (AMDSBCFG *pConfig);
+void programPciByteTable(REG8MASK* pPciByteTable, UINT16 dwTableSize);
+void programPmioByteTable(REG8MASK* pPmioByteTable, UINT16 dwTableSize);
+UINT8 getClockMode(void);
+UINT16 readStrapStatus (void);
+
+void usbInitBeforePciEnum(AMDSBCFG* pConfig);
+void usbInitAfterPciInit(AMDSBCFG* pConfig);
+void usbInitMidPost(AMDSBCFG* pConfig);
+void programOhciMmioForEmulation(void);
+
+void fcInitBeforePciEnum(AMDSBCFG* pConfig);
+
+unsigned char ReadIo8 (IN unsigned short Address);
+unsigned short ReadIo16 (IN unsigned short Address);
+unsigned int ReadIo32 (IN unsigned short Address);
+void WriteIo8 (IN unsigned short Address, IN unsigned char Data);
+void WriteIo16 (IN unsigned short Address, IN unsigned short Data);
+void WriteIo32 (IN unsigned short Address, IN unsigned int Data);
+unsigned long long ReadTSC (void);
+void CpuidRead (IN unsigned int Func, IN OUT CPUID_DATA* Data);
+
+#ifndef NO_EC_SUPPORT
+void EnterEcConfig(void);
+void ExitEcConfig(void);
+void ReadEC8(UINT8 Address, UINT8* Value);
+void WriteEC8(UINT8 Address, UINT8* Value);
+void RWEC8(UINT8 Address, UINT8 AndMask, UINT8 OrMask);
+void ecPowerOnInit(BUILDPARAM *pBuildOptPtr, AMDSBCFG *pConfig);
+void ecInitBeforePciEnum(AMDSBCFG* pConfig);
+void ecInitLatePost(AMDSBCFG* pConfig);
+#endif
+UINT8 isEcPresent(void);
+
+void DispatcherEntry(void *pConfig);
+AGESA_STATUS AmdSbDispatcher(void *pConfig);
+void AMDFamily15CpuLdtStopReq(void);
+
+#endif //#ifndef _AMD_SBDEF_H_
--- /dev/null
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include "Platform.h"
+
+#ifndef B1_IMAGE
+
+BUILDPARAM DfltStaticOptions={
+ BIOS_SIZE, // BIOS Size
+ LEGACY_FREE, // Legacy Free Option
+ 0x00, // Dummy space holder
+
+ 0x00, // ECKbd disable/enable
+ 0x00, // EcChannel0 disable/enable
+ 0x00, // Dummy space holder1
+
+ SMBUS0_BASE_ADDRESS, // Smbus Base Address;
+ SMBUS1_BASE_ADDRESS, // Smbus Base Address;
+ SIO_PME_BASE_ADDRESS, // SIO PME Base Address
+ WATCHDOG_TIMER_BASE_ADDRESS, // Watchdog Timer Base Address
+ SPI_BASE_ADDRESS,
+
+ PM1_EVT_BLK_ADDRESS, // AcpiPm1EvtBlkAddr;
+ PM1_CNT_BLK_ADDRESS, // AcpiPm1CntBlkAddr;
+ PM1_TMR_BLK_ADDRESS, // AcpiPmTmrBlkAddr;
+ CPU_CNT_BLK_ADDRESS, // CpuControlBlkAddr;
+ GPE0_BLK_ADDRESS, // AcpiGpe0BlkAddr;
+ SMI_CMD_PORT, // SmiCmdPortAddr;
+ ACPI_PMA_CNT_BLK_ADDRESS, // AcpiPmaCntBlkAddr;
+
+ EC_LDN5_MAILBOX_ADDRESS,
+ EC_LDN5_IRQ,
+ EC_LDN9_MAILBOX_ADDRESS, // EC LDN9 Mailbox address
+ RESERVED_VALUE,
+ RESERVED_VALUE,
+ RESERVED_VALUE,
+ RESERVED_VALUE,
+
+ HPET_BASE_ADDRESS, // HPET Base address
+
+ SATA_IDE_MODE_SSID,
+ SATA_RAID_MODE_SSID,
+ SATA_RAID5_MODE_SSID,
+ SATA_AHCI_SSID,
+
+ OHCI0_SSID,
+ OHCI1_SSID,
+ EHCI0_SSID,
+ OHCI2_SSID,
+ OHCI3_SSID,
+ EHCI1_SSID,
+ OHCI4_SSID,
+ SMBUS_SSID,
+ IDE_SSID,
+ AZALIA_SSID,
+ LPC_SSID,
+ P2P_SSID,
+};
+
+
+/*********************************************************************************
+*
+* Routine Description: Config SB Before PCI INIT
+*
+* Arguments:
+*
+* pConfig - SBconfiguration
+*
+* Returns:
+*
+* void
+*
+**********************************************************************************/
+void sbBeforePciInit (AMDSBCFG* pConfig){
+ BUILDPARAM *pStaticOptions;
+
+ pStaticOptions = &pConfig->BuildParameters;
+ TRACE((DMSG_SB_TRACE, "CIMx - Entering sbBeforePciInit \n"));
+ commonInitEarlyBoot(pConfig);
+ commonInitEarlyPost(pConfig);
+#ifndef NO_EC_SUPPORT
+ ecInitBeforePciEnum(pConfig);
+#endif
+ usbInitBeforePciEnum(pConfig); // USB POST TIME Only
+ fcInitBeforePciEnum(pConfig); // Preinit flash controller
+ sataInitBeforePciEnum(pConfig); // Init SATA class code and PHY
+ programSubSystemIDs(pConfig, pStaticOptions); // Set subsystem/vendor ID
+
+ TRACE((DMSG_SB_TRACE, "CIMx - Exiting sbBeforePciInit \n"));
+}
+
+
+/*********************************************************************************
+*
+* Routine Description: Config SB After PCI INIT
+*
+* Arguments:
+*
+* pConfig - SBconfiguration
+*
+* Returns: void
+*
+* Reference: atiSbAfterPciInit
+*
+**********************************************************************************/
+void sbAfterPciInit(AMDSBCFG* pConfig){
+ BUILDPARAM *pStaticOptions;
+
+ TRACE((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciInit \n"));
+
+ pStaticOptions = &pConfig->BuildParameters;
+ usbInitMidPost(pConfig); //usb initialization which is required only during post
+ usbInitAfterPciInit(pConfig); // Init USB MMIO
+ sataInitAfterPciEnum(pConfig); // SATA port enumeration
+ azaliaInitAfterPciEnum(pConfig); // Detect and configure High Definition Audio
+
+ TRACE((DMSG_SB_TRACE, "CIMx - Exiting sbAfterPciInit \n"));
+}
+
+
+/*********************************************************************************
+*
+* Routine Description: Config SB during late POST
+*
+* Arguments:
+*
+* pConfig - SBconfiguration
+*
+* Returns: void
+*
+* Reference: atiSbLatePost
+*
+**********************************************************************************/
+void sbLatePost(AMDSBCFG* pConfig){
+ UINT16 dwVar;
+ BUILDPARAM *pStaticOptions;
+ pStaticOptions = &pConfig->BuildParameters;
+ TRACE((DMSG_SB_TRACE, "CIMx - Entering sbLatePost \n"));
+ ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG02, AccWidthUint16, &dwVar);
+ if (dwVar != SB7XX_DEVICE_ID){
+ // Display message that the SB is wrong and stop the system
+ TRACE((DMSG_SB_TRACE, "Current system does not have SB700 chipset. Stopping\n"));
+ for(;;);
+ }
+ commonInitLateBoot(pConfig);
+ sataInitLatePost(pConfig);
+ hpetInit(pConfig, pStaticOptions); // SB Configure HPET base and enable bit
+#ifndef NO_EC_SUPPORT
+ ecInitLatePost(pConfig);
+#endif
+}
+
+/*********************************************************************************
+*
+* Routine Description: Config SB before ACPI S3 resume PCI config device restore
+*
+* Arguments:
+*
+* pConfig - SBconfiguration
+*
+* Returns: void
+*
+* Reference: AtiSbBfPciRestore
+*
+**********************************************************************************/
+void sbBeforePciRestoreInit(AMDSBCFG* pConfig){
+ BUILDPARAM *pStaticOptions;
+
+ TRACE((DMSG_SB_TRACE, "CIMx - Entering sbBeforePciRestoreInit \n"));
+
+ pConfig->S3Resume = 1;
+
+ pStaticOptions = &pConfig->BuildParameters;
+ commonInitEarlyBoot(pConfig); // set /SMBUS/ACPI/IDE/LPC/PCIB
+ abLinkInitBeforePciEnum(pConfig); // Set ABCFG registers
+ usbInitBeforePciEnum(pConfig); // USB POST TIME Only
+ fcInitBeforePciEnum(pConfig); // Preinit flash controller
+ sataInitBeforePciEnum(pConfig);
+ programSubSystemIDs(pConfig, pStaticOptions); // Set subsystem/vendor ID
+}
+
+
+/*********************************************************************************
+*
+* Routine Description: Config SB after ACPI S3 resume PCI config device restore
+*
+* Arguments:
+*
+* pConfig - SBconfiguration
+*
+* Returns: void
+*
+* Reference: AtiSbAfPciRestore
+*
+**********************************************************************************/
+void sbAfterPciRestoreInit(AMDSBCFG* pConfig){
+ BUILDPARAM *pStaticOptions;
+
+ pConfig->S3Resume = 1;
+
+ pStaticOptions = &pConfig->BuildParameters;
+ TRACE((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciRestoreInit \n"));
+
+ commonInitLateBoot(pConfig);
+ sataInitAfterPciEnum(pConfig);
+ azaliaInitAfterPciEnum(pConfig); // Detect and configure High Definition Audio
+ hpetInit(pConfig, pStaticOptions); // SB Configure HPET base and enable bit
+ sataInitLatePost(pConfig);
+ sbSmmAcpiOn(pConfig);
+}
+
+
+/*++
+
+Routine Description:
+
+ SB config hook during ACPI_ON
+
+Arguments:
+
+ pConfig - SBconfiguration
+
+Returns:
+
+ void
+
+--*/
+
+void sbSmmAcpiOn(AMDSBCFG* pConfig){
+ UINT32 ddBar5;
+ UINT8 dbPort;
+
+ //RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+2, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT1+BIT0), 0);
+ if (getRevisionID() >= SB700_A13)
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG43, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); //Enable Legacy DMA prefetch enhancement
+
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+2, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT1+BIT0), 0);
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64+3, AccWidthUint8| S3_SAVE, ~(UINT32)BIT7, 0);
+ programOhciMmioForEmulation();
+
+ // For IDE_TO_AHCI_MODE and IDE_TO_AMD_AHCI_MODE, clear Interrupt Status register for all ports
+ ReadPCI( ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG24), AccWidthUint32, &ddBar5);
+ if ((pConfig->SataClass == IDE_TO_AHCI_MODE) || (pConfig->SataClass == IDE_TO_AMD_AHCI_MODE)){
+ for (dbPort = 0; dbPort <= 5; dbPort++) {
+ RWMEM(ddBar5 + SB_SATA_BAR5_REG110 + dbPort * 0x80, AccWidthUint32, 0x00, 0xFFFFFFFF);
+ }
+ }
+}
+
+
+UINT32 CallBackToOEM(UINT32 Func, UINTN Data,AMDSBCFG* pConfig){
+ UINT32 Result=0;
+ TRACE((DMSG_SB_TRACE,"OEM Call Back Func [%x] Data [%x]\n",Func,Data));
+ if (pConfig->StdHeader.pCallBack==NULL)
+ return Result;
+ Result = (*(pConfig->StdHeader.pCallBack))(Func,Data,pConfig);
+ TRACE((DMSG_SB_TRACE,"SB Hook Status [%x]\n",Result));
+ return Result;
+}
+
+#endif
--- /dev/null
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include "Platform.h"
+
+REG8MASK sbPorInitPciTable[] = {
+ // SMBUS Device(Bus 0, Dev 20, Func 0)
+ {0x00, SMBUS_BUS_DEV_FUN, 0},
+ {SB_SMBUS_REGD0+2, 0x00, 0x01},
+ {SB_SMBUS_REG40, 0x00, 0x44},
+ {SB_SMBUS_REG40+1, 0xFF, 0xE9}, //Set smbus pci config 0x40[14]=1, This bit is used for internal bus flow control.
+ {SB_SMBUS_REG64, 0x00, 0xBF}, //SB_SMBUS_REG64[13]=1, delays back to back interrupts to the CPU
+ {SB_SMBUS_REG64+1, 0x00, 0x78},
+ {SB_SMBUS_REG64+2, ~(UINT8)BIT6, 0x9E},
+ {SB_SMBUS_REG64+3, 0x0F, 0x02},
+ {SB_SMBUS_REG68+1, 0x00, 0x90},
+ {SB_SMBUS_REG6C, 0x00, 0x20},
+ {SB_SMBUS_REG78, 0x00, 0xFF},
+ {SB_SMBUS_REG04, 0x00, 0x07},
+ {SB_SMBUS_REG04+1, 0x00, 0x04},
+ {SB_SMBUS_REGE1, 0x00, 0x99}, //RPR recommended setting, Sections "SMBUS Pci Config" & "IMC Access Control"
+ {SB_SMBUS_REGAC, ~(UINT8)BIT4, BIT1},
+ {SB_SMBUS_REG60+2, ~(UINT8)(BIT1+BIT0) , 0x24}, // Disabling Legacy USB Fast SMI# Smbus_PCI_config 0x62 [5] = 1. Legacy USB
+ // can request SMI# to be sent out early before IO completion.
+ // Some applications may have problems with this feature. The BIOS should set this bit
+ // to 1 to disable the feature. Enabling Legacy Interrupt Smbus_PCI_Config 0x62[2]=1.
+ {0xFF, 0xFF, 0xFF},
+
+ // LPC Device(Bus 0, Dev 20, Func 3)
+ {0x00, LPC_BUS_DEV_FUN, 0},
+ {SB_LPC_REG40, 0x00, 0x04},
+ {SB_LPC_REG48, 0x00, 0x07},
+ {SB_LPC_REG4A, 0x00, 0x20}, // Port Enable for IO Port 80h.
+ {SB_LPC_REG78, ~(UINT8)BIT0, 0x00},
+ {SB_LPC_REG7C, 0x00, 0x05},
+ {SB_LPC_REGB8+3, ~(UINT8)BIT0, BIT7+BIT6+BIT5+BIT3+BIT0}, //RPR recommended setting,Section "IO / Mem Decoding" & "SPI bus"
+ {0xFF, 0xFF, 0xFF},
+
+ // P2P Bridge(Bus 0, Dev 20, Func 4)
+ {0x00, SBP2P_BUS_DEV_FUN, 0},
+ {SB_P2P_REG40, 0x00, 0x26}, // Enabling PCI-bridge subtractive decoding & PCI Bus 64-byte DMA Read Access
+ {SB_P2P_REG4B, 0xFF, BIT6+BIT7+BIT4},
+ {SB_P2P_REG1C, 0x00, 0x11},
+ {SB_P2P_REG1D, 0x00, 0x11},
+ {SB_P2P_REG04, 0x00, 0x21},
+ {SB_P2P_REG50, 0x02, 0x01}, // PCI Bridge upstream dual address window
+ {0xFF, 0xFF, 0xFF},
+};
+
+
+REG8MASK sbA13PorInitPciTable[] = {
+ // SMBUS Device(Bus 0, Dev 20, Func 0)
+ {0x00, SMBUS_BUS_DEV_FUN, 0},
+ {SB_SMBUS_REG43, ~(UINT8)BIT3, 0x00}, //Make some hidden registers of smbus visible.
+ {SB_SMBUS_REG38, (UINT8)~BIT7, 00},
+ {SB_SMBUS_REGAC+1, ~(UINT8)BIT5, 0}, //Enable SATA test/enhancement mode
+ {SB_SMBUS_REG43, 0xFF, BIT3}, //Make some hidden registers of smbus invisible.
+ {0xFF, 0xFF, 0xFF},
+};
+
+
+REG8MASK sbA14PorInitPciTable[] = {
+ // LPC Device(Bus 0, Dev 20, Func 3)
+ {0x00, LPC_BUS_DEV_FUN, 0},
+ {SB_LPC_REG8C+2, ~(UINT8)BIT1, 00},
+ {0xFF, 0xFF, 0xFF},
+};
+
+REG8MASK sbPorPmioInitTbl[] = {
+ // index andmask ormask
+ {SB_PMIO_REG67, 0xFF, 0x02},
+ {SB_PMIO_REG37, 0xFF, 0x04}, // Configure pciepme as rising edge
+ {SB_PMIO_REG50, 0x00, 0xE0}, // Enable CPU_STP (except S5) & PCI_STP
+ {SB_PMIO_REG60, 0xFF, 0x20}, // Enable Speaker
+ {SB_PMIO_REG65, (UINT8)~(BIT4+BIT7), 0x00},// Clear PM_IO 0x65[4] UsbResetByPciRstEnable to avoid S3 reset to reset USB
+ {SB_PMIO_REG55, ~(UINT8)BIT6, 0x07}, // Select CIR wake event to ACPI.GEVENT[23] & Clear BIT6 SoftPciRst for safety
+ {SB_PMIO_REG66, 0xFF, BIT5}, // Configure keyboard reset to generate pci reset
+ {SB_PMIO_REGB2, 0xFF, BIT7},
+ {SB_PMIO_REG0E, 0xFF, BIT3}, // Enable ACPI IO decoding
+ {SB_PMIO_REGD7, 0xF6, 0x80},
+ {SB_PMIO_REG7C, 0xFF, BIT4}, // enable RTC AltCentury register
+
+ {SB_PMIO_REG75, 0xC0, 0x05}, // PME_TURN_OFF_MSG during ASF shutdown
+ {SB_PMIO_REG52, 0xC0, 0x08},
+
+ {SB_PMIO_REG8B, 0x00, 0x10},
+ {SB_PMIO_REG69, 0xF9, 0x01 << 1}, // [Updated RPR] Set default WDT resolution to 10ms
+};
+
+REG8MASK sbA13PorPmioInitTbl[]={
+ // index andmask ormask
+ {SB_PMIO_REGD7, 0xFF, BIT5+BIT0}, //Fixes for TT SB00068 & SB01054 (BIT5 & BIT0 correspondingly)
+ {SB_PMIO_REGBB, (UINT8)~BIT7, BIT6+BIT5}, //Fixes for TT SB00866 & SB00696 (BIT6 & BIT5 correspondingly)
+ // Always clear [7] to begin with SP5100 C1e disabled
+
+// {SB_PMIO_REG65, 0xFF, BIT7},
+// {SB_PMIO_REG75, 0xC0, 0x01}, // PME_TURN_OFF_MSG during ASF shutdown
+// {SB_PMIO_REG52, 0xC0, 0x02},
+
+};
+
+
+void sbPowerOnInit (AMDSBCFG *pConfig){
+ UINT8 dbVar0, dbVar1, dbValue;
+ UINT16 dwTempVar;
+ BUILDPARAM *pBuildOptPtr;
+
+ TRACE((DMSG_SB_TRACE, "CIMx - Entering sbPowerOnInit \n"));
+
+ setRevisionID();
+ ReadPCI(((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG02), AccWidthUint16 | S3_SAVE, &dwTempVar);
+ if (dwTempVar == SB750_SATA_DEFAULT_DEVICE_ID)
+ RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint8 | S3_SAVE, 0xFF, 0x01);
+
+ // Set A-Link bridge access address. This address is set at device 14h, function 0,
+ // register 0f0h. This is an I/O address. The I/O address must be on 16-byte boundry.
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGF0, AccWidthUint32, 00, ALINK_ACCESS_INDEX);
+
+ writeAlink(0x80000004, 0x04); // RPR 3.3 Enabling upstream DMA Access
+ writeAlink(0x30, 0x10); //AXINDC 0x10[9]=1, Enabling Non-Posted memory write for K8 platform.
+ writeAlink(0x34, readAlink(0x34) | BIT9);
+
+ if (!(pConfig->ResetCpuOnSyncFlood)){
+ //Enable reset on sync flood
+ writeAlink( (UINT32)( ((UINT32)SB_AB_REG10050) | ((UINT32)ABCFG << 30)),
+ (UINT32)( readAlink((((UINT32)SB_AB_REG10050) | ((UINT32)ABCFG << 30))) | ((UINT32)BIT2) ));
+ }
+
+ pBuildOptPtr = &(pConfig->BuildParameters);
+
+ WritePCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG90, AccWidthUint32 | S3_SAVE, &(pBuildOptPtr->Smbus0BaseAddress) );
+
+ dwTempVar = pBuildOptPtr->Smbus1BaseAddress & (UINT16)~BIT0;
+ if( dwTempVar != 0 ){
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG58, AccWidthUint16 | S3_SAVE, 00, (dwTempVar|BIT0));
+ // Disable ASF Slave controller on SB700 rev A15.
+ if (getRevisionID() == SB700_A15) {
+ RWIO((dwTempVar+0x0D), AccWidthUint8, (UINT8)~BIT6, BIT6);
+ }
+ }
+
+ WritePCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pBuildOptPtr->SioPmeBaseAddress));
+ RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F,(pBuildOptPtr->SpiRomBaseAddress));
+
+ WritePMIO(SB_PMIO_REG20, AccWidthUint16, &(pBuildOptPtr->AcpiPm1EvtBlkAddr));
+ WritePMIO(SB_PMIO_REG22, AccWidthUint16, &(pBuildOptPtr->AcpiPm1CntBlkAddr));
+ WritePMIO(SB_PMIO_REG24, AccWidthUint16, &(pBuildOptPtr->AcpiPmTmrBlkAddr));
+ WritePMIO(SB_PMIO_REG26, AccWidthUint16, &(pBuildOptPtr->CpuControlBlkAddr));
+ WritePMIO(SB_PMIO_REG28, AccWidthUint16, &(pBuildOptPtr->AcpiGpe0BlkAddr));
+ WritePMIO(SB_PMIO_REG2A, AccWidthUint16, &(pBuildOptPtr->SmiCmdPortAddr));
+ WritePMIO(SB_PMIO_REG2C, AccWidthUint16, &(pBuildOptPtr->AcpiPmaCntBlkAddr));
+ RWPMIO(SB_PMIO_REG2E, AccWidthUint16, 0x00,(pBuildOptPtr->SmiCmdPortAddr)+8);
+ WritePMIO(SB_PMIO_REG6C, AccWidthUint32, &(pBuildOptPtr->WatchDogTimerBase));
+
+ //Program power on pci init table
+ programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbPorInitPciTable[0]), sizeof(sbPorInitPciTable)/sizeof(REG8MASK) );
+ //Program power on pmio init table
+ programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sbPorPmioInitTbl[0]), (sizeof(sbPorPmioInitTbl)/sizeof(REG8MASK)) );
+
+ dbValue = 0x00;
+ ReadIO (SB_IOMAP_REGC14, AccWidthUint8, &dbValue);
+ dbValue &= 0xF3;
+ WriteIO (SB_IOMAP_REGC14, AccWidthUint8, &dbValue);
+
+ dbValue = 0x0A;
+ WriteIO (SB_IOMAP_REG70, AccWidthUint8, &dbValue);
+ ReadIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
+ dbValue &= 0xEF;
+ WriteIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue);
+
+
+ if (getRevisionID() >= SB700_A13){
+ programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbA13PorInitPciTable[0]), sizeof(sbA13PorInitPciTable)/sizeof(REG8MASK) );
+ programPmioByteTable( (REG8MASK *)FIXUP_PTR(&sbA13PorPmioInitTbl[0]), (sizeof(sbA13PorPmioInitTbl)/sizeof(REG8MASK)) );
+ }
+
+ if ((getRevisionID() >= SB700_A14) )
+ programPciByteTable( (REG8MASK*)FIXUP_PTR(&sbA14PorInitPciTable[0]), sizeof(sbA14PorInitPciTable)/sizeof(REG8MASK) );
+
+ if ( (getRevisionID() >= SB700_A14) && ( (pConfig->TimerClockSource == 1) || (pConfig->TimerClockSource == 2) )){
+ ReadPMIO(SB_PMIO_REGD4, AccWidthUint8, &dbVar1);
+ if (!(dbVar1 & BIT6)){
+ RWPMIO(SB_PMIO_REGD4, AccWidthUint8, 0xFF, BIT6);
+ pConfig->RebootRequired=1;
+ }
+ }
+
+ if (getRevisionID() > SB700_A11) {
+ if (pConfig->PciClk5 == 1)
+ RWPMIO(SB_PMIO_REG41, AccWidthUint8, ~(UINT32)BIT1, BIT1); // Enabled PCICLK5 for A12
+ }
+
+ dbVar0 = (pBuildOptPtr->BiosSize + 1) & 7;
+ if (dbVar0 > 4) {
+ dbVar0 = 0;
+ }
+ //KZ [061811]-It's used wrong BIOS SIZE for Coreboot. RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint8 | S3_SAVE, 0x00, 0xF8 << dbVar0);
+
+ if (pConfig->Spi33Mhz)
+ //spi reg0c[13:12] to 01h to run spi 33Mhz in system bios
+ RWMEM((pBuildOptPtr->SpiRomBaseAddress)+SB_SPI_MMIO_REG0C,AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT13+BIT12), BIT12);
+
+ //SB internal spread spectrum settings. A reboot is required if the spread spectrum settings have to be changed
+ //from the existing value.
+ ReadPMIO(SB_PMIO_REG42, AccWidthUint8, &dbVar0);
+ if (pConfig->SpreadSpectrum != (dbVar0 >> 7) )
+ pConfig->RebootRequired = 1;
+ if (pConfig->SpreadSpectrum)
+ RWPMIO(SB_PMIO_REG42, AccWidthUint8, ~(UINT32)BIT7, BIT7);
+ else
+ RWPMIO(SB_PMIO_REG42, AccWidthUint8, ~(UINT32)BIT7, 0);
+
+ if ( !(pConfig->S3Resume) ){
+ //To detect whether internal clock chip is used, do the following procedure
+ //set PMIO_B2[7]=1, then read PMIO_B0[4]; if it is 1, we are strapped to CLKGEN mode.
+ //if it is 0, we are using clock chip on board.
+ RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT7);
+
+ //Do the following programming only for SB700-A11.
+ //1. Set PMIO_B2 [7]=1 and read B0 and B1 and save those values.
+ //2. Set PMIO_B2 [7]=0
+ //3. Write the saved values from step 1, back to B0 and B1.
+ //4. Set PMIO_B2 [6]=1.
+ ReadPMIO(SB_PMIO_REGB0, AccWidthUint16, &dwTempVar);
+ if (getRevisionID() == SB700_A11){
+ RWPMIO(SB_PMIO_REGB2, AccWidthUint8, ~(UINT32)BIT7, 00);
+ WritePMIO(SB_PMIO_REGB0, AccWidthUint16, &dwTempVar);
+ RWPMIO(SB_PMIO_REGB2, AccWidthUint8, 0xFF, BIT6);
+ }
+
+ if (!(dwTempVar & BIT4)){
+ RWPMIO(SB_PMIO_REGD0, AccWidthUint8, ~(UINT32)BIT0, 0); //Enable PLL2
+
+ //we are in external clock chip on the board
+ if (pConfig->UsbIntClock == CIMX_OPTION_ENABLED){
+ //Configure usb clock to come from internal PLL
+ RWPMIO(SB_PMIO_REGD2, AccWidthUint8, 0xFF, BIT3); //Enable 48Mhz clock from PLL2
+ RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, BIT4); //Tell USB PHY to use internal 48Mhz clock from PLL2
+ }
+ else{
+ //Configure usb clock to come from external clock
+ RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, 0); //Tell USB PHY to use external 48Mhz clock from PLL2
+ RWPMIO(SB_PMIO_REGD2, AccWidthUint8, ~(UINT32)BIT3, 00); //Disable 48Mhz clock from PLL2
+ }
+ }
+ else{
+ //we are using internal clock chip on this board
+ if (pConfig->UsbIntClock == CIMX_OPTION_ENABLED){
+ //Configure usb clock to come from internal PLL
+ RWPMIO(SB_PMIO_REGD2, AccWidthUint8, ~(UINT32)BIT3, 0); //Enable 48Mhz clock from PLL2
+ RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, BIT4); //Tell USB PHY to use internal 48Mhz clock from PLL2
+ }
+ else{
+ //Configure usb clock to come from external clock
+ RWPMIO(SB_PMIO_REGBD, AccWidthUint8, ~(UINT32)BIT4, 0); //Tell USB PHY to use external 48Mhz clock from PLL2
+ RWPMIO(SB_PMIO_REGD2, AccWidthUint8, ~(UINT32)BIT3, BIT3); //Disable 48Mhz clock from PLL2
+ }
+ }
+
+ ReadPMIO(SB_PMIO_REG43, AccWidthUint8, &dbVar0);
+ RWPMIO(SB_PMIO_REG43, AccWidthUint8, ~(UINT32)(BIT6+BIT5+BIT0), (pConfig->UsbIntClock << 5));
+ //Check whether our usb clock settings changed compared to previous boot, if yes then we need to reboot.
+ if ( (dbVar0 & BIT0) || ( (pConfig->UsbIntClock) != ((dbVar0 & (BIT6+BIT5)) >> 5)) ) pConfig->RebootRequired = 1;
+ }
+
+ if (pBuildOptPtr->LegacyFree) //if LEGACY FREE system
+ RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C000);
+ else
+ RWPCI(((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0xFF03FFD5);
+
+ if ( (getRevisionID() == SB700_A14) || (getRevisionID() == SB700_A13)){
+ RWPMIO(SB_PMIO_REG65, AccWidthUint8, 0xFF, BIT7);
+ RWPMIO(SB_PMIO_REG75, AccWidthUint8, 0xC0, BIT0);
+ RWPMIO(SB_PMIO_REG52, AccWidthUint8, 0xC0, BIT1);
+ }
+
+ if (getRevisionID() >= SB700_A15) {
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40+3, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT3), 0);
+ //Enable unconditional shutdown fix in A15
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG38+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT4);
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40+3, AccWidthUint8 | S3_SAVE, 0xFF, BIT3);
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG06+1, AccWidthUint8 | S3_SAVE, 0xFF, 0xD0);
+ }
+
+ // [Updated RPR] Set ImcHostSmArbEn(SMBUS:0xE1[5]) only when IMC is enabled
+ if (isEcPresent()) {
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REGE1, AccWidthUint8 | S3_SAVE, 0xFF, BIT5);
+ }
+
+ //According to AMD Family 15h Models 00h-0fh processor BKDG section 2.12.8 LDTSTOP requirement
+ // to program VID/FID LDTSTP# duration selection register
+ AMDFamily15CpuLdtStopReq();
+
+#ifndef NO_EC_SUPPORT
+ ecPowerOnInit(pBuildOptPtr, pConfig);
+#endif
+}
+
+
+void setRevisionID(void){
+ UINT8 dbVar0, dbVar1;
+
+ ReadPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, &dbVar0);
+ ReadPMIO(SB_PMIO_REG53, AccWidthUint8, &dbVar1);
+ if ( (dbVar0 == 0x39) && (dbVar1 & BIT6) && !(dbVar1 & BIT7)){
+ RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40), AccWidthUint8, ~(UINT32)BIT0, BIT0);
+ RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, 00, SB700_A12);
+ RWPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG40), AccWidthUint8, ~(UINT32)BIT0, 00);
+ }
+ ReadPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, &dbVar0);
+}
+
+
+UINT8 getRevisionID(void){
+ UINT8 dbVar0;
+
+ ReadPCI(((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG08), AccWidthUint8, &dbVar0);
+ return dbVar0;
+}
+
+
+void AMDFamily15CpuLdtStopReq(void) {
+ CPUID_DATA CpuId;
+ CPUID_DATA CpuId_Brand;
+ UINT8 dbVar0, dbVar1, dbVar2;
+
+ //According to AMD Family 15h Models 00h-0fh processor BKDG section 2.12.8 LDTSTOP requirement
+ //to program VID/FID LDTSTP# duration selection register
+ //If any of the following system configuration properties are true LDTSTP# assertion time required by the processor is 10us:
+ // 1. Any link in the system operating at a Gen 1 Frequency.
+ // 2. Also for server platform (G34/C32) set PM_REG8A[6:4]=100b (16us)
+
+ CpuidRead (0x01, &CpuId);
+ CpuidRead (0x80000001, &CpuId_Brand); //BrandID, to read socket type
+ if ((CpuId.REG_EAX & 0xFFFFFF00) == 0x00600F00) {
+
+ //Program to Gen 3 default value - 001b
+ RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x10); //set [6:4]=001b
+
+ //Any link in the system operating at a Gen 1 Frequency.
+ //Check Link 0 - Link connected regsister
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REG98), AccWidthUint8, &dbVar2);
+ dbVar2 = dbVar2 & 0x01;
+
+ if(dbVar2 == 0x01) {
+ //Check Link 0 - Link Frequency Freq[4:0]
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REG89), AccWidthUint8, &dbVar0);
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REG9C), AccWidthUint8, &dbVar1);
+ dbVar0 = dbVar0 & 0x0F; //Freq[3:0]
+ dbVar1 = dbVar1 & 0x01; //Freq[4]
+ dbVar0 = (dbVar1 << 4) | dbVar0; //Freq[4:0]
+ //Value 6 or less indicate Gen1
+ if(dbVar0 <= 0x6) {
+ RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b
+ }
+ }
+
+ //Check Link 1 - Link connected regsister
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGB8), AccWidthUint8, &dbVar2);
+ dbVar2 = dbVar2 & 0x01;
+ if(dbVar2 == 0x01) {
+ //Check Link 1 - Link Frequency Freq[4:0]
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGA9), AccWidthUint8, &dbVar0);
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGBC), AccWidthUint8, &dbVar1);
+ dbVar0 = dbVar0 & 0x0F; //Freq[3:0]
+ dbVar1 = dbVar1 & 0x01; //Freq[4]
+ dbVar0 = (dbVar1 << 4) | dbVar0; //Freq[4:0]
+ //Value 6 or less indicate Gen1
+ if(dbVar0 <= 0x6) {
+ RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b
+ }
+ }
+
+ //Check Link 2 - Link connected regsister
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGD8), AccWidthUint8, &dbVar2);
+ dbVar2 = dbVar2 & 0x01;
+ if(dbVar2 == 0x01) {
+ //Check Link 2 - Link Frequency Freq[4:0]
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGC9), AccWidthUint8, &dbVar0);
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGDC), AccWidthUint8, &dbVar1);
+ dbVar0 = dbVar0 & 0x0F; //Freq[3:0]
+ dbVar1 = dbVar1 & 0x01; //Freq[4]
+ dbVar0 = (dbVar1 << 4) | dbVar0; //Freq[4:0]
+ //Value 6 or less indicate Gen1
+ if(dbVar0 <= 0x6) {
+ RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b
+ }
+ }
+
+ //Check Link 3 - Link connected regsister
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGF8), AccWidthUint8, &dbVar2);
+ dbVar2 = dbVar2 & 0x01;
+ if(dbVar2 == 0x01) {
+ //Check Link 3 - Link Frequency Freq[4:0]
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGE9), AccWidthUint8, &dbVar0);
+ ReadPCI(((HT_LINK_BUS_DEV_FUN << 16) + HT_LINK_REGFC), AccWidthUint8, &dbVar1);
+ dbVar0 = dbVar0 & 0x0F; //Freq[3:0]
+ dbVar1 = dbVar1 & 0x01; //Freq[4]
+ dbVar0 = ((dbVar1 << 4) | dbVar0); //Freq[4:0]
+ //Value 6 or less indicate Gen1
+ if(dbVar0 <= 0x6) {
+ RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b
+ }
+ }
+
+ // Server platform (G34/C32) set PM_REG8A[6:4]=100b (16us)
+ if(((CpuId_Brand.REG_EBX & 0xF0000000) == 0x30000000) || ((CpuId_Brand.REG_EBX & 0xF0000000) == 0x50000000)) {
+ RWPMIO(SB_PMIO_REG8A, AccWidthUint8, 0x8F, 0x40); //set [6:4]=100b
+ }
+ }
+
+}
+
--- /dev/null
+/*;********************************************************************************
+;
+; Copyright (C) 2012 Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; * Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; * Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; * Neither the name of Advanced Micro Devices, Inc. nor the names of
+; its contributors may be used to endorse or promote products derived
+; from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*********************************************************************************/
+
+#ifndef _AMD_SBTYPE_H_
+#define _AMD_SBTYPE_H_
+
+#pragma pack(push,1)
+
+typedef UINT32 (*CIM_HOOK_ENTRY)(UINT32 Param1, UINTN Param2, void* pConfig);
+typedef void (*SMM_SERVICE_ROUTINE) (void);
+
+typedef struct _STDCFG{
+ UINT32 pImageBase;
+ UINT32 pPcieBase;
+ UINT8 Func;
+ CIM_HOOK_ENTRY pCallBack;
+ UINT32 pB2ImageBase;
+}STDCFG; //Size of stdcfg is 17 bytes
+
+typedef struct _BUILDPARAM
+{
+ UINT16 BiosSize:3; //0-1MB, 1-2MB, 2-4MB, 3-8MB, 7-512KB, all other values reserved
+ UINT16 LegacyFree:1;
+ UINT16 Dummy0:12;
+
+ UINT16 EcKbd:1;
+ UINT16 EcChannel0:1;
+ UINT16 Dummy1:14;
+
+ UINT32 Smbus0BaseAddress;
+ UINT16 Smbus1BaseAddress;
+ UINT32 SioPmeBaseAddress;
+ UINT32 WatchDogTimerBase;
+ UINT32 SpiRomBaseAddress;
+
+ UINT16 AcpiPm1EvtBlkAddr;
+ UINT16 AcpiPm1CntBlkAddr;
+ UINT16 AcpiPmTmrBlkAddr;
+ UINT16 CpuControlBlkAddr;
+ UINT16 AcpiGpe0BlkAddr;
+ UINT16 SmiCmdPortAddr;
+ UINT16 AcpiPmaCntBlkAddr;
+
+ UINT16 EcLdn5MailBoxAddr;
+ UINT8 EcLdn5Irq;
+ UINT16 EcLdn9MailBoxAddr;
+ UINT32 ReservedDword0;
+ UINT32 ReservedDword1;
+ UINT32 ReservedDword2;
+ UINT32 ReservedDword3;
+
+ UINT32 HpetBase; //HPET Base address
+
+ UINT32 SataIDESsid;
+ UINT32 SataRAIDSsid;
+ UINT32 SataRAID5Ssid;
+ UINT32 SataAHCISsid;
+
+ UINT32 Ohci0Ssid;
+ UINT32 Ohci1Ssid;
+ UINT32 Ehci0Ssid;
+ UINT32 Ohci2Ssid;
+ UINT32 Ohci3Ssid;
+ UINT32 Ehci1Ssid;
+ UINT32 Ohci4Ssid;
+ UINT32 SmbusSsid;
+ UINT32 IdeSsid;
+ UINT32 AzaliaSsid;
+ UINT32 LpcSsid;
+ UINT32 P2PSsid;
+}BUILDPARAM;
+
+typedef struct _CODECENTRY{
+ UINT8 Nid;
+ UINT32 Byte40;
+}CODECENTRY;
+
+typedef struct _CODECTBLLIST{
+ UINT32 CodecID;
+ CODECENTRY* CodecTablePtr;
+}CODECTBLLIST;
+
+typedef struct _AMDSBCFG
+{
+ STDCFG StdHeader; //offset 0:16 - 17 bytes
+ //UINT32 MsgXchgBiosCimx; //offset 17:20 - 4 bytes
+ UINT32 S3Resume:1;
+ UINT32 RebootRequired:1;
+ UINT32 Spi33Mhz:1;
+ UINT32 SpreadSpectrum:1;
+ UINT32 UsbIntClock:1; //0:Use external clock, 1:Use internal clock
+ UINT32 PciClk5:1; //0:disable, 1:enable
+ UINT32 TimerClockSource:2; //0:100Mhz PCIE Reference clock (same as SB700-A12,
+ //1: 14Mhz using 25M_48M_66M_OSC pin, 2: Auto (100Mhz for SB700-A12, 14Mhz
+ //using 25M_48m_66m_0SC pin for SB700-A14, SB710, SP5100
+ UINT32 ResetCpuOnSyncFlood:1; //0:Reset CPU on Sync Flood, 1:Do not reset CPU on sync flood
+ UINT32 MsgXchgBiosCimxDummyBB:23;
+
+ /** BuildParameters - The STATIC platform information for CIMx Module. */
+ BUILDPARAM BuildParameters;
+
+ //SATA Configuration
+ UINT32 SataController :1; //0, 0:disable 1:enable* //offset 25:28 - 4 bytes
+ UINT32 SataClass :3; //1, 0:IDE* 1:RAID 2:AHCI 3:Legacy IDE 4:IDE->AHCI 5:AMD_AHCI, 6:IDE->AMD_AHCI
+ UINT32 SataSmbus :1; //4, 0:disable 1:enable*
+ UINT32 SataAggrLinkPmCap:1; //5, 0:OFF 1:ON
+ UINT32 SataPortMultCap :1; //6, 0:OFF 1:ON
+ UINT32 SataReserved :2; //8:7, Reserved
+ UINT32 SataClkAutoOff :1; //9, AutoClockOff for IDE modes 0:Disabled, 1:Enabled
+ UINT32 SataIdeCombinedMode :1; //10, SataIDECombinedMode 0:Disabled, 1:Enabled
+ UINT32 SataIdeCombMdPriSecOpt:1; //11, Combined Mode, SATA as primary or secondary 0:primary 1:secondary
+ UINT32 SataReserved1 :6; //17:12, Not used currently
+ UINT32 SataEspPort :6; //23:18 SATA port is external accessiable on a signal only connector (eSATA:)
+ UINT32 SataClkAutoOffAhciMode:1; //24: Sata Auto clock off for AHCI mode
+ UINT32 SataHpcpButNonESP:6; //25:30 Hotplug capable but not e-sata port
+ UINT32 SataHideUnusedPort:1; //31, 0:Disabled 1:Enabled
+
+ //Flash Configuration //offset 29:30 - 2 bytes
+ UINT16 FlashController :1; //0, 0:disable FC & enable IDE 1:enable FC & disable IDE
+ UINT16 FlashControllerMode:1; //1, 0:Flash behind SATA 1:Flash as standalone
+ UINT16 FlashHcCrc:1; //2,
+ UINT16 FlashErrorMode:1; //3
+ UINT16 FlashNumOfBankMode:1; //4
+ UINT16 FlashDummy:11; //5:15
+
+ //USB Configuration //offset 31:32 - 2 bytes
+ UINT16 Usb1Ohci0 :1; //0, 0:disable 1:enable* Bus 0 Dev 18 Func0
+ UINT16 Usb1Ohci1 :1; //1, 0:disable 1:enable* Bus 0 Dev 18 Func1
+ UINT16 Usb1Ehci :1; //2, 0:disable 1:enable* Bus 0 Dev 18 Func2
+ UINT16 Usb2Ohci0 :1; //3, 0:disable 1:enable* Bus 0 Dev 19 Func0
+ UINT16 Usb2Ohci1 :1; //4, 0:disable 1:enable* Bus 0 Dev 19 Func1
+ UINT16 Usb2Ehci :1; //5, 0:disable 1:enable* Bus 0 Dev 19 Func2
+ UINT16 Usb3Ohci :1; //6, 0:disable 1:enable* Bus 0 Dev 20 Func5
+ UINT16 UsbOhciLegacyEmulation:1; //7, 0:Enabled, 1:Disabled
+ UINT16 UsbDummy :8; //8:15
+
+ //Azalia Configuration //offset 33:36 - 4 bytes
+ UINT32 AzaliaController:2; //0, 0:AUTO, 1:disable, 2:enable
+ UINT32 AzaliaPinCfg :1; //2, 0:disable, 1:enable
+ UINT32 AzaliaFrontPanel:2; //3, 0:AUTO, 1:disable, 2:enable
+ UINT32 FrontPanelDetected:1; //5, 0:Not detected, 1:detected
+ UINT32 AzaliaSdin0 :2; //6
+ UINT32 AzaliaSdin1 :2; //8
+ UINT32 AzaliaSdin2 :2; //10
+ UINT32 AzaliaSdin3 :2; //12
+ UINT32 AzaliaDummy :18; //14:31
+
+ CODECTBLLIST* pAzaliaOemCodecTablePtr; //offset 37:40 - 4 bytes
+ UINT32 pAzaliaOemFpCodecTableptr; //offset 41:44 - 4 bytes
+
+ //Miscellaneous Configuration //offset 45:48 - 4 bytes
+ UINT32 MiscReserved0:1; //0
+ UINT32 HpetTimer:1; //1, 0:disable 1:enable
+ UINT32 PciClks:5; //2:6, 0:disable, 1:enable
+ UINT32 MiscReserved1:3; //9:7, Reserved
+ UINT32 IdeController:1; //10, 0:Enable, 1:Disabled
+ UINT32 MobilePowerSavings:1; //11, 0:Disable, 1:Enable Power saving features especially for Mobile platform
+ UINT32 ExternalRTCClock:1; //12, 0:Don't Shut Off, 1:Shut Off, external RTC clock
+ UINT32 AcpiS1Supported:1; //13, 0:S1 not supported, 1:S1 supported
+ UINT32 AnyHT200MhzLink:1; //14, 0:No HT 200Mhz Link in platform, 1; There is 200MHz HT Link in platform
+ UINT32 WatchDogTimerEnable:1; //15, [0]: WDT disabled; 1: WDT enabled
+ UINT32 MTC1e:1; //16, Message Triggered C1e - 0:Disabled*, 1:Enabled
+ UINT32 HpetMsiDis:1; //17, HPET MSI - 0:Enable HPET MSI, 1:Disable
+ UINT32 EhciDataCacheDis:1; //18, 0:Date Cache Enabled, 1:Date Cache Disabled /** EHCI Async Data Cache Disable */
+ UINT32 MiscDummy:13;
+
+ UINT32 AsmAslInfoExchange0; //offset 49:52 - 4 bytes
+ UINT32 AsmAslInfoExchange1; //offset 53:56
+
+ //DebugOptions_1 //offset 57:60
+ UINT32 FlashPinConfig :1; //0, 0:desktop mode 1:mobile mode
+ UINT32 UsbPhyPowerDown :1; //1
+ UINT32 PcibClkStopOverride :10; //11:2
+ UINT32 Debug1Reserved0:4; //15:11
+ UINT32 AzaliaSnoop:1; //16 0:Disable, 1:Enable
+ UINT32 SataSscPscCap:1; //17, 0:Enable SSC/PSC capability, 1:Disable SSC/PSC capability
+ UINT32 SataPortMode:6; //23:18, 0: AUTO, 1:Force SATA port(6/5/4/3/2/1) to GEN1
+ UINT32 SataPhyWorkaround:2; //25:24, 0:AUTO, 1:Enable, 2:Disable
+ UINT32 Gen1DeviceShutdownDuringPhyWrknd:2; //27:26, 0:AUTO, 1:YES, 2:NO
+ UINT32 OhciIsoOutPrefetchDis:1; //28, 0:Enable OHCI ISO OUT prefetch, 1:Disable
+ UINT32 Debug1Dummy:3; //
+
+ //DebugOptions_2
+ UINT32 PcibAutoClkCtrlLow:16;
+ UINT32 PcibAutoClkCtrlHigh:16;
+
+ //TempMMIO
+ UINT32 TempMMIO:32;
+
+}AMDSBCFG;
+
+typedef struct _SMMSERVICESTRUC
+{
+ UINT8 enableRegNum;
+ UINT8 enableBit;
+ UINT8 statusRegNum;
+ UINT8 statusBit;
+ CHAR8 *debugMessage;
+ SMM_SERVICE_ROUTINE serviceRoutine;
+}SMMSERVICESTRUC;
+
+typedef struct _ABTblEntry
+{
+ UINT8 regType;
+ UINT32 regIndex;
+ UINT32 regMask;
+ UINT32 regData;
+}ABTBLENTRY;
+
+#define PCI_ADDRESS(bus,dev,func,reg) \
+(UINT32) ( (((UINT32)bus) << 24) + (((UINT32)dev) << 19) + (((UINT32)func) << 16) + ((UINT32)reg) )
+
+typedef UINT32 CIM_STATUS;
+#define CIM_SUCCESS 0x00000000
+#define CIM_ERROR 0x80000000
+#define CIM_UNSUPPORTED 0x80000001
+
+#pragma pack(pop)
+
+#define CIMX_OPTION_DISABLED 0
+#define CIMX_OPTION_ENABLED 1
+
+#endif // _AMD_SBTYPE_H_
--- /dev/null
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include "Platform.h"
+
+SMMSERVICESTRUC smmItemsTable[]={
+ {SB_PMIO_REG0E, BIT2, SB_PMIO_REG0F, BIT2, (CHAR8 *)"Software SMI through SMI CMD port \n ", softwareSMIservice},
+ {SB_PMIO_REG00, BIT4, SB_PMIO_REG01, BIT4, (CHAR8 *)"Software initiated SMI \n ", NULL},
+ {SB_PMIO_REG02, 0xFF, SB_PMIO_REG05, 0xFF, (CHAR8 *)"SMI on IRQ15-8 \n ", NULL},
+ {SB_PMIO_REG03, 0xFF, SB_PMIO_REG06, 0xFF, (CHAR8 *)"SMI on IRQ7-0 \n ", NULL},
+ {SB_PMIO_REG04, 0xFF, SB_PMIO_REG07, 0xFF, (CHAR8 *)"SMI on legacy devices activity(Serial, FDD etc) \n ", NULL},
+ {SB_PMIO_REG1C, 0xFF, SB_PMIO_REG1D, 0xFF, (CHAR8 *)"SMI on PIO 0123 \n ", NULL},
+ {SB_PMIO_REGA8, 0x0F, SB_PMIO_REGA9, 0xFF, (CHAR8 *)"SMI on PIO 4567 \n ", NULL},
+};
+
+
+/*++
+
+Routine Description:
+
+ SB SMI service
+
+Arguments:
+
+ pConfig - SBconfiguration
+
+Returns:
+
+ void
+
+--*/
+
+void sbSmmService(AMDSBCFG* pConfig){
+ UINT8 i, dbEnableValue, dbStatusValue;
+ SMMSERVICESTRUC *pSmmItems;
+ SMM_SERVICE_ROUTINE serviceRoutine;
+
+ pSmmItems = (SMMSERVICESTRUC *)FIXUP_PTR(&smmItemsTable[0]);
+ TRACE((DMSG_SB_TRACE, "CIMx - Entering SMM services \n"));
+ for (i = 1; i <= (sizeof(smmItemsTable)/sizeof(SMMSERVICESTRUC)); i++){
+ dbEnableValue = pSmmItems->enableRegNum;
+ ReadPMIO(pSmmItems->enableRegNum, AccWidthUint8, &dbEnableValue);
+ ReadPMIO(pSmmItems->statusRegNum, AccWidthUint8, &dbStatusValue);
+ if ( (dbEnableValue & (pSmmItems->enableBit)) && (dbStatusValue & (pSmmItems->statusBit)) ){
+ TRACE((DMSG_SB_TRACE, "\n \nSmi source is: %s \n", pSmmItems->debugMessage));
+ TRACE((DMSG_SB_TRACE, "Enable Reg:%d Value:%d\n", pSmmItems->enableRegNum, dbEnableValue));
+ TRACE((DMSG_SB_TRACE, "Status Reg:%d Value:%d\n\n", pSmmItems->statusRegNum, dbStatusValue));
+ if ( (pSmmItems->serviceRoutine)!= NULL){
+ serviceRoutine = (void *)FIXUP_PTR(pSmmItems->serviceRoutine);
+ serviceRoutine();
+ }
+ }
+ }
+ TRACE((DMSG_SB_TRACE, "CIMx - Exiting SMM services \n"));
+}
+
+
+void softwareSMIservice(void){
+ UINT16 dwSmiCmdPort, dwVar;
+ ReadPMIO(SB_PMIO_REG2A, AccWidthUint16, &dwSmiCmdPort);
+ ReadIO(dwSmiCmdPort, AccWidthUint16, &dwVar);
+ TRACE((DMSG_SB_TRACE, "SMI CMD Port Address: %X SMICMD Port value is %X \n", dwSmiCmdPort, dwVar));
+}
--- /dev/null
+/*****************************************************************************
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *
+ ***************************************************************************/
+
+
+#include "Platform.h"
+
+
+void usbInitBeforePciEnum(AMDSBCFG* pConfig){
+ UINT8 dbVar=0;
+
+ TRACE((DMSG_SB_TRACE, "Entering PreInit Usb \n"));
+ if (pConfig->Usb1Ohci0){
+ dbVar = (pConfig->Usb1Ehci << 2);
+ dbVar |= ((pConfig->Usb1Ohci0) << 0);
+ dbVar |= ((pConfig->Usb1Ohci1) << 1);
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG68, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT0+BIT1+BIT2), dbVar );
+ }
+ if (pConfig->Usb2Ohci0){
+ dbVar = (pConfig->Usb2Ehci << 6) ;
+ dbVar |= ((pConfig->Usb2Ohci0) << 4);
+ dbVar |= ((pConfig->Usb2Ohci1) << 5);
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG68, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT6+BIT4+BIT5), dbVar );
+ }
+ if (pConfig->Usb3Ohci)
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG68, AccWidthUint8 | S3_SAVE, ~(UINT32)(BIT7), ((pConfig->Usb3Ohci) << 7) );
+
+ RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50+1, AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT4), BIT4);
+}
+
+
+void usbInitAfterPciInit(AMDSBCFG* pConfig){
+ UINT32 ddBarAddress, ddVar;
+
+ ReadPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address
+ if ( (ddBarAddress != -1) && (ddBarAddress != 0) ){
+ //Enable Memory access
+ RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG04, AccWidthUint8, 0, BIT1);
+ //USB Common PHY CAL & Control Register setting
+ ddVar = 0x00020F00;
+ WriteMEM(ddBarAddress+SB_EHCI_BAR_REGC0, AccWidthUint32, &ddVar);
+ //RPR - IN AND OUT DATA PACKET FIFO THRESHOLD
+ //EHCI BAR 0xA4 //IN threshold bits[7:0]=0x40 //OUT threshold bits[23:16]=0x40
+ RWMEM(ddBarAddress+SB_EHCI_BAR_REGA4, AccWidthUint32, 0xFF00FF00, 0x00400040);
+ //RPR - EHCI dynamic clock gating feature
+ //EHCI_BAR 0xBC Bit[12] = 0, For normal operation, the clock gating feature must be disabled.
+ // Disables HS uFrame babble detection for erratum: EHCI_EOR + 9Ch [11] = 1
+ RWMEM(ddBarAddress+SB_EHCI_BAR_REGBC, AccWidthUint16, ~(UINT32)(BIT12+BIT11), BIT11);
+ }
+
+ ReadPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address
+ if ( (ddBarAddress != -1) && (ddBarAddress != 0) ){
+ //Enable Memory access
+ RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG04, AccWidthUint8, 0, BIT1);
+ //USB Common PHY CAL & Control Register setting
+ ddVar = 0x00020F00;
+ WriteMEM(ddBarAddress+SB_EHCI_BAR_REGC0, AccWidthUint32, &ddVar);
+ //RPR - IN AND OUT DATA PACKET FIFO THRESHOLD
+ //EHCI BAR 0xA4 //IN threshold bits[7:0]=0x40 //OUT threshold bits[23:16]=0x40
+ RWMEM(ddBarAddress+SB_EHCI_BAR_REGA4, AccWidthUint32, 0xFF00FF00, 0x00400040);
+ //RPR - EHCI dynamic clock gating feature
+ //EHCI_BAR 0xBC Bit[12] = 0, For normal operation, the clock gating feature must be disabled.
+ // Disables HS uFrame babble detection for erratum: EHCI_EOR + 9Ch [11] = 1
+ RWMEM(ddBarAddress+SB_EHCI_BAR_REGBC, AccWidthUint16, ~(UINT32)(BIT12+BIT11), BIT11);
+ }
+
+ if (pConfig->UsbPhyPowerDown)
+ RWPMIO(SB_PMIO_REG65, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, BIT0);
+ else
+ RWPMIO(SB_PMIO_REG65, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT0, 0);
+
+ // Disable the MSI capability of USB host controllers
+ RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG40+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT1+BIT0);
+ RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG40+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT1+BIT0);
+ RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG40+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
+
+ //RPR recommended setting "EHCI Advance Asynchronous Enhancement DISABLE"
+ //Set EHCI_pci_configx50[28]='1' to disable the advance async enhancement feature to avoid the bug found in Linux.
+ //Set EHCI_pci_configx50[6]='1' to disable EHCI MSI support
+ //RPR recommended setting "EHCI Async Park Mode"
+ //Set EHCI_pci_configx50[23]='1' to disable "EHCI Async Park Mode support"
+ // RPR recommended setting "EHCI Advance PHY Power Savings"
+ // Set EHCI_pci_configx50[31]='1' if SB700 A12 & above
+ // Fix for EHCI controller driver yellow sign issue under device manager
+ // when used in conjunction with HSET tool driver. EHCI PCI config 0x50[20]=1
+ RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT31+BIT28+BIT23+BIT20+BIT6);
+ RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT31+BIT28+BIT23+BIT20+BIT6);
+
+ //RPR recommended setting to, enable fix to cover the corner case S3 wake up issue from some USB 1.1 devices
+ //OHCI 0_PCI_Config 0x50[16] = 1
+ RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50+2, AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
+ RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50+2, AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
+ RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50+2, AccWidthUint8 | S3_SAVE, 0xFF, BIT0);
+
+ if (getRevisionID() >= SB700_A14){
+ RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(UINT32)(BIT28), BIT8+BIT7+BIT4+BIT3);
+ RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(UINT32)(BIT28), BIT8+BIT7+BIT4+BIT3);
+
+ RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT26+BIT25+BIT17);
+ RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT26+BIT25+BIT17);
+ RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, BIT26+BIT25);
+ }
+
+ if (getRevisionID() >= SB700_A15) {
+ //USB PID Error checking
+ RWPCI((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT1);
+ RWPCI((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50+1, AccWidthUint8 | S3_SAVE, 0xFF, BIT1);
+ }
+
+ // RPR 6.25 - Optionally disable OHCI isochronous out prefetch
+ if (pConfig->OhciIsoOutPrefetchDis) {
+ RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT9 + BIT8), 0);
+ RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT9 + BIT8), 0);
+ RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG50, AccWidthUint16 | S3_SAVE, ~(UINT32)(BIT9 + BIT8), 0);
+ }
+
+ if ( pConfig->EhciDataCacheDis ) {
+ // Disable Async Data Cache, EHCI_pci_configx50[26]='1'
+ RWPCI ((USB1_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(UINT32)BIT26, BIT26);
+ RWPCI ((USB2_EHCI_BUS_DEV_FUN << 16) + SB_EHCI_REG50, AccWidthUint32 | S3_SAVE, ~(UINT32)BIT26, BIT26);
+ }
+}
+
+
+void usbInitMidPost(AMDSBCFG* pConfig){
+ if (pConfig->UsbOhciLegacyEmulation == 0){
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG60+2, AccWidthUint8 | S3_SAVE, 0xFF, BIT1+BIT0);
+ RWPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG64+3, AccWidthUint8 | S3_SAVE, 0xFF, BIT7);
+ }
+ else{
+ programOhciMmioForEmulation();
+ }
+}
+
+
+void programOhciMmioForEmulation(void){
+ UINT32 ddBarAddress;
+
+ ReadPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address
+ ddBarAddress &= 0xFFFFF000;
+ if ( (ddBarAddress != 0xFFFFF000) && (ddBarAddress != 0) ){
+ //Enable Memory access
+ RWPCI((USB1_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG04, AccWidthUint8, 0, BIT1);
+ RWMEM(ddBarAddress+SB_OHCI_BAR_REG160, AccWidthUint32, 0, 0);
+ }
+
+ ReadPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address
+ ddBarAddress &= 0xFFFFF000;
+ if ( (ddBarAddress != 0xFFFFF000) && (ddBarAddress != 0) ){
+ //Enable Memory access
+ RWPCI((USB2_OHCI0_BUS_DEV_FUN << 16) + SB_OHCI_REG04, AccWidthUint8, 0, BIT1);
+ RWMEM(ddBarAddress+SB_OHCI_BAR_REG160, AccWidthUint32, 0, 0);
+ }
+
+ ReadPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG10, AccWidthUint32, &ddBarAddress);//Get BAR address
+ if ( (ddBarAddress != 0xFFFFF000) && (ddBarAddress != 0) ){
+ //Enable Memory access
+ RWPCI((USB3_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG04, AccWidthUint8, 0, BIT1);
+ RWMEM(ddBarAddress+SB_OHCI_BAR_REG160, AccWidthUint32, 0, 0);
+ }
+}
--- /dev/null
+/*;********************************************************************************
+;
+; Copyright (C) 2012 Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; * Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; * Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; * Neither the name of Advanced Micro Devices, Inc. nor the names of
+; its contributors may be used to endorse or promote products derived
+; from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*********************************************************************************/
+
+#ifndef _AMD_AMDLIB_H_
+#define _AMD_AMDLIB_H_
+
+typedef CHAR8 *va_list;
+#ifndef _INTSIZEOF
+ #define _INTSIZEOF(n)( (sizeof(n) + sizeof(UINTN) - 1) & ~(sizeof(UINTN) - 1) )
+#endif
+
+// Also support coding convention rules for var arg macros
+#ifndef va_start
+#define va_start(ap,v) ( ap = (va_list)&(v) + _INTSIZEOF(v) )
+#endif
+#define va_arg(ap,t) ( *(t *)((ap += _INTSIZEOF(t)) - _INTSIZEOF(t)) )
+#define va_end(ap) ( ap = (va_list)0 )
+
+#ifndef CIMx_DEBUG
+ #define CIMx_DEBUG 0
+#endif
+
+
+#pragma pack(push,1)
+
+#define IMAGE_ALIGN 32*1024
+#define NUM_IMAGE_LOCATION 32
+
+//Entry Point Call
+typedef void (*CIM_IMAGE_ENTRY)(void* pConfig);
+
+//Hook Call
+
+typedef struct _Reg8Mask
+{
+ UINT8 bRegIndex;
+ UINT8 bANDMask;
+ UINT8 bORMask;
+}REG8MASK;
+
+
+typedef struct _CIMFILEHEADER{
+ UINT32 AtiLogo;
+ UINT32 EntryPoint;
+ UINT32 ModuleLogo;
+ UINT32 ImageSize;
+ UINT16 Version;
+ UINT8 CheckSum;
+ UINT8 Reserved1;
+ UINT32 Reserved2;
+}CIMFILEHEADER;
+
+typedef struct _CPUID_DATA{
+ UINT32 REG_EAX;
+ UINT32 REG_EBX;
+ UINT32 REG_ECX;
+ UINT32 REG_EDX;
+}CPUID_DATA;
+
+#ifndef BIT0
+ #define BIT0 (1 << 0)
+#endif
+#ifndef BIT1
+ #define BIT1 (1 << 1)
+#endif
+#ifndef BIT2
+ #define BIT2 (1 << 2)
+#endif
+#ifndef BIT3
+ #define BIT3 (1 << 3)
+#endif
+#ifndef BIT4
+ #define BIT4 (1 << 4)
+#endif
+#ifndef BIT5
+ #define BIT5 (1 << 5)
+#endif
+#ifndef BIT6
+ #define BIT6 (1 << 6)
+#endif
+#ifndef BIT7
+ #define BIT7 (1 << 7)
+#endif
+#ifndef BIT8
+ #define BIT8 (1 << 8)
+#endif
+#ifndef BIT9
+ #define BIT9 (1 << 9)
+#endif
+#ifndef BIT10
+ #define BIT10 (1 << 10)
+#endif
+#ifndef BIT11
+ #define BIT11 (1 << 11)
+#endif
+#ifndef BIT12
+ #define BIT12 (1 << 12)
+#endif
+#ifndef BIT13
+ #define BIT13 (1 << 13)
+#endif
+#ifndef BIT14
+ #define BIT14 (1 << 14)
+#endif
+#ifndef BIT15
+ #define BIT15 (1 << 15)
+#endif
+#ifndef BIT16
+ #define BIT16 (1 << 16)
+#endif
+#ifndef BIT17
+ #define BIT17 (1 << 17)
+#endif
+#ifndef BIT18
+ #define BIT18 (1 << 18)
+#endif
+#ifndef BIT19
+ #define BIT19 (1 << 19)
+#endif
+#ifndef BIT20
+ #define BIT20 (1 << 20)
+#endif
+#ifndef BIT21
+ #define BIT21 (1 << 21)
+#endif
+#ifndef BIT22
+ #define BIT22 (1 << 22)
+#endif
+#ifndef BIT23
+ #define BIT23 (1 << 23)
+#endif
+#ifndef BIT24
+ #define BIT24 (1 << 24)
+#endif
+#ifndef BIT25
+ #define BIT25 (1 << 25)
+#endif
+#ifndef BIT26
+ #define BIT26 (1 << 26)
+#endif
+#ifndef BIT27
+ #define BIT27 (1 << 27)
+#endif
+#ifndef BIT28
+ #define BIT28 (1 << 28)
+#endif
+#ifndef BIT29
+ #define BIT29 (1 << 29)
+#endif
+#ifndef BIT30
+ #define BIT30 (1 << 30)
+#endif
+#ifndef BIT31
+ #define BIT31 (1 << 31)
+#endif
+
+#define PCI_ADDRESS(bus,dev,func,reg) \
+(UINT32) ( (((UINT32)bus) << 24) + (((UINT32)dev) << 19) + (((UINT32)func) << 16) + ((UINT32)reg) )
+
+#pragma pack(pop)
+
+typedef enum {
+ AccWidthUint8 = 0,
+ AccWidthUint16,
+ AccWidthUint32,
+} ACC_WIDTH;
+
+#define S3_SAVE 0x80
+
+#endif //#ifndef _AMD_AMDLIB_H_
projects / coreboot.git / commitdiff