rs780: power down GPPSB SB lane pads in correct PCIe core

Change-Id: I059d5b155cae051f31cc2495f8a47d53e01af808
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/519
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>

diff --git a/src/southbridge/amd/rs780/pcie.c b/src/southbridge/amd/rs780/pcie.c
index 5e2d9851303f169dec4c32d4f300c350e98af840..efa2e58e7619fa494737c5b1e5592751aeda85d9 100644 (file)
--- a/src/southbridge/amd/rs780/pcie.c
+++ b/src/southbridge/amd/rs780/pcie.c
@@ -86,15 +86,21 @@ static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port)
                 Config & (PCIE_DISABLE_HIDE_UNUSED_PORTS +
                           PCIE_GFX_COMPLIANCE))) {
        }
+
        /* step 3 Power Down Control for Southbridge */
+       if (port != 8)
+               return;
+
        reg = nbpcie_p_read_index(dev, 0xa2);
 
        switch ((reg >> 4) & 0x7) {     /* get bit 4-6, LC_LINK_WIDTH_RD */
        case 1:
-               nbpcie_ind_write_index(nb_dev, 0x65, 0x0e0e);
+               set_pcie_enable_bits(nb_dev, 0x65 | PCIE_CORE_INDEX_GPPSB,
+                                    0x0f0f, 0x0e0e);
                break;
        case 2:
-               nbpcie_ind_write_index(nb_dev, 0x65, 0x0c0c);
+               set_pcie_enable_bits(nb_dev, 0x65 | PCIE_CORE_INDEX_GPPSB,
+                                    0x0f0f, 0x0c0c);
                break;
        default:
                break;