projects / coreboot.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 8fa2787) | patch
i945: fix tsc udelay()
authorSven Schnelle <svens@stackframe.org>
Tue, 10 Jan 2012 11:16:38 +0000 (12:16 +0100)
committerPatrick Georgi <patrick@georgi-clan.de>
Tue, 10 Jan 2012 11:54:09 +0000 (12:54 +0100)
commit784ffb3db694dd2c964d9a4e1c6657a835b2d141
tree7998d307db61ef6518473518b5a71193153787d1tree | snapshot
parent8fa2787a0d74c70ca9497abf1483ab9dd223e642commit | diff
i945: fix tsc udelay()

The comparision is the wrong way round: as long as tsc
is below tsc1, the timeout is not reached

Change-Id: I75de74ef750b5a45be0156efaf10d7239a0b1136
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/530
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
src/northbridge/intel/i945/udelay.c diff | blob | history
my coreboot WIP stuff (asus m5a99x-evo board)