Allocation size for the section was miscalculated, so the section
did not honour its upper-bound address.
Also align the section start to 4 bytes, so it starts with code
instead of pad bytes.
Change-Id: Ic2a43981836a0873b50abecfcad2def7b6586a5d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/453
Tested-by: build bot (Jenkins)
Reviewed-by: Alec Ari <neotheuser@ymail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
TARGET(binary)
SECTIONS
{
+ /* Align .rom to next 4 byte boundary so no pad byte appears
+ * between _rom and _start.
+ */
+ .bogus ROMLOC_MIN : {
+ . = ALIGN(4);
+ ROMLOC = .;
+ } >rom = 0xff
+
/* This section might be better named .setup */
.rom ROMLOC : {
_rom = .;
_erom = .;
} >rom = 0xff
- ROMLOC = 0xffffff00 - (_erom - _rom) + 1;
+ /* Allocation reserves extra 16 bytes here. Alignment requirements
+ * may cause the total size of a section to change when the start
+ * address gets applied.
+ */
+ ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16);
/DISCARD/ : {
*(.comment)