config USE_OPTION_TABLE
bool "Use CMOS for configuration values"
default n
+ depends on HAVE_OPTION_TABLE
help
Enable this option if coreboot shall read options from the "CMOS"
NVRAM instead of using hard coded values.
bool
default n
+config USE_OPTION_TABLE
+ bool
+ default n
+
config HAVE_OPTION_TABLE
bool
- default y
+ default n
help
This variable specifies whether a given board has a cmos.layout
file containing NVRAM/CMOS bit definitions.
- It defaults to 'y' but can be changed to 'n' in mainboard/*/Kconfig.
+ It defaults to 'n' but can be selected in mainboard/*/Kconfig.
config PIRQ_ROUTE
bool
#include <version.h>
#include <device/device.h>
#include <stdlib.h>
-#if (CONFIG_HAVE_OPTION_TABLE == 1)
+#if (CONFIG_USE_OPTION_TABLE == 1)
#include <option_table.h>
#endif
return mainboard;
}
-#if (CONFIG_HAVE_OPTION_TABLE == 1)
+#if (CONFIG_USE_OPTION_TABLE == 1)
static struct cmos_checksum *lb_cmos_checksum(struct lb_header *header)
{
struct lb_record *rec;
rom_table_end &= ~0xffff;
printk(BIOS_DEBUG, "0x%08lx \n", rom_table_end);
-#if (CONFIG_HAVE_OPTION_TABLE == 1)
+#if (CONFIG_USE_OPTION_TABLE == 1)
{
struct lb_record *rec_dest = lb_new_record(head);
/* Copy the option config table, it's already a lb_record... */
#include <arch/io.h>
#include "arch/romcc_io.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
static void main(unsigned long bist)
{
#endif
#include "cpu/amd/dualcore/dualcore_id.c"
+#include <pc80/mc146818rtc.h>
static inline unsigned get_core_num_in_bsp(unsigned nodeid)
{
unsigned nodes;
unsigned nodeid;
- if (CONFIG_HAVE_OPTION_TABLE &&
- read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) {
+ if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0)) {
return; // disable multi_core
}
/* get_nodes define in ht_wrapper.c */
nodes = get_nodes();
- disable_siblings = !CONFIG_LOGICAL_CPUS;
-
-#if CONFIG_LOGICAL_CPUS == 1 && CONFIG_HAVE_OPTION_TABLE == 1
- if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) { // 0 mean multi core
+ if (!CONFIG_LOGICAL_CPUS ||
+ read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) { // 0 means multi core
disable_siblings = 1;
+ } else {
+ disable_siblings = 0;
}
-#endif
/* Assume that all node are same stepping, otherwise we can use use
nb_cfg_54 from bsp for all nodes */
/* get_nodes define in in_coherent_ht.c */
nodes = get_nodes();
- disable_siblings = !CONFIG_LOGICAL_CPUS;
-
-#if CONFIG_LOGICAL_CPUS == 1 && CONFIG_HAVE_OPTION_TABLE == 1
- if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) { // 0 mean multi core
+ if (!CONFIG_LOGICAL_CPUS ||
+ read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) { // 0 means multi core
disable_siblings = 1;
+ } else {
+ disable_siblings = 0;
}
-#endif
/* here I assume that all node are same stepping, otherwise we can use use nb_cfg_54 from bsp for all nodes */
nb_cfg_54 = read_nb_cfg_54();
*/
#include <console/console.h>
-#include <pc80/mc146818rtc_early.c>
+#include <pc80/mc146818rtc.h>
#include <northbridge/amd/amdht/ht_wrapper.c>
#ifndef SET_NB_CFG_54
* LB_CKS_RANGE_START, LB_CKS_RANGE_END and LB_CKS_LOC are defined
* in option_table.h
*/
+#if CONFIG_HAVE_OPTION_TABLE
+#include <option_table.h>
+#endif
+
+#ifndef UTIL_BUILD_OPTION_TABLE
+#include <arch/io.h>
+static inline unsigned char cmos_read(unsigned char addr)
+{
+ int offs = 0;
+ if (addr >= 128) {
+ offs = 2;
+ addr -= 128;
+ }
+ outb(addr, RTC_BASE_PORT + offs + 0);
+ return inb(RTC_BASE_PORT + offs + 1);
+}
-#if !defined(ASSEMBLY) && !defined(__PRE_RAM__)
+static inline void cmos_write(unsigned char val, unsigned char addr)
+{
+ int offs = 0;
+ if (addr >= 128) {
+ offs = 2;
+ addr -= 128;
+ }
+ outb(addr, RTC_BASE_PORT + offs + 0);
+ outb(val, RTC_BASE_PORT + offs + 1);
+}
+#endif
+
+#if !defined(__ROMCC__)
void rtc_init(int invalid);
-#if CONFIG_USE_OPTION_TABLE == 1
+#if CONFIG_USE_OPTION_TABLE
int get_option(void *dest, const char *name);
+unsigned read_option(unsigned start, unsigned size, unsigned def);
#else
static inline int get_option(void *dest __attribute__((unused)),
const char *name __attribute__((unused))) { return -2; }
+static inline unsigned read_option(unsigned start, unsigned size, unsigned def)
+ { return def; }
#endif
+#else
+#include <pc80/mc146818rtc_early.c>
#endif
#endif /* PC80_MC146818RTC_H */
default "ATC-6220"
depends on BOARD_A_TREND_ATC_6220
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_A_TREND_ATC_6220
-
config IRQ_SLOT_COUNT
int
default 7
default "ATC-6240"
depends on BOARD_A_TREND_ATC_6240
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_A_TREND_ATC_6240
-
config IRQ_SLOT_COUNT
int
default 7
default "BE6-II V2.0"
depends on BOARD_ABIT_BE6_II_V2_0
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_ABIT_BE6_II_V2_0
-
config IRQ_SLOT_COUNT
int
default 9
default "PCM-5820"
depends on BOARD_ADVANTECH_PCM_5820
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_ADVANTECH_PCM_5820
-
config IRQ_SLOT_COUNT
int
default 2
default "DB800"
depends on BOARD_AMD_DB800
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_AMD_DB800
-
config IRQ_SLOT_COUNT
int
default 4
select GENERATE_ACPI_TABLES
select GENERATE_MP_TABLE
select GENERATE_PIRQ_TABLE
+ select HAVE_OPTION_TABLE
select HAVE_MAINBOARD_RESOURCES
select HAVE_BUS_CONFIG
select USE_PRINTK_IN_CAR
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
select GENERATE_ACPI_TABLES
select GENERATE_MP_TABLE
select GENERATE_PIRQ_TABLE
+ select HAVE_OPTION_TABLE
select HAVE_MAINBOARD_RESOURCES
select HAVE_BUS_CONFIG
select LIFT_BSP_APIC_ID
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
select SUPERIO_ITE_IT8718F
select BOARD_HAS_FADT
select HAVE_BUS_CONFIG
+ select HAVE_OPTION_TABLE
select GENERATE_PIRQ_TABLE
select GENERATE_MP_TABLE
select USE_PRINTK_IN_CAR
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
#include <console/console.h>
#include "lib/ramtest.c"
#include <cpu/amd/model_10xxx_rev.h>
default "Norwich"
depends on BOARD_AMD_NORWICH
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_AMD_NORWICH
-
config IRQ_SLOT_COUNT
int
default 6
select SOUTHBRIDGE_AMD_SB600
select BOARD_HAS_FADT
select HAVE_BUS_CONFIG
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select USE_PRINTK_IN_CAR
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
default "Rumba"
depends on BOARD_AMD_RUMBA
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_AMD_RUMBA
-
config IRQ_SLOT_COUNT
int
default 2
select SUPERIO_WINBOND_W83627HF
select BOARD_HAS_FADT
select HAVE_BUS_CONFIG
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select USE_PRINTK_IN_CAR
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include "pc80/serial.c"
#include "./arch/i386/lib/printk_init.c"
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
select SUPERIO_WINBOND_W83627HF
select BOARD_HAS_FADT
select HAVE_BUS_CONFIG
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select USE_PRINTK_IN_CAR
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
#include <console/console.h>
#include "lib/ramtest.c"
#include <cpu/amd/model_10xxx_rev.h>
select SUPERIO_ITE_IT8718F
select BOARD_HAS_FADT
select HAVE_BUS_CONFIG
+ select HAVE_OPTION_TABLE
select GENERATE_PIRQ_TABLE
select GENERATE_MP_TABLE
select USE_PRINTK_IN_CAR
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
#include <console/console.h>
#include "lib/ramtest.c"
#include <cpu/amd/model_10xxx_rev.h>
select SOUTHBRIDGE_AMD_AMD8131
select SUPERIO_NSC_PC87360
select HAVE_PIRQ_TABLE
+ select HAVE_OPTION_TABLE
select HAVE_MP_TABLE
select USE_PRINTK_IN_CAR
select USE_DCACHE_RAM
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
default "DBE61"
depends on BOARD_ARTECGROUP_DBE61
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_ARTECGROUP_DBE61
-
config IRQ_SLOT_COUNT
int
default 3
default "MB-5BLGP"
depends on BOARD_ASI_MB_5BLGP
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_ASI_MB_5BLGP
-
config IRQ_SLOT_COUNT
int
default 3
default "MB-5BLMP"
depends on BOARD_ASI_MB_5BLMP
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_ASI_MB_5BLMP
-
config IRQ_SLOT_COUNT
int
default 5
select GENERATE_MP_TABLE
select GENERATE_PIRQ_TABLE
select HAVE_MAINBOARD_RESOURCES
+ select HAVE_OPTION_TABLE
select HAVE_BUS_CONFIG
select LIFT_BSP_APIC_ID
select USE_PRINTK_IN_CAR
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
select SOUTHBRIDGE_NVIDIA_CK804
select SUPERIO_ITE_IT8712F
select HAVE_BUS_CONFIG
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select USE_PRINTK_IN_CAR
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/ite/it8712f/it8712f_early_serial.c"
select SUPERIO_WINBOND_W83627EHG
select USE_PRINTK_IN_CAR
select USE_DCACHE_RAM
+ select HAVE_OPTION_TABLE
select HAVE_ACPI_TABLES
select HAVE_MP_TABLE
select BOARD_ROMSIZE_KB_512
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
#include <arch/romcc_io.h>
#include <cpu/amd/mtrr.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
default "MEW-AM"
depends on BOARD_ASUS_MEW_AM
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_ASUS_MEW_AM
-
config IRQ_SLOT_COUNT
int
default 8
select SOUTHBRIDGE_INTEL_I82801AX
select SUPERIO_SMSC_LPC47B272
select ROMCC
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_512
default "P2B-D"
depends on BOARD_ASUS_P2B_D
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_ASUS_P2B_D
-
config IRQ_SLOT_COUNT
int
default 6
default "P2B-DS"
depends on BOARD_ASUS_P2B_DS
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_ASUS_P2B_DS
-
config IRQ_SLOT_COUNT
int
default 7
default "P2B-F"
depends on BOARD_ASUS_P2B_F
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_ASUS_P2B_F
-
config IRQ_SLOT_COUNT
int
default 7
default "P2B-LS"
depends on BOARD_ASUS_P2B_LS
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_ASUS_P2B_LS
-
config IRQ_SLOT_COUNT
int
default 8
default "P2B"
depends on BOARD_ASUS_P2B
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_ASUS_P2B
-
config IRQ_SLOT_COUNT
int
default 6
default "P3B-F"
depends on BOARD_ASUS_P3B_F
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_ASUS_P3B_F
-
config IRQ_SLOT_COUNT
int
default 8
default "TC320"
depends on BOARD_AXUS_TC320
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_AXUS_TC320
-
# Soldered NIC, internal USB, no real PCI slots.
config IRQ_SLOT_COUNT
int
default "PT-6IBD"
depends on BOARD_AZZA_PT_6IBD
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_AZZA_PT_6IBD
-
config IRQ_SLOT_COUNT
int
default 7
default "WinNET100"
depends on BOARD_BCOM_WINNET100
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_BCOM_WINNET100
-
# Soldered NIC, internal USB, no real PCI slots.
config IRQ_SLOT_COUNT
int
select SOUTHBRIDGE_VIA_VT8237R
select SUPERIO_WINBOND_W83697HF
select HAVE_PIRQ_TABLE
+ select HAVE_OPTION_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_512
default "M6TBA"
depends on BOARD_BIOSTAR_M6TBA
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_BIOSTAR_M6TBA
-
config IRQ_SLOT_COUNT
int
default 7
select SOUTHBRIDGE_BROADCOM_BCM5785
select SUPERIO_NSC_PC87417
select HAVE_BUS_CONFIG
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select USE_PRINTK_IN_CAR
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
default "Deskpro EN SFF P600"
depends on BOARD_COMPAQ_DESKPRO_EN_SFF_P600
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_COMPAQ_DESKPRO_EN_SFF_P600
-
config IRQ_SLOT_COUNT
int
default 5
select SUPERIO_NSC_PC8374
select ROMCC
select HAVE_HARD_RESET
+ select HAVE_OPTION_TABLE
select BOARD_HAS_HARD_RESET
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
select NORTHBRIDGE_INTEL_I855
select SOUTHBRIDGE_INTEL_I82801DX
select SUPERIO_WINBOND_W83627HF
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_HARD_RESET
select BOARD_ROMSIZE_KB_1024
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
-//#include "option_table.h"
#include <stdlib.h>
#include "pc80/udelay_io.c"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
#include "southbridge/intel/i82801dx/i82801dx.h"
select ARCH_X86
select CPU_AMD_SC520
select HAVE_PIRQ_TABLE
+ select HAVE_OPTION_TABLE
select BOARD_ROMSIZE_KB_512
select ROMCC
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
#include "cpu/x86/bist.h"
default "MSM800SEV"
depends on BOARD_DIGITALLOGIC_MSM800SEV
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_DIGITALLOGIC_MSM800SEV
-
config IRQ_SLOT_COUNT
int
default 9
default "5BCM"
depends on BOARD_EAGLELION_5BCM
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_EAGLELION_5BCM
-
config IRQ_SLOT_COUNT
int
default 2
default "P6IWP-FE"
depends on BOARD_ECS_P6IWP_FE
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_ECS_P6IWP_FE
-
config IRQ_SLOT_COUNT
int
default 10
select ARCH_X86
select SOUTHBRIDGE_INTEL_I82371EB
select ROMCC
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_256
select WARNINGS_ARE_ERRORS
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "pc80/udelay_io.c"
#include "lib/delay.c"
select GENERATE_ACPI_TABLES
select GENERATE_PIRQ_TABLE
select GENERATE_MP_TABLE
+ select HAVE_OPTION_TABLE
select HAVE_HARD_RESET
select HAVE_ACPI_RESUME
select HAVE_ACPI_SLIC
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
default "GA-6BXC"
depends on BOARD_GIGABYTE_GA_6BXC
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_GIGABYTE_GA_6BXC
-
config IRQ_SLOT_COUNT
int
default 6
default "GA-6BXE"
depends on BOARD_GIGABYTE_GA_6BXE
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_GIGABYTE_GA_6BXE
-
config IRQ_SLOT_COUNT
int
default 7
select SOUTHBRIDGE_SIS_SIS966
select SUPERIO_ITE_IT8716F
select HAVE_BUS_CONFIG
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select USE_PRINTK_IN_CAR
select USE_DCACHE_RAM
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include "pc80/serial.c"
#include "lib/uart8250.c"
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#if CONFIG_USBDEBUG
select SUPERIO_ITE_IT8716F
select SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
select HAVE_BUS_CONFIG
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select USE_PRINTK_IN_CAR
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include "pc80/serial.c"
#include "lib/uart8250.c"
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#if CONFIG_USBDEBUG
select SOUTHBRIDGE_BROADCOM_BCM5785
select SUPERIO_NSC_PC87417
select HAVE_BUS_CONFIG
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select USE_PRINTK_IN_CAR
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
default "e-Vectra P2706T"
depends on BOARD_HP_E_VECTRA_P2706T
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_HP_E_VECTRA_P2706T
-
config IRQ_SLOT_COUNT
int
default 3
select GENERATE_PIRQ_TABLE
select GENERATE_MP_TABLE
select HAVE_HARD_RESET
+ select HAVE_OPTION_TABLE
select HAVE_ACPI_RESUME
select HAVE_MAINBOARD_RESOURCES
select MMCONF_SUPPORT
#include "superio/winbond/w83627ehg/w83627ehg.h"
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
select SOUTHBRIDGE_AMD_AMD8111
select SOUTHBRIDGE_AMD_AMD8131
select SUPERIO_NSC_PC87366
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select USE_PRINTK_IN_CAR
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
select SOUTHBRIDGE_AMD_AMD8111
select SOUTHBRIDGE_AMD_AMD8131
select SUPERIO_NSC_PC87366
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select USE_PRINTK_IN_CAR
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
default "PCISA-LX-800-R10"
depends on BOARD_IEI_PCISA_LX_800_R10
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_IEI_PCISA_LX_800_R10
-
config IRQ_SLOT_COUNT
int
default 9
default "D810E2CB"
depends on BOARD_INTEL_D810E2CB
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_INTEL_D810E2CB
-
config IRQ_SLOT_COUNT
int
default 7
select GENERATE_ACPI_TABLES
select GENERATE_PIRQ_TABLE
select GENERATE_MP_TABLE
+ select HAVE_OPTION_TABLE
select HAVE_HARD_RESET
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
#include "superio/smsc/lpc47m15x/lpc47m15x.h"
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
select SOUTHBRIDGE_INTEL_I3100
select SUPERIO_INTEL_I3100
select SUPERIO_SMSC_SMSCSUPERIO
+ select HAVE_OPTION_TABLE
select HAVE_HARD_RESET
select BOARD_HAS_HARD_RESET
select BOARD_HAS_FADT
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
select ROMCC
select HAVE_HARD_RESET
select BOARD_HAS_HARD_RESET
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select UDELAY_TSC
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
default "3100 devkit (Mt. Arvon)"
depends on BOARD_INTEL_MTARVON
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_INTEL_MTARVON
-
config IRQ_SLOT_COUNT
int
default 1
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
#include "southbridge/intel/i3100/i3100_early_smbus.c"
default "Truxton"
depends on BOARD_INTEL_TRUXTON
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_INTEL_TRUXTON
-
config IRQ_SLOT_COUNT
int
default 1
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include "pc80/udelay_io.c"
#include <console/console.h>
#include "lib/ramtest.c"
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select UDELAY_TSC
- select HAVE_OPTION_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_2048
#include <cpu/x86/lapic.h>
#include <arch/cpu.h>
#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
#include "southbridge/intel/i82801cx/i82801cx_early_smbus.c"
select SUPERIO_WINBOND_W83627HF
select BOARD_HAS_FADT
select HAVE_BUS_CONFIG
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select USE_PRINTK_IN_CAR
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
select SOUTHBRIDGE_AMD_AMD8131
select SUPERIO_WINBOND_W83627HF
select HAVE_PIRQ_TABLE
+ select HAVE_OPTION_TABLE
select HAVE_MP_TABLE
select USE_PRINTK_IN_CAR
select USE_DCACHE_RAM
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
select SOUTHBRIDGE_AMD_AMD8111
select SOUTHBRIDGE_AMD_AMD8131
select SUPERIO_WINBOND_W83627THF
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select USE_PRINTK_IN_CAR
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
select NORTHBRIDGE_VIA_CN700
select SOUTHBRIDGE_VIA_VT8237R
select SUPERIO_FINTEK_F71805F
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_512
select GENERATE_ACPI_TABLES
select GENERATE_PIRQ_TABLE
select GENERATE_MP_TABLE
+ select HAVE_OPTION_TABLE
select HAVE_HARD_RESET
select HAVE_ACPI_RESUME
select HAVE_MAINBOARD_RESOURCES
#include "superio/winbond/w83627thg/w83627thg.h"
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
select SOUTHBRIDGE_AMD_SB600
select SUPERIO_WINBOND_W83627DHG
select BOARD_HAS_FADT
+ select HAVE_OPTION_TABLE
select HAVE_BUS_CONFIG
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
default "Cool Frontrunner"
depends on BOARD_LIPPERT_FRONTRUNNER
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_LIPPERT_FRONTRUNNER
-
config IRQ_SLOT_COUNT
int
default 2
default "Cool RoadRunner-LX"
depends on BOARD_LIPPERT_ROADRUNNER_LX
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_LIPPERT_ROADRUNNER_LX
-
config IRQ_SLOT_COUNT
int
default 7
default "Cool SpaceRunner-LX"
depends on BOARD_LIPPERT_SPACERUNNER_LX
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_LIPPERT_SPACERUNNER_LX
-
config IRQ_SLOT_COUNT
int
default 7
default "6513WU"
depends on BOARD_MITAC_6513WU
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_MITAC_6513WU
-
config IRQ_SLOT_COUNT
int
default 8
default "MS-6119"
depends on BOARD_MSI_MS_6119
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_MSI_MS_6119
-
config IRQ_SLOT_COUNT
int
default 7
default "MS-6147"
depends on BOARD_MSI_MS_6147
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_MSI_MS_6147
-
config IRQ_SLOT_COUNT
int
default 8
default "MS-6156"
depends on BOARD_MSI_MS_6156
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_MSI_MS_6156
-
config IRQ_SLOT_COUNT
int
default 7
default "MS-6178"
depends on BOARD_MSI_MS_6178
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_MSI_MS_6178
-
config IRQ_SLOT_COUNT
int
default 4
select SUPERIO_WINBOND_W83627THF
select HAVE_BUS_CONFIG
select HAVE_HARD_RESET
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select USE_DCACHE_RAM
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
select SOUTHBRIDGE_NVIDIA_MCP55
select SUPERIO_WINBOND_W83627EHG
select HAVE_BUS_CONFIG
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select USE_PRINTK_IN_CAR
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include "pc80/serial.c"
#include "console/console.c"
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#if CONFIG_USBDEBUG
select SOUTHBRIDGE_BROADCOM_BCM5785
select SUPERIO_NSC_PC87417
select HAVE_BUS_CONFIG
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select USE_PRINTK_IN_CAR
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
select SOUTHBRIDGE_NVIDIA_MCP55
select SUPERIO_WINBOND_W83627EHG
select HAVE_BUS_CONFIG
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select USE_PRINTK_IN_CAR
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
default 0
depends on BOARD_MSI_MS9652_FAM10
-config HAVE_OPTION_TABLE
- bool
- default y
- depends on BOARD_MSI_MS9652_FAM10
-
config MAX_CPUS
int
default 8
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
#include <console/console.h>
#if CONFIG_USBDEBUG
#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
default "PowerMate 2000"
depends on BOARD_NEC_POWERMATE_2000
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_NEC_POWERMATE_2000
-
config IRQ_SLOT_COUNT
int
default 5
select SOUTHBRIDGE_AMD_AMD8111
select SOUTHBRIDGE_AMD_AMD8131
select SUPERIO_WINBOND_W83627HF
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select USE_PRINTK_IN_CAR
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
default "IP530"
depends on BOARD_NOKIA_IP530
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_NOKIA_IP530
-
config IRQ_SLOT_COUNT
int
default 22
select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
select SOUTHBRIDGE_NVIDIA_MCP55
select SUPERIO_WINBOND_W83627EHG
+ select HAVE_OPTION_TABLE
select HAVE_BUS_CONFIG
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include "pc80/serial.c"
#include "lib/uart8250.c"
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#if CONFIG_USBDEBUG
default "btest"
depends on BOARD_OLPC_BTEST
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_OLPC_BTEST
-
config IRQ_SLOT_COUNT
int
default 2
default "rev_a"
depends on BOARD_OLPC_REV_A
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_OLPC_REV_A
-
config IRQ_SLOT_COUNT
int
default 2
default "ALIX.1C"
depends on BOARD_PCENGINES_ALIX1C
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_PCENGINES_ALIX1C
-
config IRQ_SLOT_COUNT
int
default 5
default "RM4100"
depends on BOARD_RCA_RM4100
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_RCA_RM4100
-
config DCACHE_RAM_BASE
hex
default 0xffdf8000
select SUPERIO_SMSC_LPC47N227
select SUPERIO_RENESAS_M3885X
select BOARD_HAS_FADT
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select MMCONF_SUPPORT
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
default "SY-6BA+ III"
depends on BOARD_SOYO_SY_6BA_PLUS_III
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_SOYO_SY_6BA_PLUS_III
-
config IRQ_SLOT_COUNT
int
default 7
select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
select SOUTHBRIDGE_NVIDIA_CK804
select SUPERIO_SMSC_LPC47M10X
+ select HAVE_OPTION_TABLE
select HAVE_BUS_CONFIG
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
select SOUTHBRIDGE_NVIDIA_MCP55
select SUPERIO_WINBOND_W83627HF
+ select HAVE_OPTION_TABLE
select HAVE_BUS_CONFIG
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include "pc80/serial.c"
#include "console/console.c"
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
select SOUTHBRIDGE_NVIDIA_MCP55
select SUPERIO_WINBOND_W83627HF
+ select HAVE_OPTION_TABLE
select HAVE_BUS_CONFIG
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include "pc80/serial.c"
#include "console/console.c"
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
select SOUTHBRIDGE_NVIDIA_MCP55
select SUPERIO_WINBOND_W83627HF
select HAVE_BUS_CONFIG
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select USE_PRINTK_IN_CAR
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
#include <console/console.h>
#include "lib/ramtest.c"
select SOUTHBRIDGE_NVIDIA_MCP55
select SUPERIO_WINBOND_W83627HF
select HAVE_BUS_CONFIG
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select USE_PRINTK_IN_CAR
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
#include <console/console.h>
#include "lib/ramtest.c"
select ROMCC
select HAVE_HARD_RESET
select BOARD_HAS_HARD_RESET
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select BOARD_ROMSIZE_KB_1024
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
#include "pc80/udelay_io.c"
select ROMCC
select HAVE_HARD_RESET
select BOARD_HAS_HARD_RESET
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select BOARD_ROMSIZE_KB_1024
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
#include "pc80/udelay_io.c"
select ROMCC
select HAVE_HARD_RESET
select BOARD_HAS_HARD_RESET
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select BOARD_ROMSIZE_KB_1024
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
select ROMCC
select HAVE_HARD_RESET
select BOARD_HAS_HARD_RESET
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select USE_WATCHDOG_ON_BOOT
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
select ROMCC
select HAVE_HARD_RESET
select BOARD_HAS_HARD_RESET
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select USE_WATCHDOG_ON_BOOT
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
select SUPERIO_ITE_IT8712F
select BOARD_HAS_FADT
select HAVE_BUS_CONFIG
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select USE_PRINTK_IN_CAR
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
select SUPERIO_ITE_IT8712F
select BOARD_HAS_FADT
select HAVE_BUS_CONFIG
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select USE_PRINTK_IN_CAR
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
select ARCH_X86
select CPU_AMD_SC520
select ROMCC
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_128
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
#include "cpu/x86/bist.h"
default "TC7020"
depends on BOARD_TELEVIDEO_TC7020
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_TELEVIDEO_TC7020
-
config IRQ_SLOT_COUNT
int
default 3
default "IP1000"
depends on BOARD_THOMSON_IP1000
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_THOMSON_IP1000
-
config DCACHE_RAM_BASE
hex
default 0xffdf8000
default "Geos"
depends on BOARD_TRAVERSE_GEOS
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_TRAVERSE_GEOS
-
config IRQ_SLOT_COUNT
int
default 6
default "S1846"
depends on BOARD_TYAN_S1846
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_TYAN_S1846
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
select SOUTHBRIDGE_AMD_AMD8111
select SUPERIO_WINBOND_W83627HF
select HAVE_HARD_RESET
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select BOARD_ROMSIZE_KB_512
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
select SOUTHBRIDGE_AMD_AMD8111
select SUPERIO_WINBOND_W83627HF
select HAVE_HARD_RESET
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select BOARD_ROMSIZE_KB_512
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
select SOUTHBRIDGE_AMD_AMD8111
select SUPERIO_WINBOND_W83627HF
select HAVE_HARD_RESET
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select BOARD_ROMSIZE_KB_512
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
select SUPERIO_WINBOND_W83627HF
select HAVE_BUS_CONFIG
select HAVE_HARD_RESET
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select BOARD_ROMSIZE_KB_512
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
select SOUTHBRIDGE_AMD_AMD8111
select SUPERIO_WINBOND_W83627HF
select HAVE_HARD_RESET
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select BOARD_ROMSIZE_KB_512
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
select SUPERIO_WINBOND_W83627HF
select HAVE_BUS_CONFIG
select HAVE_HARD_RESET
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select BOARD_ROMSIZE_KB_512
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
select SUPERIO_WINBOND_W83627HF
select HAVE_BUS_CONFIG
select HAVE_HARD_RESET
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select SERIAL_CPU_INIT
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
select SUPERIO_WINBOND_W83627HF
select HAVE_BUS_CONFIG
select HAVE_HARD_RESET
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select SERIAL_CPU_INIT
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
select SOUTHBRIDGE_AMD_AMD8131
select SUPERIO_SMSC_LPC47B397
select HAVE_BUS_CONFIG
+ select HAVE_OPTION_TABLE
select HAVE_HARD_RESET
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
#include <cpu/amd/model_fxx_rev.h>
select SOUTHBRIDGE_NVIDIA_MCP55
select SUPERIO_WINBOND_W83627HF
select HAVE_BUS_CONFIG
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select USE_PRINTK_IN_CAR
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include "pc80/serial.c"
#include "console/console.c"
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#if CONFIG_USBDEBUG
select SOUTHBRIDGE_NVIDIA_MCP55
select SUPERIO_WINBOND_W83627HF
select HAVE_BUS_CONFIG
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select USE_PRINTK_IN_CAR
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
#include <console/console.h>
#if CONFIG_USBDEBUG
#include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c"
select SOUTHBRIDGE_AMD_AMD8111
select SOUTHBRIDGE_AMD_AMD8131
select SUPERIO_WINBOND_W83627HF
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select USE_PRINTK_IN_CAR
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
select SOUTHBRIDGE_AMD_AMD8111
select SOUTHBRIDGE_AMD_AMD8131
select SUPERIO_WINBOND_W83627HF
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select USE_PRINTK_IN_CAR
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
select NORTHBRIDGE_VIA_CN700
select SOUTHBRIDGE_VIA_VT8237R
select SUPERIO_VIA_VT1211
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_512
select SOUTHBRIDGE_RICOH_RL5C476
select SUPERIO_VIA_VT1211
select BOARD_HAS_FADT
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_256
select NORTHBRIDGE_VIA_VX800
select SUPERIO_WINBOND_W83697HF
select BOARD_HAS_FADT
+ select HAVE_OPTION_TABLE
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_512
select SOUTHBRIDGE_VIA_VT8237R
select SUPERIO_WINBOND_W83697HF
select BOARD_HAS_FADT
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select EPIA_VT8237R_INIT
select NORTHBRIDGE_VIA_VT8601
select SOUTHBRIDGE_VIA_VT8231
select SUPERIO_WINBOND_W83627HF
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_256
select ROMCC
select NORTHBRIDGE_VIA_CN700
select SOUTHBRIDGE_VIA_VT8237R
select SUPERIO_ITE_IT8716F
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select SMP
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
+#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include "lib/ramtest.c"
#include "northbridge/via/cn700/raminit.h"
select NORTHBRIDGE_VIA_CX700
select SUPERIO_VIA_VT1211
select BOARD_HAS_FADT
+ select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
# select MMCONF_SUPPORT
default "PL6064"
depends on BOARD_WINENT_PL6064
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_WINENT_PL6064
-
config IRQ_SLOT_COUNT
int
default 7
default "s50"
depends on BOARD_WYSE_S50
-config HAVE_OPTION_TABLE
- bool
- default n
- depends on BOARD_WYSE_S50
-
config IRQ_SLOT_COUNT
int
default 3
#include <device/hypertransport_def.h>
#include <stdlib.h>
#include "arch/romcc_io.h"
+#include <pc80/mc146818rtc.h>
#include "amdk8.h"
#if CONFIG_LOGICAL_CPUS==1
unsigned total_cpus;
- if ((!CONFIG_HAVE_OPTION_TABLE) ||
- read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) == 0) { /* multi_core */
+ if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) == 0) { /* multi_core */
total_cpus = verify_dualcore(nodes);
}
else {
if (nbcap & NBCAP_ECC) {
dcl |= DCL_DimmEccEn;
}
- if (CONFIG_HAVE_OPTION_TABLE &&
- read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
+ if (read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) {
dcl &= ~DCL_DimmEccEn;
}
pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
{
unsigned long tom_k, base_k;
- if ((!CONFIG_HAVE_OPTION_TABLE) ||
- read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) {
+ if (read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) {
tom_k = interleave_chip_selects(ctrl);
} else {
printk(BIOS_DEBUG, "Interleaving disabled\n");
min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
bios_cycle_time = min_cycle_times[
read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)];
- if (CONFIG_HAVE_OPTION_TABLE && bios_cycle_time > min_cycle_time) {
+ if (bios_cycle_time > min_cycle_time) {
min_cycle_time = bios_cycle_time;
}
min_latency = 2;
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
+#include <pc80/mc146818rtc.h>
#include <spd.h>
#include "raminit.h"
#include "i945.h"
values[3] |= (reg32 >> (24 - 4)) & 0xf0;
/* coreboot only uses bytes 0 - 127 for its CMOS values so far
- * so we grad bytes 128 - 131 to save the receive enable values
+ * so we grab bytes 128 - 131 to save the receive enable values
*/
for (i=0; i<4; i++)
obj-y += i8259.o
obj-$(CONFIG_UDELAY_IO) += udelay_io.o
obj-y += keyboard.o
-
+initobj-$(CONFIG_USE_OPTION_TABLE) += mc146818rtc_early.o
initobj-$(CONFIG_USE_DCACHE_RAM) += serial.o
subdirs-y += vga
#include <console/console.h>
-#include <arch/io.h>
#include <pc80/mc146818rtc.h>
#include <boot/coreboot_tables.h>
#include <string.h>
-#if CONFIG_HAVE_OPTION_TABLE
-#include <option_table.h>
-#endif
/* control registers - Moto names
*/
# define RTC_VRT 0x80 /* valid RAM and time */
/**********************************************************************/
-static inline unsigned char cmos_read(unsigned char addr)
-{
- int offs = 0;
- if (addr >= 128) {
- offs = 2;
- addr -= 128;
- }
- outb(addr, RTC_BASE_PORT + offs + 0);
- return inb(RTC_BASE_PORT + offs + 1);
-}
-
-static inline void cmos_write(unsigned char val, unsigned char addr)
-{
- int offs = 0;
- if (addr >= 128) {
- offs = 2;
- addr -= 128;
- }
- outb(addr, RTC_BASE_PORT + offs + 0);
- outb(val, RTC_BASE_PORT + offs + 1);
-}
-
-#if CONFIG_HAVE_OPTION_TABLE
+#if CONFIG_USE_OPTION_TABLE
static int rtc_checksum_valid(int range_start, int range_end, int cks_loc)
{
int i;
void rtc_init(int invalid)
{
-#if CONFIG_HAVE_OPTION_TABLE
+#if CONFIG_USE_OPTION_TABLE
unsigned char x;
int cmos_invalid, checksum_invalid;
#endif
printk(BIOS_DEBUG, "RTC Init\n");
-#if CONFIG_HAVE_OPTION_TABLE
+#if CONFIG_USE_OPTION_TABLE
/* See if there has been a CMOS power problem. */
x = cmos_read(RTC_VALID);
cmos_invalid = !(x & RTC_VRT);
/* Setup the frequency it operates at */
cmos_write(RTC_FREQ_SELECT_DEFAULT, RTC_FREQ_SELECT);
-#if CONFIG_HAVE_OPTION_TABLE
+#if CONFIG_USE_OPTION_TABLE
/* See if there is a LB CMOS checksum error */
checksum_invalid = !rtc_checksum_valid(LB_CKS_RANGE_START,
LB_CKS_RANGE_END,LB_CKS_LOC);
}
-#if CONFIG_USE_OPTION_TABLE == 1
+#if CONFIG_USE_OPTION_TABLE
/* This routine returns the value of the requested bits
input bit = bit count from the beginning of the cmos image
length = number of bits to include in the value
#include <pc80/mc146818rtc.h>
#include <fallback.h>
-#if CONFIG_HAVE_OPTION_TABLE
-#include <option_table.h>
-#endif
#ifndef CONFIG_MAX_REBOOT_CNT
#error "CONFIG_MAX_REBOOT_CNT not defined"
#error "CONFIG_MAX_REBOOT_CNT too high"
#endif
-static unsigned char cmos_read(unsigned char addr)
-{
- int offs = 0;
- if (addr >= 128) {
- offs = 2;
- addr -= 128;
- }
- outb(addr, RTC_BASE_PORT + offs + 0);
- return inb(RTC_BASE_PORT + offs + 1);
-}
-
-static void cmos_write(unsigned char val, unsigned char addr)
-{
- int offs = 0;
- if (addr >= 128) {
- offs = 2;
- addr -= 128;
- }
- outb(addr, RTC_BASE_PORT + offs + 0);
- outb(val, RTC_BASE_PORT + offs + 1);
-}
-
static int cmos_error(void)
{
unsigned char reg_d;
static int cmos_chksum_valid(void)
{
-#if CONFIG_HAVE_OPTION_TABLE == 1
+#if CONFIG_USE_OPTION_TABLE
unsigned char addr;
unsigned long sum, old_sum;
sum = 0;
return (byte & (1<<1));
}
-static inline unsigned read_option(unsigned start, unsigned size, unsigned def)
+unsigned read_option(unsigned start, unsigned size, unsigned def)
{
-#if CONFIG_USE_OPTION_TABLE == 1
+#if CONFIG_USE_OPTION_TABLE
unsigned byte;
byte = cmos_read(start/8);
return (byte >> (start & 7U)) & ((1U << size) - 1U);
#include <lib.h> /* Prototypes */
#include <arch/io.h>
+#include "pc80/mc146818rtc.h"
/* Base Address */
#ifndef CONFIG_TTYS0_BASE
outb(0x01, CONFIG_TTYS0_BASE + UART_FCR);
/* Set Baud Rate Divisor to 12 ==> 115200 Baud */
outb(0x80 | UART_LCS, CONFIG_TTYS0_BASE + UART_LCR);
-#if CONFIG_USE_OPTION_TABLE == 1
+#if CONFIG_USE_OPTION_TABLE
static const unsigned char divisor[] = { 1,2,3,6,12,24,48,96 };
unsigned ttys0_div, ttys0_index;
ttys0_index = read_option(CMOS_VSTART_baud_rate, CMOS_VLEN_baud_rate, 0);
extern void uart8250_init(unsigned base_port, unsigned divisor, unsigned lcs);
void uart_init(void)
{
-#if CONFIG_USE_OPTION_TABLE == 1
+#if CONFIG_USE_OPTION_TABLE
static const unsigned char divisor[] = { 1,2,3,6,12,24,48,96 };
unsigned ttys0_div, ttys0_index;
ttys0_index = read_option(CMOS_VSTART_baud_rate, CMOS_VLEN_baud_rate, 0);
#include <ctype.h>
#include <errno.h>
#include <libgen.h>
+#define UTIL_BUILD_OPTION_TABLE
#include "../../src/include/pc80/mc146818rtc.h"
#include "../../src/include/boot/coreboot_tables.h"
projects / coreboot.git / commitdiff