src/mainboard/iwill/dk8x/romstage.c

   1 #define RAMINIT_SYSINFO 1
   2 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
   3
   4 #define SET_NB_CFG_54 1
   5
   6 //used by raminit
   7 #define QRANK_DIMM_SUPPORT 1
   8
   9 //used by incoherent_ht
  10 //#define K8_ALLOCATE_IO_RANGE 1
  11
  12 //used by init_cpus and fidvid
  13 #define SET_FIDVID 0
  14 //if we want to wait for core1 done before DQS training, set it to 0
  15 #define SET_FIDVID_CORE0_ONLY 1
  16
  17 #if CONFIG_K8_REV_F_SUPPORT == 1
  18 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  19 #endif
  20
  21 #include <stdint.h>
  22 #include <string.h>
  23 #include <device/pci_def.h>
  24 #include <device/pci_ids.h>
  25 #include <arch/io.h>
  26 #include <device/pnp_def.h>
  27 #include <arch/romcc_io.h>
  28 #include <cpu/x86/lapic.h>
  29 #include <pc80/mc146818rtc.h>
  30
  31 #include <console/console.h>
  32 #include <cpu/amd/model_fxx_rev.h>
  33 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  34 #include "northbridge/amd/amdk8/raminit.h"
  35 #include "cpu/amd/model_fxx/apic_timer.c"
  36
  37 #include "cpu/x86/lapic/boot_cpu.c"
  38 #include "northbridge/amd/amdk8/reset_test.c"
  39
  40 #include "cpu/x86/bist.h"
  41
  42 #include "lib/delay.c"
  43
  44 #include "northbridge/amd/amdk8/debug.c"
  45 #include "cpu/x86/mtrr/earlymtrr.c"
  46 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  47
  48 #include "northbridge/amd/amdk8/setup_resource_map.c"
  49
  50 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  51
  52 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  53
  54 /*
  55  * GPIO28 of 8111 will control H0_MEMRESET_L
  56  * GPIO29 of 8111 will control H1_MEMRESET_L
  57  */
  58 static void memreset_setup(void)
  59 {
  60         if (is_cpu_pre_c0()) {
  61                 /* Set the memreset low */
  62                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  63                 /* Ensure the BIOS has control of the memory lines */
  64                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  65         } else {
  66                 /* Ensure the CPU has controll of the memory lines */
  67                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  68         }
  69 }
  70
  71 static void memreset(int controllers, const struct mem_controller *ctrl)
  72 {
  73         if (is_cpu_pre_c0()) {
  74                 udelay(800);
  75                 /* Set memreset_high */
  76                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  77                 udelay(90);
  78         }
  79 }
  80
  81 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  82 {
  83 }
  84
  85 static inline int spd_read_byte(unsigned device, unsigned address)
  86 {
  87         return smbus_read_byte(device, address);
  88 }
  89
  90 #include "northbridge/amd/amdk8/amdk8.h"
  91 #include "northbridge/amd/amdk8/incoherent_ht.c"
  92 #include "northbridge/amd/amdk8/coherent_ht.c"
  93 #include "northbridge/amd/amdk8/raminit.c"
  94 #include "lib/generic_sdram.c"
  95 #include "lib/ramtest.c"
  96
  97  /* tyan does not want the default */
  98 #include "northbridge/amd/amdk8/resourcemap.c"
  99
 100 #include "cpu/amd/dualcore/dualcore.c"
 101
 102 #define DIMM0 0x50
 103 #define DIMM1 0x51
 104 #define DIMM2 0x52
 105 #define DIMM3 0x53
 106 #define DIMM4 0x54
 107 #define DIMM5 0x55
 108 #define DIMM6 0x56
 109 #define DIMM7 0x57
 110
 111 #include "cpu/amd/car/post_cache_as_ram.c"
 112
 113 #include "cpu/amd/model_fxx/init_cpus.c"
 114
 115 #include "cpu/amd/model_fxx/fidvid.c"
 116
 117 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 118 #include "northbridge/amd/amdk8/early_ht.c"
 119
 120 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 121 {
 122         static const uint16_t spd_addr[] = {
 123                         // first node
 124                         DIMM0, DIMM2, 0, 0,
 125                         DIMM1, DIMM3, 0, 0,
 126
 127                         // second node
 128                         DIMM4, DIMM6, 0, 0,
 129                         DIMM5, DIMM7, 0, 0,
 130         };
 131
 132         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
 133                 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 134
 135         int needs_reset;
 136         unsigned bsp_apicid = 0;
 137
 138         if (!cpu_init_detectedx && boot_cpu()) {
 139                 /* Nothing special needs to be done to find bus 0 */
 140                 /* Allow the HT devices to be found */
 141
 142                 enumerate_ht_chain();
 143
 144                 /* Setup the rom access for 4M */
 145                 amd8111_enable_rom();
 146         }
 147
 148         if (bist == 0) {
 149                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 150         }
 151
 152         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 153         uart_init();
 154         console_init();
 155
 156         /* Halt if there was a built in self test failure */
 157         report_bist_failure(bist);
 158
 159         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 160
 161         setup_default_resource_map();
 162
 163         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 164
 165 #if CONFIG_MEM_TRAIN_SEQ == 1
 166         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 167 #endif
 168         setup_coherent_ht_domain(); // routing table and start other core0
 169
 170         wait_all_core0_started();
 171 #if CONFIG_LOGICAL_CPUS==1
 172         // It is said that we should start core1 after all core0 launched
 173         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 174          * So here need to make sure last core0 is started, esp for two way system,
 175          * (there may be apic id conflicts in that case)
 176          */
 177         start_other_cores();
 178         wait_all_other_cores_started(bsp_apicid);
 179 #endif
 180
 181         /* it will set up chains and store link pair for optimization later */
 182         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 183
 184 #if SET_FIDVID == 1
 185
 186         {
 187                 msr_t msr;
 188                 msr=rdmsr(0xc0010042);
 189                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 190
 191         }
 192
 193         enable_fid_change();
 194
 195         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 196
 197         init_fidvid_bsp(bsp_apicid);
 198
 199         // show final fid and vid
 200         {
 201                 msr_t msr;
 202                 msr=rdmsr(0xc0010042);
 203                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 204
 205         }
 206 #endif
 207
 208         needs_reset = optimize_link_coherent_ht();
 209         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 210
 211         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 212         if (needs_reset) {
 213                 print_info("ht reset -\n");
 214                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 215         }
 216
 217         allow_all_aps_stop(bsp_apicid);
 218
 219         //It's the time to set ctrl in sysinfo now;
 220         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 221
 222         enable_smbus();
 223
 224 #if 0
 225         dump_smbus_registers();
 226 #endif
 227
 228         memreset_setup();
 229
 230         //do we need apci timer, tsc...., only debug need it for better output
 231         /* all ap stopped? */
 232         init_timer(); // Need to use TMICT to synconize FID/VID
 233         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 234
 235 #if 0
 236         dump_pci_devices();
 237 #endif
 238
 239         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 240
 241 }
 242