src/mainboard/ibm/e326/romstage.c

   1
   2 #include <stdint.h>
   3 #include <string.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include <stdlib.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include <console/console.h>
  13 #include "lib/ramtest.c"
  14
  15 #include <cpu/amd/model_fxx_rev.h>
  16 #include "northbridge/amd/amdk8/incoherent_ht.c"
  17 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  18 #include "northbridge/amd/amdk8/raminit.h"
  19 #include "cpu/amd/model_fxx/apic_timer.c"
  20 #include "lib/delay.c"
  21
  22 #include "cpu/x86/lapic/boot_cpu.c"
  23 #include "northbridge/amd/amdk8/reset_test.c"
  24 #include "northbridge/amd/amdk8/debug.c"
  25 #include "superio/nsc/pc87366/pc87366_early_serial.c"
  26
  27 #include "cpu/x86/mtrr/earlymtrr.c"
  28 #include "cpu/x86/bist.h"
  29
  30 #include "northbridge/amd/amdk8/setup_resource_map.c"
  31
  32 #define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
  33
  34 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  35
  36 static void memreset_setup(void)
  37 {
  38         if (is_cpu_pre_c0()) {
  39                 /* Set the memreset low */
  40                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
  41                 /* Ensure the BIOS has control of the memory lines */
  42                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  43         } else {
  44                 /* Ensure the CPU has controll of the memory lines */
  45                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
  46         }
  47 }
  48
  49 static void memreset(int controllers, const struct mem_controller *ctrl)
  50 {
  51         if (is_cpu_pre_c0()) {
  52                 udelay(800);
  53                 /* Set memreset_high */
  54                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
  55                 udelay(90);
  56         }
  57 }
  58
  59 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  60 {
  61         /* nothing to do */
  62 }
  63
  64 static inline int spd_read_byte(unsigned device, unsigned address)
  65 {
  66         return smbus_read_byte(device, address);
  67 }
  68
  69 #define QRANK_DIMM_SUPPORT 1
  70
  71 #include "northbridge/amd/amdk8/raminit.c"
  72 #include "resourcemap.c"
  73 #include "northbridge/amd/amdk8/coherent_ht.c"
  74 #include "lib/generic_sdram.c"
  75
  76 #if CONFIG_LOGICAL_CPUS==1
  77 #define SET_NB_CFG_54 1
  78 #endif
  79 #include "cpu/amd/dualcore/dualcore.c"
  80
  81 #define FIRST_CPU  1
  82 #define SECOND_CPU 1
  83 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
  84
  85
  86
  87 #include "cpu/amd/car/post_cache_as_ram.c"
  88
  89 #include "cpu/amd/model_fxx/init_cpus.c"
  90
  91 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  92 #include "northbridge/amd/amdk8/early_ht.c"
  93
  94 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  95 {
  96         static const struct mem_controller cpu[] = {
  97                 {
  98                         .node_id = 0,
  99                         .f0 = PCI_DEV(0, 0x18, 0),
 100                         .f1 = PCI_DEV(0, 0x18, 1),
 101                         .f2 = PCI_DEV(0, 0x18, 2),
 102                         .f3 = PCI_DEV(0, 0x18, 3),
 103                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 104                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 105                 },
 106 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 107                 {
 108                         .node_id = 1,
 109                         .f0 = PCI_DEV(0, 0x19, 0),
 110                         .f1 = PCI_DEV(0, 0x19, 1),
 111                         .f2 = PCI_DEV(0, 0x19, 2),
 112                         .f3 = PCI_DEV(0, 0x19, 3),
 113                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 114                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 115                 },
 116 #endif
 117         };
 118
 119         int needs_reset;
 120
 121         if (!cpu_init_detectedx && boot_cpu()) {
 122                 /* Nothing special needs to be done to find bus 0 */
 123                 /* Allow the HT devices to be found */
 124
 125                 enumerate_ht_chain();
 126
 127                 amd8111_enable_rom();
 128         }
 129
 130         if (bist == 0) {
 131                 init_cpus(cpu_init_detectedx);
 132         }
 133
 134         pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 135         uart_init();
 136         console_init();
 137
 138         /* Halt if there was a built in self test failure */
 139         report_bist_failure(bist);
 140
 141         setup_ibm_e326_resource_map();
 142
 143         needs_reset = setup_coherent_ht_domain();
 144
 145 #if CONFIG_LOGICAL_CPUS==1
 146         // It is said that we should start core1 after all core0 launched
 147         start_other_cores();
 148 #endif
 149         // automatically set that for you, but you might meet tight space
 150         needs_reset |= ht_setup_chains_x();
 151
 152         if (needs_reset) {
 153                 print_info("ht reset -\n");
 154                 soft_reset();
 155         }
 156
 157         enable_smbus();
 158
 159         memreset_setup();
 160         sdram_initialize(ARRAY_SIZE(cpu), cpu);
 161
 162         post_cache_as_ram();
 163
 164 }
 165