src/mainboard/tyan/s2881/romstage.c

   1 #define QRANK_DIMM_SUPPORT 1
   2
   3 #if CONFIG_LOGICAL_CPUS==1
   4 #define SET_NB_CFG_54 1
   5 #endif
   6
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <device/pci_def.h>
  10 #include <arch/io.h>
  11 #include <device/pnp_def.h>
  12 #include <arch/romcc_io.h>
  13 #include <cpu/x86/lapic.h>
  14 #include <pc80/mc146818rtc.h>
  15 #include <console/console.h>
  16 #include "lib/ramtest.c"
  17
  18 #include <cpu/amd/model_fxx_rev.h>
  19
  20 #include "northbridge/amd/amdk8/incoherent_ht.c"
  21 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  22 #include "northbridge/amd/amdk8/raminit.h"
  23 #include "cpu/amd/model_fxx/apic_timer.c"
  24 #include "lib/delay.c"
  25
  26 #include "cpu/x86/lapic/boot_cpu.c"
  27 #include "northbridge/amd/amdk8/reset_test.c"
  28 #include "northbridge/amd/amdk8/debug.c"
  29 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  30
  31 #include "cpu/x86/mtrr/earlymtrr.c"
  32 #include "cpu/x86/bist.h"
  33
  34 #include "northbridge/amd/amdk8/setup_resource_map.c"
  35
  36 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  37
  38 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  39
  40 static void memreset_setup(void)
  41 {
  42    if (is_cpu_pre_c0()) {
  43         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  44    }
  45    else {
  46         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  47    }
  48         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  49 }
  50
  51 static void memreset(int controllers, const struct mem_controller *ctrl)
  52 {
  53    if (is_cpu_pre_c0()) {
  54         udelay(800);
  55         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  56         udelay(90);
  57    }
  58 }
  59
  60 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  61 {
  62         /* nothing to do */
  63 }
  64
  65 static inline int spd_read_byte(unsigned device, unsigned address)
  66 {
  67         return smbus_read_byte(device, address);
  68 }
  69
  70 #include "northbridge/amd/amdk8/raminit.c"
  71 #include "resourcemap.c"
  72 #include "northbridge/amd/amdk8/coherent_ht.c"
  73 #include "lib/generic_sdram.c"
  74
  75 #include "cpu/amd/dualcore/dualcore.c"
  76
  77
  78
  79 #include "cpu/amd/car/post_cache_as_ram.c"
  80
  81 #include "cpu/amd/model_fxx/init_cpus.c"
  82
  83 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  84 #include "northbridge/amd/amdk8/early_ht.c"
  85
  86 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  87 {
  88         static const uint16_t spd_addr [] = {
  89                         (0xa<<3)|0, (0xa<<3)|2, 0, 0,
  90                         (0xa<<3)|1, (0xa<<3)|3, 0, 0,
  91 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  92                         (0xa<<3)|4, (0xa<<3)|6, 0, 0,
  93                         (0xa<<3)|5, (0xa<<3)|7, 0, 0,
  94 #endif
  95         };
  96
  97         int needs_reset;
  98         unsigned bsp_apicid = 0;
  99
 100         struct mem_controller ctrl[8];
 101         unsigned nodes;
 102
 103         if (!cpu_init_detectedx && boot_cpu()) {
 104                 /* Nothing special needs to be done to find bus 0 */
 105                 /* Allow the HT devices to be found */
 106
 107                 enumerate_ht_chain();
 108
 109                 /* Setup the amd8111 */
 110                 amd8111_enable_rom();
 111         }
 112
 113         if (bist == 0) {
 114                 bsp_apicid = init_cpus(cpu_init_detectedx);
 115         }
 116
 117 //      post_code(0x32);
 118
 119         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 120         uart_init();
 121         console_init();
 122
 123         /* Halt if there was a built in self test failure */
 124         report_bist_failure(bist);
 125
 126         setup_s2881_resource_map();
 127 #if 0
 128         dump_pci_device(PCI_DEV(0, 0x18, 0));
 129         dump_pci_device(PCI_DEV(0, 0x19, 0));
 130 #endif
 131
 132         needs_reset = setup_coherent_ht_domain();
 133
 134         wait_all_core0_started();
 135 #if CONFIG_LOGICAL_CPUS==1
 136         // It is said that we should start core1 after all core0 launched
 137         start_other_cores();
 138         wait_all_other_cores_started(bsp_apicid);
 139 #endif
 140
 141         needs_reset |= ht_setup_chains_x();
 142
 143         if (needs_reset) {
 144                 print_info("ht reset -\n");
 145                 soft_reset();
 146         }
 147
 148         enable_smbus();
 149 #if 0
 150         dump_spd_registers(&cpu[0]);
 151 #endif
 152 #if 0
 153         dump_smbus_registers();
 154 #endif
 155
 156         allow_all_aps_stop(bsp_apicid);
 157
 158         nodes = get_nodes();
 159         //It's the time to set ctrl now;
 160         fill_mem_ctrl(nodes, ctrl, spd_addr);
 161
 162         memreset_setup();
 163         sdram_initialize(nodes, ctrl);
 164
 165 #if 0
 166         dump_pci_devices();
 167 #endif
 168
 169         post_cache_as_ram();
 170 }
 171