src/mainboard/msi/ms9282/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2006 AMD
   5  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6  *
   7  * Copyright (C) 2006 MSI
   8  * Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  23  */
  24
  25 #define RAMINIT_SYSINFO 1
  26 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
  27
  28 #define SET_NB_CFG_54 1
  29
  30 //used by raminit
  31 #define QRANK_DIMM_SUPPORT 1
  32
  33 //used by init_cpus and fidvid
  34 #define SET_FIDVID 1
  35 //if we want to wait for core1 done before DQS training, set it to 0
  36 #define SET_FIDVID_CORE0_ONLY 1
  37
  38 #include <stdint.h>
  39 #include <string.h>
  40 #include <device/pci_def.h>
  41 #include <arch/io.h>
  42 #include <device/pnp_def.h>
  43 #include <arch/romcc_io.h>
  44 #include <cpu/x86/lapic.h>
  45 #include "option_table.h"
  46 #include "pc80/mc146818rtc_early.c"
  47 #include <console/console.h>
  48
  49 #include <cpu/amd/model_fxx_rev.h>
  50 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
  51 #include "northbridge/amd/amdk8/raminit.h"
  52 #include "cpu/amd/model_fxx/apic_timer.c"
  53 #include "lib/delay.c"
  54
  55 #include "cpu/x86/lapic/boot_cpu.c"
  56 #include "northbridge/amd/amdk8/reset_test.c"
  57 #include "northbridge/amd/amdk8/debug.c"
  58 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
  59
  60 #include "cpu/x86/mtrr/earlymtrr.c"
  61 #include "cpu/x86/bist.h"
  62
  63 #include "northbridge/amd/amdk8/setup_resource_map.c"
  64
  65 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
  66 #define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)
  67
  68 #include <device/pci_ids.h>
  69 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
  70
  71 static void memreset(int controllers, const struct mem_controller *ctrl)
  72 {
  73 }
  74
  75 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  76 {
  77 #define SMBUS_SWITCH1 0x70
  78 #define SMBUS_SWITCH2 0x72
  79         unsigned device=(ctrl->channel0[0])>>8;
  80         smbus_send_byte(SMBUS_SWITCH1, device);
  81        smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
  82 }
  83
  84 #if 0
  85 static inline void change_i2c_mux(unsigned device)
  86 {
  87 #define SMBUS_SWITCH1 0x70
  88 #define SMBUS_SWITHC2 0x72
  89         smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
  90        smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
  91 }
  92 #endif
  93
  94 static inline int spd_read_byte(unsigned device, unsigned address)
  95 {
  96        return smbus_read_byte(device, address);
  97 }
  98
  99 //#define K8_4RANK_DIMM_SUPPORT 1
 100
 101 #include "northbridge/amd/amdk8/amdk8_f.h"
 102 #include "northbridge/amd/amdk8/incoherent_ht.c"
 103 #include "northbridge/amd/amdk8/coherent_ht.c"
 104 #include "northbridge/amd/amdk8/raminit_f.c"
 105 #include "lib/generic_sdram.c"
 106
 107  /* msi does not want the default */
 108 #include "resourcemap.c"
 109 #include "cpu/amd/dualcore/dualcore.c"
 110
 111 #define MCP55_NUM 1
 112 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 113 //set GPIO to input mode
 114 #define MCP55_MB_SETUP \
 115                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
 116                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
 117                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
 118                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
 119
 120 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 121
 122 #include "cpu/amd/car/post_cache_as_ram.c"
 123
 124 #include "cpu/amd/model_fxx/init_cpus.c"
 125 #include "cpu/amd/model_fxx/fidvid.c"
 126
 127 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 128 #include "northbridge/amd/amdk8/early_ht.c"
 129
 130 static void sio_setup(void)
 131 {
 132         uint32_t dword;
 133         uint8_t byte;
 134
 135         byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
 136         byte |= 0x20;
 137         pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
 138
 139         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
 140         dword |= (1<<0);
 141         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
 142 }
 143
 144 //CPU 1 mem is on SMBUS_HUB channel 2, and CPU 2 mem is on channel 1.
 145 #define RC0 (2<<8)
 146 #define RC1 (1<<8)
 147
 148 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 149 {
 150         static const uint16_t spd_addr[] = {
 151                 // Node 0
 152                 RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6,
 153                 RC0|(0xa<<3)|1, RC0|(0xa<<3)|3, RC0|(0xa<<3)|5, RC0|(0xa<<3)|7,
 154                 // node 1
 155                 RC1|(0xa<<3)|0, RC1|(0xa<<3)|2, RC1|(0xa<<3)|4, RC1|(0xa<<3)|6,
 156                 RC1|(0xa<<3)|1, RC1|(0xa<<3)|3, RC1|(0xa<<3)|5, RC1|(0xa<<3)|7,
 157         };
 158
 159         unsigned bsp_apicid = 0;
 160         int needs_reset;
 161         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
 162                 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 163
 164         if (!cpu_init_detectedx && boot_cpu()) {
 165                 /* Nothing special needs to be done to find bus 0 */
 166                 /* Allow the HT devices to be found */
 167
 168                 enumerate_ht_chain();
 169
 170                 sio_setup();
 171
 172                 /* Setup the mcp55 */
 173                 mcp55_enable_rom();
 174         }
 175
 176         if (bist == 0) {
 177                //init_cpus(cpu_init_detectedx);
 178                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 179         }
 180
 181         w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 182         uart_init();
 183         console_init();
 184
 185         /* Halt if there was a built in self test failure */
 186         report_bist_failure(bist);
 187
 188         setup_ms9282_resource_map();
 189
 190         setup_coherent_ht_domain();
 191
 192         wait_all_core0_started();
 193
 194 #if CONFIG_LOGICAL_CPUS==1
 195         // It is said that we should start core1 after all core0 launched
 196         start_other_cores();
 197         //wait_all_other_cores_started(bsp_apicid);
 198 #endif
 199         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 200
 201         init_timer(); /* Need to use TMICT to synconize FID/VID. */
 202
 203         needs_reset = optimize_link_coherent_ht();
 204         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 205         needs_reset |= mcp55_early_setup_x();
 206
 207         if (needs_reset) {
 208                 print_info("ht reset -\n");
 209                 soft_reset();
 210         }
 211
 212         //It's the time to set ctrl now;
 213         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 214
 215        enable_smbus();
 216
 217 #if 0
 218         int i;
 219         for(i=4;i<8;i++) {
 220                 change_i2c_mux(i);
 221                 dump_smbus_registers();
 222         }
 223 #endif
 224
 225        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 226
 227        post_cache_as_ram();
 228 }
 229