src/mainboard/tyan/s2885/romstage.c

   1
   2 #include <stdint.h>
   3 #include <string.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include "option_table.h"
  10 #include "pc80/mc146818rtc_early.c"
  11 #include <console/console.h>
  12 #include "lib/ramtest.c"
  13
  14 #include <cpu/amd/model_fxx_rev.h>
  15
  16 #include "northbridge/amd/amdk8/incoherent_ht.c"
  17 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  18 #include "northbridge/amd/amdk8/raminit.h"
  19 #include "cpu/amd/model_fxx/apic_timer.c"
  20 #include "lib/delay.c"
  21
  22 #include "cpu/x86/lapic/boot_cpu.c"
  23 #include "northbridge/amd/amdk8/reset_test.c"
  24 #include "northbridge/amd/amdk8/debug.c"
  25 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  26
  27 #include "cpu/x86/mtrr/earlymtrr.c"
  28 #include "cpu/x86/bist.h"
  29
  30 #include "northbridge/amd/amdk8/setup_resource_map.c"
  31
  32 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  33
  34 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  35
  36 static void memreset_setup(void)
  37 {
  38    if (is_cpu_pre_c0()) {
  39         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
  40    }
  41    else {
  42         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
  43    }
  44         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
  45 }
  46
  47 static void memreset(int controllers, const struct mem_controller *ctrl)
  48 {
  49    if (is_cpu_pre_c0()) {
  50         udelay(800);
  51         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
  52         udelay(90);
  53    }
  54 }
  55
  56 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  57 {
  58         /* nothing to do */
  59 }
  60
  61 static inline int spd_read_byte(unsigned device, unsigned address)
  62 {
  63         return smbus_read_byte(device, address);
  64 }
  65
  66 #define QRANK_DIMM_SUPPORT 1
  67
  68 #include "northbridge/amd/amdk8/raminit.c"
  69 #include "northbridge/amd/amdk8/coherent_ht.c"
  70 #include "lib/generic_sdram.c"
  71
  72  /* tyan does not want the default */
  73 #include "resourcemap.c"
  74
  75 #if CONFIG_LOGICAL_CPUS==1
  76 #define SET_NB_CFG_54 1
  77 #endif
  78 #include "cpu/amd/dualcore/dualcore.c"
  79
  80
  81
  82 #include "cpu/amd/car/post_cache_as_ram.c"
  83
  84 #include "cpu/amd/model_fxx/init_cpus.c"
  85
  86 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
  87 #include "northbridge/amd/amdk8/early_ht.c"
  88
  89 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  90 {
  91         static const uint16_t spd_addr [] = {
  92                         (0xa<<3)|0, (0xa<<3)|2, 0, 0,
  93                         (0xa<<3)|1, (0xa<<3)|3, 0, 0,
  94 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  95                         (0xa<<3)|4, (0xa<<3)|6, 0, 0,
  96                         (0xa<<3)|5, (0xa<<3)|7, 0, 0,
  97 #endif
  98         };
  99
 100         int needs_reset;
 101         unsigned bsp_apicid = 0;
 102
 103         struct mem_controller ctrl[8];
 104         unsigned nodes;
 105
 106         if (!cpu_init_detectedx && boot_cpu()) {
 107                 /* Nothing special needs to be done to find bus 0 */
 108                 /* Allow the HT devices to be found */
 109
 110                 enumerate_ht_chain();
 111
 112                 /* Setup the amd8111 */
 113                 amd8111_enable_rom();
 114         }
 115
 116         if (bist == 0) {
 117                 bsp_apicid = init_cpus(cpu_init_detectedx);
 118         }
 119
 120 //      post_code(0x32);
 121
 122         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 123         uart_init();
 124         console_init();
 125
 126 //      dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 127
 128         /* Halt if there was a built in self test failure */
 129         report_bist_failure(bist);
 130
 131         setup_s2885_resource_map();
 132 #if 0
 133         dump_pci_device(PCI_DEV(0, 0x18, 0));
 134         dump_pci_device(PCI_DEV(0, 0x19, 0));
 135 #endif
 136
 137         needs_reset = setup_coherent_ht_domain();
 138
 139         wait_all_core0_started();
 140 #if CONFIG_LOGICAL_CPUS==1
 141         // It is said that we should start core1 after all core0 launched
 142         start_other_cores();
 143         wait_all_other_cores_started(bsp_apicid);
 144 #endif
 145
 146         needs_reset |= ht_setup_chains_x();
 147
 148         if (needs_reset) {
 149                 print_info("ht reset -\n");
 150                 soft_reset();
 151         }
 152
 153         allow_all_aps_stop(bsp_apicid);
 154
 155         nodes = get_nodes();
 156         //It's the time to set ctrl now;
 157         fill_mem_ctrl(nodes, ctrl, spd_addr);
 158
 159         enable_smbus();
 160
 161         memreset_setup();
 162         sdram_initialize(nodes, ctrl);
 163
 164 #if 0
 165         dump_pci_devices();
 166 #endif
 167
 168         post_cache_as_ram();
 169
 170 }
 171