Nils Jacobs [Wed, 3 Nov 2010 13:21:41 +0000 (13:21 +0000)]
Clean up some more comments and white space in model_gx2/cpureginit.c.
This is Abuild and boot tested.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6015
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Nils Jacobs [Wed, 3 Nov 2010 13:19:50 +0000 (13:19 +0000)]
Clean up some comments and white space in gx2/northbridgeinit.c
and gx2/raminit.c.
This is Abuild and boot tested.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6014
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Tobias Diedrich [Tue, 2 Nov 2010 21:24:29 +0000 (21:24 +0000)]
Need to clear downstream read cycle retry bit, or the bus scan will
hang. Also need to set lane config to 0x00 for autonegotiation.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6013
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Tobias Diedrich [Tue, 2 Nov 2010 20:54:37 +0000 (20:54 +0000)]
This adds pci device ids and pci_driver structs for the K8T890 CF
variant. It also adds additional dev_find_device calls in k8t890_ctrl.c for
subfunctions 3 and 7.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6012
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Nils Jacobs [Mon, 1 Nov 2010 15:20:27 +0000 (15:20 +0000)]
Change Geode GX2 to use the auto DRAM detect code from Geode LX.
Also, change the GX2 boards to use it.
Add a processor speed setting function in human readable MHz and remove
the useless and broken PLLMSR settings (the processor speed was hardcoded
to 366MHz in pll_reset.c).
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6011
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Nils Jacobs [Mon, 1 Nov 2010 14:39:49 +0000 (14:39 +0000)]
Remove some unused code.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6010
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Nils Jacobs [Mon, 1 Nov 2010 14:36:54 +0000 (14:36 +0000)]
GX2: Clean up some white space and comments.
Also, add a copyright header to pll_reset.c.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6009
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Nils Jacobs [Mon, 1 Nov 2010 14:18:11 +0000 (14:18 +0000)]
GX2: Change MSR register numbers into more descriptive names.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6008
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Uwe Hermann [Sun, 31 Oct 2010 23:24:18 +0000 (23:24 +0000)]
Remove definitions of ACPI_SSDTX_NUM to 0, that's the default anyway.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6007
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Uwe Hermann [Sun, 31 Oct 2010 19:37:50 +0000 (19:37 +0000)]
Remove incorrect IOAPIC lines from some mptable.c files.
- via/epia-n/mptable.c
- intel/eagleheights/mptable.c (commented out anyway)
- asus/p2b-d/mptable.c
- asus/p2b-ds/mptable.c
Some files still incorrectly contain some smp_write_ioapic() lines from
the original mptable utility target (Supermicro P4DPE), which has one
IOAPIC in the southbridge (Intel ICH3-S), two IOAPICs contained in
the first P64H2, and two more in the second P64H2, i.e. 5 IOAPICs in total.
However, none of the boards where this chunk of code is present has
multiple IOAPICs (and even if they had, the PCI devices where those are
located would probably be different anyway), so drop the incorrect
mptable.c contents.
Also drop the lines from the mptable utility, so that future mptable.c files
don't incorrectly inherit any of this stuff.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6006
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Scott Duplichan [Sun, 31 Oct 2010 14:17:51 +0000 (14:17 +0000)]
Fix AMD family 10h engineering sample is reported as 'thermal test kit'.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6005
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Uwe Hermann [Sat, 30 Oct 2010 21:27:13 +0000 (21:27 +0000)]
Mptable related fixes for ASUS P2B-DS.
- Add "select IOAPIC" in the board's Kconfig file.
- Set CONFIG_MAX_PHYSICAL_CPUS to 2 on the board. There are two
CPU sockets (Slot 1) and each CPU can only have one core, multi-core CPUs
didn't exist in that era (CONFIG_MAX_CPUS was set to 2 already).
- Drop useless/duplicated enable_lapic() call from ASUS P2B-DS's romstage.c,
that function is always called if either CONFIG_SMP and/or CONFIG_IOAPIC
are set.
- Rework ASUS P2B-DS mptable.c to fix a number of things:
- Convert it to use mptable_write_buses() as all mptable.c files should do.
- Fix incorrect IOAPICID (it's 0x11 for the external
82093AA IOAPIC).
- Fix a bunch of hardcoded bus IDs, remove incorrect entries, etc.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6004
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jonathan Kollasch [Fri, 29 Oct 2010 20:40:06 +0000 (20:40 +0000)]
Use common code to set PCI subsystem in mcp55.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6003
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jonathan Kollasch [Fri, 29 Oct 2010 15:56:04 +0000 (15:56 +0000)]
Deduplicate ck804 subsystem-setting functionality.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6002
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Uwe Hermann [Fri, 29 Oct 2010 14:26:27 +0000 (14:26 +0000)]
Drop duplicate HAVE_ACPI_TABLES (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6001
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jonathan Kollasch [Thu, 28 Oct 2010 19:57:52 +0000 (19:57 +0000)]
The no point in having a non-NULL ops_pci pointer when the set_subsystem operation within is NULL anyway.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6000
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Uwe Hermann [Thu, 28 Oct 2010 14:22:20 +0000 (14:22 +0000)]
Fix broken build due to missing #if CONFIG_IOAPIC.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5999
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Uwe Hermann [Thu, 28 Oct 2010 08:19:22 +0000 (08:19 +0000)]
Add IOAPIC support for Intel
82371EB and fixup SMP on ASUS P2B-D.
- Add enable_intel_82093aa_ioapic() which enables IOAPIC usage in the
Intel
82371EB southbridge (sets the proper chip-select) and sets an
IOAPIC ID.
- We only call enable_intel_82093aa_ioapic() if a board does "select IOAPIC"
as on
82371EB-based boards the IOAPIC is an external chip (not integrated
in the southbridge) and it's only populated on multi-CPU boards.
That is, we cannot unconditionally enable it, only on SMP-capable boards.
- Due to the reason explained above, remove "select IOAPIC" from
src/southbridge/intel/i82371eb/Kconfig, and add it to
src/mainboard/asus/p2b-d/Kconfig.
- Also set CONFIG_MAX_PHYSICAL_CPUS to 2 on ASUS P2B-D. There are two
CPU sockets (Slot 1) and each CPU can only have one core, multi-core CPUs
didn't exist in that era (CONFIG_MAX_CPUS was set to 2 already).
- Drop useless/duplicated enable_lapic() call from ASUS P2B-D's romstage.c,
that function is always called if either CONFIG_SMP and/or CONFIG_IOAPIC
are set.
- Rework ASUS P2B-D mptable.c to fix a number of things:
- Convert it to use mptable_write_buses() as all mptable.c files should do.
- Fix incorrect IOAPICID (it's 0x11 for the external
82093AA IOAPIC).
- Fix a bunch of hardcoded bus IDs, remove incorrect entries, etc.
This is build-tested on ASUS P2B-D, and also boot-tested successfully there.
On Linux I now get two entries in /proc/cpuinfo (where only one appeared
before this patch), i.e. both populated CPUs are found.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5998
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jonathan Kollasch [Wed, 27 Oct 2010 20:32:49 +0000 (20:32 +0000)]
Enable CK804 AC'97 audio interface and explicitly enable NIC on A8N-E.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5997
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jonathan Kollasch [Wed, 27 Oct 2010 20:30:32 +0000 (20:30 +0000)]
Correct an apparent copy-paste error that shows up at compile time on
boards using ck804_early_setup.c that select CK804_USE_NIC.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5996
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jonathan Kollasch [Wed, 27 Oct 2010 17:41:40 +0000 (17:41 +0000)]
Drop referenced-yet-does-nothing static function from ms7135 romstage.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5995
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jonathan Kollasch [Wed, 27 Oct 2010 17:26:57 +0000 (17:26 +0000)]
Convert ck804_early_smbus.c to a separately compiled unit.
Additionally, make the second SMBus more accessible in romstage.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5994
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Uwe Hermann [Tue, 26 Oct 2010 22:46:43 +0000 (22:46 +0000)]
Convert some comments to proper Doxygen syntax.
Also, make them all fit in 80chars/column, fix some whitespace issues
and also some typos I noticed.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5993
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Tobias Diedrich [Tue, 26 Oct 2010 22:40:16 +0000 (22:40 +0000)]
We need to call smp_write_lintsrc() instead of smp_write_intsrc() for
local ints. This is wrong in most coreboot mptables, probably all
generated by util/mptable/mptable.c.
After fixing this now XP can boot in MPS mode on my M2V.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5992
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jonathan Kollasch [Tue, 26 Oct 2010 16:10:20 +0000 (16:10 +0000)]
Convert all ck804-based boards to tiny bootblock.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5991
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Tue, 26 Oct 2010 15:51:57 +0000 (15:51 +0000)]
Move bcm5785_enable_rom.c include to where it's used.
Right now, it breaks the build of bootblock enabled boards
with that chipset.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5990
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Patrick Georgi [Tue, 26 Oct 2010 15:11:45 +0000 (15:11 +0000)]
reg is only used inside the #if clause, so declare it there. trivial.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5989
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Scott Duplichan [Tue, 26 Oct 2010 05:26:01 +0000 (05:26 +0000)]
When gcc 4.5.0 is used, compiling mcp55_early_setup_car.c fails. This change eliminates the compiler warning that causes the build to fail.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5988
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Uwe Hermann [Mon, 25 Oct 2010 15:32:07 +0000 (15:32 +0000)]
Factor out common mptable code to mptable_init().
- Drop sig[], oem[], and productid[] fields in all mptable.c files, no
longer needed. The sig[] is always the same ("PCMP"), the oem[] is
currently also always the same ("COREBOOT"), and productid is being
passed into mptable_init() directly as string now.
- LAPIC_ADDR is passed in as parameter, too. While at the moment it's
always the same value that is passed in, the LAPIC base address could
also be relocated theoretically, so keep it as parameter for now.
- Fix a few productid entries, they were (partially) incorrect:
- DK8S2 (was "DK8X", copypaste)
- 939A785GMH (was "MAHOGANY", copypaste)
- X6DHE-G (was "X6DHE", incomplete board name)
- H8DME-2 (was "H8DMR", copypaste)
- H8QME-2+ (was "H8QME", incomplete board name)
- X6DHE-G2 (was "X6DHE", incomplete board name)
- X6DHR-iG2 (was "X6DHR-iG", incomplete board name)
- GA-M57SLI-S4 (was "M57SLI", incomplete board name)
- KINO-780AM2 (was "KINO", incomplete board name)
- DL145 G1 (was "DL145G1", small fix as per vendor website)
- DL145 G3 (was "TREX", wrong board name)
- DL165 G6 (was "HP DL165 G6", drop vendor)
- S2912 (was "S2895", copypaste)
- VT8454c (was "VIA VT8454C", drop vendor, lower-case "c")
- EPIA-N (was "P4DPE", copypaste)
- pc2500e (was "PC2500", incorrect name)
- S1850 (was "S2850", copy-paste)
- MS-7135 (was "MS7135")
- MS-9282 (was "MS9282")
- MS-9185 (was "MS9185")
- MS-9652 (was "K9ND MS-9652")
- Ultra 40 (was "ultra40")
- E326 (was "E325", copypaste)
- M4A785-M (was "TILAPIA", copypaste)
- P2B-D (was "ASUS P2B-D", drop vendor)
- P2B-DS (was "ASUS P2B-DS", drop vendor)
- Adapt the mptable utility to use mptable_init() too.
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5987
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Peter Stuge [Mon, 25 Oct 2010 02:12:04 +0000 (02:12 +0000)]
Make ectool -i work; add missing break
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5986
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Scott Duplichan [Sun, 24 Oct 2010 16:22:11 +0000 (16:22 +0000)]
Running a checked build of Windows is needed for understanding its various BIOS related BSODs. Win7 checked build complains when running coreboot+seabios:
FADT revision inconsistent with length.
Revision: 0x1
Length: 0xf4
Expected Length: 0x74
Change the FADT revision from 1 to 3 to match its length and prevent the Windows checked build assert.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5985
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Uwe Hermann [Sun, 24 Oct 2010 14:19:09 +0000 (14:19 +0000)]
Add small comment about LDN 5 on
F71872F/FG /
F71806F/FG.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5984
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jonathan Kollasch [Sun, 24 Oct 2010 14:18:55 +0000 (14:18 +0000)]
Fix superiotool build on non-NetBSD x86_64.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5983
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jonathan Kollasch [Sun, 24 Oct 2010 14:10:35 +0000 (14:10 +0000)]
Provide for I/O space access on NetBSD.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5982
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Idwer Vollering [Sun, 24 Oct 2010 13:50:13 +0000 (13:50 +0000)]
Add inteltool support for FreeBSD.
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Acked-by Stefan Reinauer <stepan@coreboot.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5981
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Idwer Vollering [Sun, 24 Oct 2010 13:42:32 +0000 (13:42 +0000)]
Update superiotool support for FreeBSD, Makefile fixes.
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5980
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jonathan Kollasch [Sun, 24 Oct 2010 12:43:41 +0000 (12:43 +0000)]
Teach superiotool about the registers in a Fintek F71806 (and F71872).
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5979
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Uwe Hermann [Wed, 20 Oct 2010 20:21:27 +0000 (20:21 +0000)]
Revert sblk/sblink change, use sblk like the rest of the codebase does.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5978
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Myles Watson [Wed, 20 Oct 2010 19:23:22 +0000 (19:23 +0000)]
Now that no boards set RAMBASE < 1M, get rid of some dead code. Trivial.
It's probably time to reconsider moving all fam10 boards to RAMBASE = 1M.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5977
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Scott Duplichan [Tue, 19 Oct 2010 21:08:11 +0000 (21:08 +0000)]
For AMD family 10h processors, msr
c0010058 is always programmed
for 256 buses, even if fewer are configured. This patch lets msr
c0010058 programming use the configured bus count, CONFIG_MMCONF_BUS_NUMBER.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5976
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jonathan Kollasch [Tue, 19 Oct 2010 15:25:06 +0000 (15:25 +0000)]
Drop duplicate SB_HT_CHAIN_ON_BUS0 in Kconfig for MS-7135.
Trivial.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5975
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jonathan Kollasch [Tue, 19 Oct 2010 15:17:18 +0000 (15:17 +0000)]
Use the correct (W83627THF, not W83627HF) superio code in MS-7135 romstage.
This is consistent with the device tree and the chip actually on the board.
Trivial.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5974
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jonathan Kollasch [Tue, 19 Oct 2010 14:02:10 +0000 (14:02 +0000)]
Copy ICH4 hard_reset() for 6300ESB.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5973
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jonathan Kollasch [Tue, 19 Oct 2010 13:49:11 +0000 (13:49 +0000)]
Remove unused variables from 6300ESB smbus_write_block().
#ifdef DEADCODE out smbus_write_byte() and smbus_write_block() as
they are static and nothing uses them or are incompletely implemented.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5972
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jonathan Kollasch [Tue, 19 Oct 2010 13:39:38 +0000 (13:39 +0000)]
Correct spelling of "spacing" (in comments).
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5971
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jonathan Kollasch [Tue, 19 Oct 2010 13:11:56 +0000 (13:11 +0000)]
Use mptable_write_buses().
Remove unhelpful comment.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5970
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jonathan Kollasch [Tue, 19 Oct 2010 13:03:34 +0000 (13:03 +0000)]
Modernize socket_754 Kconfig with CAR and address bits information.
Also, update the board that uses this socket to match.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5969
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Scott Duplichan [Tue, 19 Oct 2010 04:58:49 +0000 (04:58 +0000)]
Revision 5966 changed the end of line style of the 3 modified files. This change restores the original end of line style.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Scott Duplichan <scott@notabs.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5968
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Scott Duplichan [Tue, 19 Oct 2010 04:36:42 +0000 (04:36 +0000)]
To reduce boot time, remove the double startup IPI and 10 ms delay from lapic_cpu_init.c. The change is
currently restricted to recent model AMD processors, though it could be applied to others after successful testing.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5967
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Scott Duplichan [Tue, 19 Oct 2010 04:26:17 +0000 (04:26 +0000)]
When debug logging is enabled, a message such as '* AP 02 timed out:
02010501'
is sometimes logged. The reason is that the AP first sets a completion value
such as 0x13, which is what function wait_cpu_state() is waiting for. Then a
short time later, the AP calls function init_fidvid_ap(). This function sets
a completion value of 01. When logging is off, wait_cpu_state is fast enough
to see the initial completion value for each of the APs. But with logging
enabled, one or more APs may go on to complete function init_fidvid_ap, which
sets the completion value to 01. While mostly harmless, the timeout does
increase boot time. This patch eliminates the timeout by making function
wait_cpu_state recognize 01 as an additional valid AP completion value.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5966
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Scott Duplichan [Mon, 18 Oct 2010 04:01:12 +0000 (04:01 +0000)]
This patch enables SB700 option PrefetchEnSPIFromHost in early setup.
It affects only systems booting from SPI flash, not those booting from
LPC flash. By default, the SB700 reads dwords from the SPI flash chip.
Setting PrefetchEnSPIFromHost causes the SB700 to read entire cache
lines from the flash chip.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5965
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Mon, 18 Oct 2010 00:21:39 +0000 (00:21 +0000)]
update intel microcode files.
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5964
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Uwe Hermann [Mon, 18 Oct 2010 00:20:40 +0000 (00:20 +0000)]
Make update-microcodes.sh executable.
This also has an additional benefit:
I was running "sh update-microcodes.sh" previously which broke with
update-microcodes.sh: 102: Bad substitution
due to the script requiring /bin/bash instead of /bin/sh (uses bash-specific
stuff). Running "bash update-microcodes.sh" works fine.
Making the script executable in svn reduces the likelyhood of people
running the script with differing shells that may not work.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5963
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Uwe Hermann [Mon, 18 Oct 2010 00:00:57 +0000 (00:00 +0000)]
Cosmetics and coding style fixes in devices/*.
- Whitespace and indentation fixes in various places.
- Fix various typos.
- Use u8, u16 etc. everywhere.
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5962
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Sun, 17 Oct 2010 23:55:17 +0000 (23:55 +0000)]
update intel microcode update script
Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5961
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Keith Hui [Sun, 17 Oct 2010 22:07:08 +0000 (22:07 +0000)]
Removes model_65x CPUIDs from model_6xx code.
They now have their own home at cpu/intel/model_65x.
Signed-off-by: Keith Hui <buurin@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5960
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Liu Tao [Sun, 17 Oct 2010 21:59:43 +0000 (21:59 +0000)]
In the RS780/RS690 ProgK8TempMmioBase() function, the dst-link field is set
to zero, so for boards with RS780 not on CPU's HT chain 0, the function will
mis-configure the MMIO dst-link routing, and the following enable_pcie_bar3()
function will hang when it visits the MMIO.
The following patch fixes the problem, and is tested on a K8 board with RS780
on HT chain 1.
Signed-off-by: Liu Tao <liutao1980@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5959
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Liu Tao [Sun, 17 Oct 2010 21:34:45 +0000 (21:34 +0000)]
We currently read the CPU HT speed from HT chain 0's register.
Fix that to read the register from the chain where the SB chip is on.
Signed-off-by: Liu Tao <liutao1980@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5958
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Uwe Hermann [Sun, 17 Oct 2010 19:30:58 +0000 (19:30 +0000)]
Add more missing GPL-headers, fix inconsistencies in others.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5957
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Uwe Hermann [Sun, 17 Oct 2010 19:13:18 +0000 (19:13 +0000)]
Use common GPL-header format in CK804 files, add missing ones (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5956
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Uwe Hermann [Sun, 17 Oct 2010 19:01:48 +0000 (19:01 +0000)]
Various Doxygen comment fixes, typo fixes, etc.
- Fix incorrect argument names for @param entries.
- Add missing @param and @return entries, partly as TODOs.
- s/@returns/@return/, that's a typo.
- Small whitespace fixes while I'm at it.
- Drop useless @brief commands, they just clutter the comments and make them
harder to read. Doxygen has an option to always use the first sentence
of a Doxygen-comment as @brief automatically (should be on per default).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5955
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Keith Hui [Sat, 16 Oct 2010 08:45:31 +0000 (08:45 +0000)]
Move support for Deschutes Slot 1 CPUs (model_65x) into its own directory.
abuild-tested. I have no Deschutes CPUs to boot test this with.
Signed-off-by: Keith Hui <buurin@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5954
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Uwe Hermann [Fri, 15 Oct 2010 07:47:51 +0000 (07:47 +0000)]
Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets.
This CAR implementation hardcodes the Cache-as-RAM base address to:
0xd0000 - CacheSize
so the DCACHE_RAM_BASE is never actually used for this implementation
and these sockets.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5953
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Uwe Hermann [Thu, 14 Oct 2010 23:40:10 +0000 (23:40 +0000)]
Cosmetics in ioapic.c (trivial, no functional changes).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5952
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Uwe Hermann [Wed, 13 Oct 2010 23:00:41 +0000 (23:00 +0000)]
Remove various .c #includes from Intel i810/i82801ax/i82801bx boards.
This is pretty much the same mechanism as in r5929.
- Use 'romstage-y' to turn i82801ax_early_smbus.c and i82801bx_early_smbus.c
into distinct compilation units, and don't #include the files anymore
in romstage.c files.
- Ditto for northbridge/intel/i82810/raminit.c, and
northbridge/intel/i82810/debug.c.
- Add various header files which are now needed, drop unused includes.
- Make functions that need to be visible non-static.
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5951
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Keith Hui [Wed, 13 Oct 2010 17:00:42 +0000 (17:00 +0000)]
Move out Katmai Slot 1 CPUs (model_67x) from model_6xx to model_67x.
abuild-tested. Boot tested on P2B-LS.
Signed-off-by: Keith Hui <buurin@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5950
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Uwe Hermann [Wed, 13 Oct 2010 08:21:44 +0000 (08:21 +0000)]
Convert all Intel i810 boards to CAR.
- Drop "select ROMCC" from the boards, as well as early_mtrr stuff.
- Add "select CACHE_AS_RAM" to socket_PGA370/Kconfig, as well as the
usual DCACHE_RAM_BASE and DCACHE_RAM_SIZE variables.
- In socket_PGA370/Makefile.inc add:
cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc
- Other smaller related fixes.
Abuild-tested and boot-tested on MSI MS-6178.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5949
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Peter Stuge [Wed, 13 Oct 2010 06:23:02 +0000 (06:23 +0000)]
Enable or disable the power button in Kconfig
Some mainboards need to disable the power button to avoid turning off
right after being turned on, while other boards ship with a jumper over
the power button and should allow the user to configure the behavior.
This adds infrastructure in the form of four mutually exclusive options
which can be selected in a mainboard Kconfig (power button forced on/off,
and user-controllable with default on/off) and one result bool which
source code can test. (Enable the button or not.)
The options have been implemented in CS5536 code and for all mainboards
which select SOUTHBRIDGE_AMD_CS5536, but should be used also by other
chipsets where applicable. Note that if chipset code uses the result
bool ENABLE_POWER_BUTTON, then every board using that chipset must
select one out of the four control options in order to build.
All touched boards should have unchanged behavior, except
pcengines/alix1c, traverse/geos and lippert/hurricane-lx where the
power button can now be configured by the user.
Build tested for alix1c, alix2d, hurricane-lx and wyse-s50. Confirmed
to work as advertised on alix1c both with button enabled and disabled.
Includes additional traverse/geos changes from Nathan and
lippert/hurricane-lx changes from Jens to correctly use the new
feature on those boards.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Aurelien Guillaume <aurelien@iwi.me>
Acked-by: Nils Jacobs <njacobs8@hetnet.nl>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5948
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Zheng Bao [Wed, 13 Oct 2010 05:16:48 +0000 (05:16 +0000)]
Fix a stupid bug in rs780 and rs690 code.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Scott Duplichan <scott@notabs.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5947
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Zheng Bao [Wed, 13 Oct 2010 02:46:59 +0000 (02:46 +0000)]
Trivial. Clean up code and add some comments.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5946
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Keith Hui [Tue, 12 Oct 2010 23:22:08 +0000 (23:22 +0000)]
Add missing include of model_6bx for slot_1.
I could no longer boot my P3B-F with my Tualeron and r5938. Dies with
"unknown CPU". I believe it will happen with any Slot 1 440BX boards
that supports model_6bx CPUs.
I need to make the change below to make it work. abuild tested. Boot
tested on P2B-LS and P3B-F.
Signed-off-by: Keith Hui <buurin@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5945
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Uwe Hermann [Tue, 12 Oct 2010 21:37:03 +0000 (21:37 +0000)]
Move translate_spd_to_i82810[] from .h to .c file (trivial).
This is in preparation of further i810 fixes and switching it to CAR.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5944
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Uwe Hermann [Tue, 12 Oct 2010 17:34:08 +0000 (17:34 +0000)]
We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it.
As both ioapic.h and acpi.h define a macro named "NMI", rename one
of them (NMI -> NMIType in acpi.h).
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5943
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Warren Turkal [Tue, 12 Oct 2010 06:13:40 +0000 (06:13 +0000)]
Reduce duplicate definition in CAR code.
Macros for the register addresses for the MTRR MSRs are already defined
in include/cpu/x86/car.h. This patch uses those macros instead of
creating a second instance of that same data.
I also added a few macros to the amd mtrr.h to make the MSR naming more
consistent.
Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5942
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Warren Turkal [Tue, 12 Oct 2010 06:12:00 +0000 (06:12 +0000)]
Build bootblock.S instead of bootblock.c.
The file is actually just including a bunch of assembly. The build rule
for bootblock.c even states that the file will be "assembler-with-cpp."
Signed-off-by: Warren Turkal <wt@penguintechs.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5941
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Sylvain Hitier [Mon, 11 Oct 2010 23:22:24 +0000 (23:22 +0000)]
Fix typo after r5925.
BTW, embed the always-the-same string instead of referencing it through "%s".
Do the same for i82371EB while we're at it.
Signed-off-by: Sylvain Hitier <sylvain.hitier@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5940
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Uwe Hermann [Mon, 11 Oct 2010 22:49:39 +0000 (22:49 +0000)]
Build fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5939
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Uwe Hermann [Mon, 11 Oct 2010 21:38:49 +0000 (21:38 +0000)]
First round of ICH2/ICH2-M cleanups after split from i82801xx.
- Drop all non-ICH2 "struct pci_driver" entries from all files.
- Kconfig: Add missing USE_WATCHDOG_ON_BOOT.
- Drop i82801bx_sata.c and i82801bx_usb_ehci.c, ICH2 doesn't have SATA/EHCI.
- Simplify lots of code, getting rid of i82801xx remainders.
- Use u8 et al (instead of uint8_t) in a few more places.
- Use #defines from header files where possible.
- Various other fixes and updates.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5938
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Uwe Hermann [Mon, 11 Oct 2010 19:36:13 +0000 (19:36 +0000)]
Factor out a few commonly duplicated functions from northbridge.c.
The following functions are moved to devices/device_util.c:
- ram_resource()
- tolm_test()
- find_pci_tolm()
There are only two tolm_test() / find_pci_tolm() which differ from the
defaults, one of them can easily be eliminated in a follow-up patch,
maybe even both, but for now keep it simple and only eliminate the majority.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5937
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Sun, 10 Oct 2010 22:05:02 +0000 (22:05 +0000)]
fix typo in minilzma.cc, found by Idwer.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5936
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Sun, 10 Oct 2010 21:15:53 +0000 (21:15 +0000)]
don't include unused code, we only need the header.
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5935
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Stefan Reinauer [Sun, 10 Oct 2010 21:15:01 +0000 (21:15 +0000)]
fix typos found by zbao in other files.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5934
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Rudolf Marek [Sun, 10 Oct 2010 20:43:00 +0000 (20:43 +0000)]
Same applies for SB600.
Following patch enables UDMA on ALL IDE devices. The current code enables it only for primary master, which causes my DVD drive to fail under windows install
and even after hard reset in linux (DMA seems lockup).
The fix should not have any influence for Linux because the IDE driver will
correctly reprogram this bit.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5933
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Rudolf Marek [Sun, 10 Oct 2010 19:55:32 +0000 (19:55 +0000)]
Following patch fixes the boot_switch_sata_ide logic. It can swap
primary / secondary IDE channel with SATA (in IDE mode).
The bug was that setup was done in wrong device.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5932
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Rudolf Marek [Sun, 10 Oct 2010 19:54:15 +0000 (19:54 +0000)]
Following patch enables UDMA on ALL IDE devices. The current code enables it only for primary master, which causes my DVD drive to fail under windows install
and even after hard reset in linux (DMA seems lockup).
The fix should not have any influence for Linux because the IDE driver will
correctly reprogram this bit.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5931
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Zheng Bao [Sun, 10 Oct 2010 15:18:53 +0000 (15:18 +0000)]
Trivial. Spelling check.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5930
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Uwe Hermann [Sat, 9 Oct 2010 17:00:18 +0000 (17:00 +0000)]
Remove various .c #includes from Intel 440BX/
82371EB boards.
- Use 'romstage-y' to turn i82371eb_early_pm.c and i82371eb_early_smbus.c
into distinct compilation units, and don't #include the files anymore
in romstage.c files.
- Ditto for lib/debug.c, northbridge/intel/i440bx/raminit.c, and
northbridge/intel/i440bx/debug.c.
- Add various header files which are now needed.
- Make functions that need to be visible non-static.
- Drop a remaining "select ROMCC" from a 4440BX board.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Idwer Vollering <vidwer@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5929
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Zheng Bao [Sat, 9 Oct 2010 07:18:50 +0000 (07:18 +0000)]
Trivial. Spell checking.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5928
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Zheng Bao [Sat, 9 Oct 2010 02:31:10 +0000 (02:31 +0000)]
Trivial. Spell checking.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5927
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Uwe Hermann [Fri, 8 Oct 2010 20:09:21 +0000 (20:09 +0000)]
Drop unused i82801ax_early_lpc.c and i82801bx_early_lpc.c.
Nothing ever calls the functions in these files, and we already have
i82801ax_watchdog.c and i82801bx_watchdog.c which basically do the same
_and_ are hooked up correctly in the Makefile.inc and via the
USE_WATCHDOG_ON_BOOT mechanism.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5926
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Uwe Hermann [Fri, 8 Oct 2010 19:24:56 +0000 (19:24 +0000)]
Round 2 of i82801AX fixes to get it into a usable shape.
- Remove left-overs from more generic code in i82801xx times, and fix
register names as needed.
- Simplify IDE init code (and save some ROM space too).
- Simplify PIRQ code.
- Use u8 et al instead of uint8_t everywhere.
- Random other fixes.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5925
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Uwe Hermann [Fri, 8 Oct 2010 16:40:23 +0000 (16:40 +0000)]
Intel 82801ax/82801bx: Fix and hook up i82801xx_smbus.c.
- Fix incorrect #includes, add missing ones.
- Drop unused do_smbus_write_block() and smbus_wait_until_blk_done().
- Pass smbus_io_base to all functions as the other ICH implementations do.
- Random other fixes which are required to make it build.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5924
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Zheng Bao [Fri, 8 Oct 2010 05:08:47 +0000 (05:08 +0000)]
Trivial. Spell checking.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5923
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Zheng Bao [Fri, 8 Oct 2010 03:35:12 +0000 (03:35 +0000)]
Trivial. Fix the typo.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5922
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Uwe Hermann [Thu, 7 Oct 2010 23:42:17 +0000 (23:42 +0000)]
Remove some duplicate #include files (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5921
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jonathan Kollasch [Thu, 7 Oct 2010 23:02:06 +0000 (23:02 +0000)]
Remove duplicate line from pci_ids.h.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5920
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Scott Duplichan [Thu, 7 Oct 2010 18:25:04 +0000 (18:25 +0000)]
RS780 function ProgK8TempMmioBase is setting a reserved
bit in the AMD processor 'MMIO Limit Address Register'.
I suspect it is because of a typo where 0x80 was entered
as 0x8. If 0x80 is used, then the strap configuration
register accesses become non-posted, which is how the
Shiner reference BIOS does it.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5919
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Uwe Hermann [Thu, 7 Oct 2010 16:24:28 +0000 (16:24 +0000)]
Convert all Intel
82371AB/EB/MB based boards to TINY_BOOTBLOCK.
Also:
Unfortunately Intel 440BX +
82371AB/EB/MB boards can have their ISA device
on various PCI bus:device.function locations.
Examples we encountered: 00:07.0, 00:04.0, or 00:14.0.
Thus, instead of hardcoding PCI bus:device.function numbers such as
PCI_DEV(0, 7, 0), we now simply find the ISA device via PCI IDs, which
works the same on all boards.
As an additional benefit this patch also gets rid of one .c file include
in romstage.c.
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5918
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Uwe Hermann [Wed, 6 Oct 2010 19:32:39 +0000 (19:32 +0000)]
Convert all Intel 440BX boards to Cache-as-RAM (CAR).
- Add "select CACHE_AS_RAM" in src/cpu/intel/slot_1/Kconfig.
- Add the following in src/cpu/intel/slot_1/Makefile.inc:
cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc
- Remove "select ROMCC" from all 440BX board Kconfig files.
- Drop all early_mtrr_init() calls, that's done by CAR code now.
Various small fixes were needed to make it build:
- Drop do_smbus_recv_byte(), do_smbus_send_byte(), do_smbus_write_byte(),
those were never called anyways.
- Remove the "static" from the main() functions in romstage.c files.
- Always call dump_spd_registers() from the 440BX debug.c, but use
"#if CONFIG_DEBUG_RAM_SETUP" to only have that code if RAM debugging
is enabled in menuconfig.
- Drop all "lib/ramtest.c" #includes and ram_check() calls (even if
commented out) from romstage.c's, as we've done for most other boards.
- Add missing #includes or prototypes. Some of the prototypes will be
removed later when we get rid of the #include'd .c files.
Abuild-tested for all boards, and boot-tested on A-Trend ATC-6220.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5917
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
Jonathan Kollasch [Tue, 5 Oct 2010 19:39:35 +0000 (19:39 +0000)]
Remove duplicate line from pci_ids.h.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5916
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1