Convert ck804_early_smbus.c to a separately compiled unit.

Additionally, make the second SMBus more accessible in romstage.

Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5994 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c
index 6cddfd21a3318518208540c64a0eb31861d334ab..424da45738618fe3101c3ccacef683882f46e2dc 100644 (file)
--- a/src/mainboard/asus/a8n_e/romstage.c
+++ b/src/mainboard/asus/a8n_e/romstage.c
@@ -45,7 +45,7 @@
 #include <cpu/amd/model_fxx_rev.h>
 #include <console/console.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
+#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"

diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c
index 82195d59b3ebd4a28dff45b76893d6f23ceec577..0d3dbd5c8b6b7e4b98c73ca77fb42f86f0e0cf75 100644 (file)
--- a/src/mainboard/msi/ms7135/romstage.c
+++ b/src/mainboard/msi/ms7135/romstage.c
@@ -46,7 +46,7 @@
 #include <cpu/amd/model_fxx_rev.h>
 #include <console/console.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
+#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"

diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c
index b45b8322454655b36bd240635b4a03e70150c35c..edbaaed4755c932ffff61f242250056d10136e4b 100644 (file)
--- a/src/mainboard/sunw/ultra40/romstage.c
+++ b/src/mainboard/sunw/ultra40/romstage.c
@@ -20,7 +20,7 @@
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
+#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"

diff --git a/src/mainboard/tyan/s2891/romstage.c b/src/mainboard/tyan/s2891/romstage.c
index 494b71d33ad8b34fcce3a5dcd86e1b4a19b6f3ba..cd63d0f704e1d0e86cb57a06b8531fdb8cefe11b 100644 (file)
--- a/src/mainboard/tyan/s2891/romstage.c
+++ b/src/mainboard/tyan/s2891/romstage.c
@@ -19,7 +19,7 @@
 #include <cpu/amd/model_fxx_rev.h>
 
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
+#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"

diff --git a/src/mainboard/tyan/s2892/romstage.c b/src/mainboard/tyan/s2892/romstage.c
index b15fda2cc65af015fde72edf422657b1646b101f..ea023b5ed449986199725acfab7b76734fc8c84b 100644 (file)
--- a/src/mainboard/tyan/s2892/romstage.c
+++ b/src/mainboard/tyan/s2892/romstage.c
@@ -19,7 +19,7 @@
 #include <cpu/amd/model_fxx_rev.h>
 
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
+#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"

diff --git a/src/mainboard/tyan/s2895/romstage.c b/src/mainboard/tyan/s2895/romstage.c
index 4b6cd0ac496cd72abab95b26e90289ec16c97b09..00836ac2e0df9676e1093ea2a63459d6a3d81229 100644 (file)
--- a/src/mainboard/tyan/s2895/romstage.c
+++ b/src/mainboard/tyan/s2895/romstage.c
@@ -18,7 +18,7 @@
 #include <lib.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
+#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"

diff --git a/src/southbridge/nvidia/ck804/Makefile.inc b/src/southbridge/nvidia/ck804/Makefile.inc
index 48f7713a8b3870573d579c5c12850d3518c5bf21..09b20708af43f1c2912ab3f8292936ff252a2a46 100644 (file)
--- a/src/southbridge/nvidia/ck804/Makefile.inc
+++ b/src/southbridge/nvidia/ck804/Makefile.inc
@@ -16,6 +16,7 @@ ramstage-y += ck804_reset.c
 ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += ck804_fadt.c
 
 romstage-y += ck804_enable_usbdebug.c
+romstage-y += ck804_early_smbus.c
 
 chipset_bootblock_inc += $(src)/southbridge/nvidia/ck804/romstrap.inc
 chipset_bootblock_lds += $(src)/southbridge/nvidia/ck804/romstrap.lds

diff --git a/src/southbridge/nvidia/ck804/ck804_early_smbus.c b/src/southbridge/nvidia/ck804/ck804_early_smbus.c
index 6f88c327b09de9d3228422128075ff6385d49237..05dcd9801479994308bff9479faeb842e0acb90b 100644 (file)
--- a/src/southbridge/nvidia/ck804/ck804_early_smbus.c
+++ b/src/southbridge/nvidia/ck804/ck804_early_smbus.c
@@ -18,36 +18,63 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+
 #include "ck804_smbus.h"
+#include "ck804_early_smbus.h"
 
+#define SMBUS_BAR_BASE 0x20
 #define SMBUS_IO_BASE 0x1000
+#define SMBUS_IO_SIZE 0x0040
+
+#define SMBUS_BAR(x) (SMBUS_BAR_BASE + 4 * (x))
+#define SMBUS_BASE(x) (SMBUS_IO_BASE + SMBUS_IO_SIZE * (x))
 
-static void enable_smbus(void)
+void enable_smbus(void)
 {
        device_t dev;
-       dev = pci_locate_device(PCI_ID(0x10de, 0x0052), 0);
+
+       dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_NVIDIA,
+                               PCI_DEVICE_ID_NVIDIA_CK804_SMB), 0);
        if (dev == PCI_DEV_INVALID)
                die("SMBus controller not found\n");
 
-       print_debug("SMBus controller enabled\n");
-
        /* Set SMBus I/O base. */
-       pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
+       pci_write_config32(dev, SMBUS_BAR(0), SMBUS_BASE(0) | 1);
+       pci_write_config32(dev, SMBUS_BAR(1), SMBUS_BASE(1) | 1);
 
        /* Set SMBus I/O space enable. */
        pci_write_config16(dev, 0x4, 0x01);
 
        /* Clear any lingering errors, so the transaction will run. */
-       outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
+       outb(inb(SMBUS_BASE(0) + SMBHSTSTAT), SMBUS_BASE(0) + SMBHSTSTAT);
+       outb(inb(SMBUS_BASE(1) + SMBHSTSTAT), SMBUS_BASE(1) + SMBHSTSTAT);
+
+       print_debug("SMBus controller enabled\n");
 }
 
-static int smbus_read_byte(unsigned device, unsigned address)
+int ck804_smbus_read_byte(unsigned bus, unsigned device, unsigned address)
 {
-       return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
+       return do_smbus_read_byte(SMBUS_BASE(bus), device, address);
 }
 
-static inline int smbus_write_byte(unsigned device, unsigned address,
+int ck804_smbus_write_byte(unsigned bus, unsigned device, unsigned address,
                            unsigned char val)
 {
-       return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
+       return do_smbus_write_byte(SMBUS_BASE(bus), device, address, val);
+}
+
+int smbus_read_byte(unsigned device, unsigned address)
+{
+       return ck804_smbus_read_byte(0, device, address);
+}
+
+int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
+{
+       return ck804_smbus_write_byte(0, device, address, val);
 }

diff --git a/src/southbridge/nvidia/ck804/ck804_early_smbus.h b/src/southbridge/nvidia/ck804/ck804_early_smbus.h
new file mode 100644 (file)
index 0000000..cf25403
--- /dev/null
+++ b/src/southbridge/nvidia/ck804/ck804_early_smbus.h
@@ -0,0 +1,5 @@
+int ck804_smbus_read_byte(unsigned int, unsigned int, unsigned);
+int ck804_smbus_write_byte(unsigned int, unsigned int, unsigned int, unsigned char);
+void enable_smbus(void);
+int smbus_read_byte(unsigned int, unsigned int);
+int smbus_write_byte(unsigned int, unsigned int, unsigned char);