Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets.

This CAR implementation hardcodes the Cache-as-RAM base address to:

  0xd0000 - CacheSize

so the DCACHE_RAM_BASE is never actually used for this implementation
and these sockets.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5953 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig
index d10de589e78b897a0154d17ced99eb3105f656c7..45c94ac6f0ca3946933de73ae972fce76852f643 100644 (file)
--- a/src/cpu/intel/slot_1/Kconfig
+++ b/src/cpu/intel/slot_1/Kconfig
@@ -21,11 +21,6 @@ config CPU_INTEL_SLOT_1
        bool
        select CACHE_AS_RAM
 
-config DCACHE_RAM_BASE
-       hex
-       default 0xc0000
-       depends on CPU_INTEL_SLOT_1
-
 config DCACHE_RAM_SIZE
        hex
        default 0x01000

diff --git a/src/cpu/intel/slot_2/Kconfig b/src/cpu/intel/slot_2/Kconfig
index 49f3cb1d533ae01ccca0fdc03d60a9c93f40fcaf..2862431f0414acf8b372c8604df5d4ad470a819f 100644 (file)
--- a/src/cpu/intel/slot_2/Kconfig
+++ b/src/cpu/intel/slot_2/Kconfig
@@ -20,11 +20,6 @@
 config CPU_INTEL_SLOT_2
        bool
 
-config DCACHE_RAM_BASE
-       hex
-       default 0xc0000
-       depends on CPU_INTEL_SLOT_2
-
 config DCACHE_RAM_SIZE
        hex
        default 0x01000

diff --git a/src/cpu/intel/socket_FC_PGA370/Kconfig b/src/cpu/intel/socket_FC_PGA370/Kconfig
index f3987783a889605cf5471f284306a82f5296605b..88541a8379aa9ddd9599e8a6c8dcfc28a671d6c3 100644 (file)
--- a/src/cpu/intel/socket_FC_PGA370/Kconfig
+++ b/src/cpu/intel/socket_FC_PGA370/Kconfig
@@ -26,11 +26,6 @@ config CPU_INTEL_SOCKET_FC_PGA370
        select CACHE_AS_RAM
        select TINY_BOOTBLOCK
 
-config DCACHE_RAM_BASE
-       hex
-       default 0xffdf8000
-       depends on CPU_INTEL_SOCKET_FC_PGA370
-
 config DCACHE_RAM_SIZE
        hex
        default 0x8000

diff --git a/src/cpu/intel/socket_PGA370/Kconfig b/src/cpu/intel/socket_PGA370/Kconfig
index bfabfb847172502b1eebd1adbc6d7594c08f6e6a..adfb5f3a7310f64b472f6669ab225edc26085ce1 100644 (file)
--- a/src/cpu/intel/socket_PGA370/Kconfig
+++ b/src/cpu/intel/socket_PGA370/Kconfig
@@ -30,10 +30,6 @@ config SSE2
        bool
        default n
 
-config DCACHE_RAM_BASE
-       hex
-       default 0xc0000
-
 config DCACHE_RAM_SIZE
        hex
        default 0x01000