#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
-#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c"
+#include "southbridge/intel/i82801ax/i82801ax.h"
#include "northbridge/intel/i82810/raminit.h"
-#include "lib/debug.c"
#include "pc80/udelay_io.c"
-#include "lib/delay.c"
#include "cpu/x86/bist.h"
#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
-#include "northbridge/intel/i82810/raminit.c"
-/* #include "northbridge/intel/i82810/debug.c" */
#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
void main(unsigned long bist)
{
smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
report_bist_failure(bist);
enable_smbus();
- /* dump_spd_registers(); */
+ dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
#include "superio/smsc/lpc47b272/lpc47b272_early_serial.c"
#include "northbridge/intel/i82810/raminit.h"
#include "cpu/x86/bist.h"
-#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c"
-#include "lib/debug.c"
+#include "southbridge/intel/i82801ax/i82801ax.h"
#include "pc80/udelay_io.c"
-#include "lib/delay.c"
-#include "northbridge/intel/i82810/raminit.c"
-#include "northbridge/intel/i82810/debug.c"
#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
void main(unsigned long bist)
{
lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
-#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c"
+#include "southbridge/intel/i82801ax/i82801ax.h"
#include "northbridge/intel/i82810/raminit.h"
-#include "lib/debug.c"
#include "pc80/udelay_io.c"
-#include "lib/delay.c"
#include "cpu/x86/bist.h"
#include "superio/ite/it8712f/it8712f_early_serial.c"
-#include "northbridge/intel/i82810/raminit.c"
-#include "northbridge/intel/i82810/debug.c"
#include <lib.h>
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
void main(unsigned long bist)
{
it8712f_24mhz_clkin();
/* TODO: It's i810E actually! */
#include "northbridge/intel/i82810/raminit.h"
#include "cpu/x86/bist.h"
-#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c"
+#include "southbridge/intel/i82801ax/i82801ax.h"
#include "pc80/udelay_io.c"
-#include "lib/debug.c"
-#include "northbridge/intel/i82810/raminit.c"
#include <lib.h>
/* TODO: It's a PC87364 actually! */
#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
void main(unsigned long bist)
{
/* TODO: It's a PC87364 actually! */
console_init();
enable_smbus();
report_bist_failure(bist);
- /* dump_spd_registers(); */
+ dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
#include "southbridge/intel/i82801bx/i82801bx.h"
-#include "southbridge/intel/i82801bx/i82801bx_early_smbus.c"
#include "northbridge/intel/i82810/raminit.h"
-#include "lib/debug.c"
#include "pc80/udelay_io.c"
-#include "lib/delay.c"
#include "cpu/x86/bist.h"
#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
#include "gpio.c"
-#include "northbridge/intel/i82810/raminit.c"
-/* #include "northbridge/intel/i82810/debug.c" */
#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
void main(unsigned long bist)
{
/* Set southbridge and Super I/O GPIOs. */
report_bist_failure(bist);
enable_smbus();
- /* dump_spd_registers(); */
+ dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <console/console.h>
-#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c"
+#include "southbridge/intel/i82801ax/i82801ax.h"
#include "northbridge/intel/i82810/raminit.h"
-#include "lib/debug.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
#include "cpu/x86/bist.h"
#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
-#include "northbridge/intel/i82810/raminit.c"
-/* #include "northbridge/intel/i82810/debug.c" */
#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
void main(unsigned long bist)
{
smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
report_bist_failure(bist);
enable_smbus();
- /* dump_spd_registers(); */
+ dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "northbridge/intel/i82810/raminit.h"
#include "cpu/x86/bist.h"
-#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c"
+#include "southbridge/intel/i82801ax/i82801ax.h"
#include "pc80/udelay_io.c"
-#include "lib/debug.c"
-#include "northbridge/intel/i82810/raminit.c"
#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
void main(unsigned long bist)
{
/* FIXME */
uart_init();
console_init();
-
enable_smbus();
-
report_bist_failure(bist);
-
- /* dump_spd_registers(); */
+ dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
#include "northbridge/intel/i82810/raminit.h"
#include "cpu/x86/bist.h"
-#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c"
+#include "southbridge/intel/i82801ax/i82801ax.h"
#include "pc80/udelay_io.c"
-#include "northbridge/intel/i82810/raminit.c"
#include <lib.h>
#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
+void enable_smbus(void);
+int smbus_read_byte(u8 device, u8 address);
+
void main(unsigned long bist)
{
smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
enable_smbus();
report_bist_failure(bist);
- /* dump_spd_registers(); */
+ dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
driver-y += northbridge.c
+romstage-y += raminit.c
+romstage-y += debug.c
+
-static void dump_spd_registers(void)
+#include "raminit.h"
+
+void dump_spd_registers(void)
{
#if CONFIG_DEBUG_RAM_SETUP
int i;
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#ifndef NORTHBRIDGE_INTEL_I82810_I82810_H
+#define NORTHBRIDGE_INTEL_I82810_I82810_H
+
/*
* Datasheet:
* - Name: Intel 810 Chipset:
#define MISSC 0x72 /* Miscellaneous Control */
#define MISSC2 0x80 /* Miscellaneous Control 2 */
#define BUFF_SC 0x92 /* System Memory Buffer Strength Control */
+
+int smbus_read_byte(u8 device, u8 address);
+
+#endif
#include <spd.h>
#include <delay.h>
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <console/console.h>
#include "i82810.h"
+#include "raminit.h"
/*-----------------------------------------------------------------------------
Macros and definitions.
Public interface.
-----------------------------------------------------------------------------*/
-static void sdram_set_registers(void)
+void sdram_set_registers(void)
{
u8 reg8;
u16 did;
pci_write_config8(PCI_DEV(0, 0, 0), MISSC2, reg8);
}
-static void sdram_set_spd_registers(void)
+void sdram_set_spd_registers(void)
{
spd_set_dram_size();
set_dram_buffer_strength();
/**
* Enable SDRAM.
*/
-static void sdram_enable(void)
+void sdram_enable(void)
{
int i;
/* DIMM0 is at 0x50, DIMM1 is at 0x51. */
#define DIMM_SPD_BASE 0x50
-#endif /* NORTHBRIDGE_INTEL_I82810_RAMINIT_H */
+/* Function prototypes. */
+void sdram_set_registers(void);
+void sdram_set_spd_registers(void);
+void sdram_enable(void);
+void dump_spd_registers(void);
+
+#endif
ramstage-y += i82801ax_reset.c
ramstage-y += i82801ax_watchdog.c
+romstage-y += i82801ax_early_smbus.c
+
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
#include <device/pci_ids.h>
+#include <device/pci_def.h>
#include "i82801ax.h"
#include "i82801ax_smbus.h"
-static void enable_smbus(void)
+int smbus_read_byte(u8 device, u8 address);
+
+void enable_smbus(void)
{
device_t dev;
print_debug("SMBus controller enabled\n");
}
-static inline int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(u8 device, u8 address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include <device/smbus_def.h>
+void enable_smbus(void);
+int do_smbus_read_byte(u16 smbus_io_base, u8 device, u8 address);
+
static void smbus_delay(void)
{
inb(0x80);
return loops ? 0 : -1;
}
-static int do_smbus_read_byte(u16 smbus_io_base, unsigned device,
- unsigned address)
+int do_smbus_read_byte(u16 smbus_io_base, u8 device, u8 address)
{
unsigned char global_status_register;
unsigned char byte;
ramstage-y += i82801bx_reset.c
ramstage-y += i82801bx_watchdog.c
+romstage-y += i82801bx_early_smbus.c
+
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
#include <device/pci_ids.h>
+#include <device/pci_def.h>
#include "i82801bx.h"
#include "i82801bx_smbus.h"
-static void enable_smbus(void)
+int smbus_read_byte(u8 device, u8 address);
+
+void enable_smbus(void)
{
device_t dev;
print_debug("SMBus controller enabled\n");
}
-static inline int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(u8 device, u8 address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
#include <device/smbus_def.h>
+void enable_smbus(void);
+
static void smbus_delay(void)
{
inb(0x80);
return loops ? 0 : -1;
}
-static int do_smbus_read_byte(u16 smbus_io_base, unsigned device,
- unsigned address)
+static int do_smbus_read_byte(u16 smbus_io_base, u8 device, u8 address)
{
unsigned char global_status_register;
unsigned char byte;