Drop unused i82801ax_early_lpc.c and i82801bx_early_lpc.c.

Nothing ever calls the functions in these files, and we already have
i82801ax_watchdog.c and i82801bx_watchdog.c which basically do the same
_and_ are hooked up correctly in the Makefile.inc and via the
USE_WATCHDOG_ON_BOOT mechanism.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5926 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/southbridge/intel/i82801ax/i82801ax_early_lpc.c b/src/southbridge/intel/i82801ax/i82801ax_early_lpc.c
deleted file mode 100644 (file)
index abcf9c6..0000000
--- a/src/southbridge/intel/i82801ax/i82801ax_early_lpc.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- *
- */
-
-static void i82801ax_halt_tco_timer(void)
-{
-       device_t dev;
-       uint16_t halt_tco_timer;
-
-       /* Set the LPC device statically. */
-       dev = PCI_DEV(0x0, 0x1f, 0x0);
-
-       /* Temporarily set ACPI base address (I/O space). */
-       pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
-
-       /* Temporarily enable ACPI I/O. */
-       pci_write_config8(dev, ACPI_CNTL, 0x10);
-
-       /* Halt the TCO timer, preventing SMI and automatic reboot */
-       outw(inw(PMBASE_ADDR + TCOBASE + TCO1_CNT) | (1 << 11), PMBASE_ADDR + TCOBASE + TCO1_CNT);
-
-       /* Disable ACPI I/O. */
-       pci_write_config8(dev, ACPI_CNTL, 0x00);
-}

diff --git a/src/southbridge/intel/i82801bx/i82801bx_early_lpc.c b/src/southbridge/intel/i82801bx/i82801bx_early_lpc.c
deleted file mode 100644 (file)
index b64c3d8..0000000
--- a/src/southbridge/intel/i82801bx/i82801bx_early_lpc.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- *
- */
-
-static void i82801bx_halt_tco_timer(void)
-{
-       device_t dev;
-       uint16_t halt_tco_timer;
-
-       /* Set the LPC device statically. */
-       dev = PCI_DEV(0x0, 0x1f, 0x0);
-
-       /* Temporarily set ACPI base address (I/O space). */
-       pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
-
-       /* Temporarily enable ACPI I/O. */
-       pci_write_config8(dev, ACPI_CNTL, 0x10);
-
-       /* Halt the TCO timer, preventing SMI and automatic reboot */
-       outw(inw(PMBASE_ADDR + TCOBASE + TCO1_CNT) | (1 << 11), PMBASE_ADDR + TCOBASE + TCO1_CNT);
-
-       /* Disable ACPI I/O. */
-       pci_write_config8(dev, ACPI_CNTL, 0x00);
-}