config SOUTHBRIDGE_INTEL_I82801BX
bool
select HAVE_HARD_RESET
+ select USE_WATCHDOG_ON_BOOT
driver-y += i82801bx_lpc.c
driver-y += i82801bx_nic.c
driver-y += i82801bx_pci.c
-driver-y += i82801bx_sata.c
driver-y += i82801bx_smbus.c
driver-y += i82801bx_usb.c
-driver-y += i82801bx_usb_ehci.c
ramstage-y += i82801bx_reset.c
ramstage-y += i82801bx_watchdog.c
*/
/*
- * The i82801bx code currently supports:
- * - 82801AA
- * - 82801AB
- * - 82801BA
- * - 82801CA
- * - 82801DB
- * - 82801DBM
- * - 82801EB
- * - 82801ER
- *
- * This code should NOT be used for ICH6 and later versions.
+ * The i82801bx code supports: 82801BA/82801BAM (ICH2/ICH2-M)
*/
#ifndef SOUTHBRIDGE_INTEL_I82801BX_CHIP_H
#define SOUTHBRIDGE_INTEL_I82801BX_CHIP_H
+#include <stdint.h>
+
struct southbridge_intel_i82801bx_config {
- /**
- * Interrupt Routing configuration
- * If bit7 is 1, the interrupt is disabled.
- */
- uint8_t pirqa_routing;
- uint8_t pirqb_routing;
- uint8_t pirqc_routing;
- uint8_t pirqd_routing;
- uint8_t pirqe_routing;
- uint8_t pirqf_routing;
- uint8_t pirqg_routing;
- uint8_t pirqh_routing;
+ u8 pirqa_routing;
+ u8 pirqb_routing;
+ u8 pirqc_routing;
+ u8 pirqd_routing;
+ u8 pirqe_routing;
+ u8 pirqf_routing;
+ u8 pirqg_routing;
+ u8 pirqh_routing;
- uint8_t ide0_enable;
- uint8_t ide1_enable;
+ u8 ide0_enable;
+ u8 ide1_enable;
};
extern struct chip_operations southbridge_intel_i82801bx_ops;
void i82801bx_enable(device_t dev)
{
- unsigned int index = 0;
- uint16_t cur_disable_mask, new_disable_mask;
+ u16 reg16, index;
+ device_t lpc_dev;
- /* All 82801xx devices should be on bus 0. */
- unsigned int devfn = PCI_DEVFN(0x1f, 0); // LPC
- device_t lpc_dev = dev_find_slot(0, devfn); // 0
+ /* Search for the 82801BA/BAM LPC device (D31:F0) on PCI bus 0. */
+ lpc_dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
if (!lpc_dev)
return;
- /* We're going to assume, perhaps incorrectly, that if a function
- * exists it can be disabled. Workarounds for ICH variants that don't
- * follow this should be done by checking the device ID.
- */
- if (PCI_SLOT(dev->path.pci.devfn) == 31) {
- index = PCI_FUNC(dev->path.pci.devfn);
- } else if (PCI_SLOT(dev->path.pci.devfn) == 29) {
- index = 8 + PCI_FUNC(dev->path.pci.devfn);
- }
+ index = PCI_FUNC(dev->path.pci.devfn);
- /* Function 0 is a bit of an exception. */
- if (index == 0) {
- index = 14;
- }
-
- cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS);
- new_disable_mask = cur_disable_mask & ~(1 << index); /* Enable it. */
- if (!dev->enabled) {
- new_disable_mask |= (1 << index); /* Disable it, if desired. */
- }
- if (new_disable_mask != cur_disable_mask) {
- pci_write_config16(lpc_dev, FUNC_DIS, new_disable_mask);
- }
+ reg16 = pci_read_config16(lpc_dev, FUNC_DIS);
+ reg16 &= ~(1 << index); /* Enable device. */
+ if (!dev->enabled)
+ reg16 |= (1 << index); /* Disable device, if desired. */
+ pci_write_config16(lpc_dev, FUNC_DIS, reg16);
}
struct chip_operations southbridge_intel_i82801bx_ops = {
extern void i82801bx_enable(device_t dev);
#endif
+#define SMBUS_IO_BASE 0x0f00
+#define PMBASE_ADDR 0x0400
+#define GPIO_BASE_ADDR 0x0500
+#define HPET_ADDR 0xfed00000
+
+#define SECSTS 0x1e
+
#define PCI_DMA_CFG 0x90
#define SERIRQ_CNTL 0x64
#define GEN_CNTL 0xd0
#define GEN_PMCON_3 0xa4
#define PMBASE 0x40
-#define PMBASE_ADDR 0x0400 /* ACPI Base Address Register */
#define ACPI_CNTL 0x44
+#define ACPI_EN (1 << 4)
#define BIOS_CNTL 0x4E
-#define GPIO_BASE 0x58 /* LPC GPIO Base Address Register */
-#define GPIO_CNTL 0x5C /* LPC GPIO Control Register */
+#define GPIO_BASE 0x58 /* GPIO Base Address Register */
+#define GPIO_CNTL 0x5C /* GPIO Control Register */
+#define GPIO_EN (1 << 4)
#define PIRQA_ROUT 0x60
#define PIRQB_ROUT 0x61
#define FUNC_DIS 0xF2
-#define COM_DEC 0xE0 /* LPC I/F Communication Port Decode Ranges (ICH0-ICH5) */
-#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register (ICH6-ICH9) */
-#define LPC_EN_ICH0_5 0xE6 /* LPC IF Enables Register (ICH0-ICH5) */
-#define LPC_EN_ICH6_9 0x82 /* LPC IF Enables Register (ICH6-ICH9) */
+#define COM_DEC 0xE0 /* LPC I/F Comm. Port Decode Ranges */
+#define LPC_EN 0xE6 /* LPC IF Enables Register */
+
+// TODO: FDC_DEC etc
#define SBUS_NUM 0x19
#define SUB_BUS_NUM 0x1A
#define MTT 0x70
#define PCI_MAST_STS 0x82
-#define GPIO_BASE_ADDR 0x00000500 /* GPIO Base Address Register */
-
#define TCOBASE 0x60 /* TCO Base Address Register */
#define TCO1_CNT 0x08 /* TCO1 Control Register */
#define RTC_POWER_FAILED (1 << 1)
#define SLEEP_AFTER_POWER_FAIL (1 << 0)
-/* PCI Configuration Space (D31:F1) */
+/* IDE Timing registers (IDE_TIM) */
#define IDE_TIM_PRI 0x40 /* IDE timings, primary */
#define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
/* IDE_TIM bits */
#define IDE_DECODE_ENABLE (1 << 15)
-/* PCI Configuration Space (D31:F3) */
+/* SMbus */
#define SMB_BASE 0x20
#define HOSTC 0x40
#define SMB_SMI_EN (1 << 1)
#define HST_EN (1 << 0)
-/* SMBus I/O bits.
- * TODO: Does it matter where we put the SMBus IO base, as long as we keep
- * consistent and don't interfere with anything else?
- */
-/* #define SMBUS_IO_BASE 0x1000 */
-#define SMBUS_IO_BASE 0x0f00
-
+/* SMBus I/O registers. */
#define SMBHSTSTAT 0x0
#define SMBHSTCTL 0x2
#define SMBHSTCMD 0x3
#define SMBUS_TIMEOUT (10 * 1000 * 100)
-/* HPET, if present */
-#define HPET_ADDR 0xfed00000
-
#endif /* SOUTHBRIDGE_INTEL_I82801BX_I82801BX_H */
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-/* This code should work for all ICH* southbridges with AC97 audio/modem. */
-
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
.enable = i82801bx_enable,
};
-/* 82801AA (ICH) */
-static const struct pci_driver i82801aa_ac97_audio __pci_driver = {
- .ops = &ac97_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801AA_AC97_AUDIO,
-};
-
-static const struct pci_driver i82801aa_ac97_modem __pci_driver = {
- .ops = &ac97_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801AA_AC97_MODEM,
-};
-
-/* 82801AB (ICH0) */
-static const struct pci_driver i82801ab_ac97_audio __pci_driver = {
- .ops = &ac97_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801AB_AC97_AUDIO,
-};
-
-static const struct pci_driver i82801ab_ac97_modem __pci_driver = {
- .ops = &ac97_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801AB_AC97_MODEM,
-};
-
/* 82801BA/BAM (ICH2/ICH2-M) */
static const struct pci_driver i82801ba_ac97_audio __pci_driver = {
.ops = &ac97_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_82801BA_AC97_MODEM,
};
-
-/* 82801CA/CAM (ICH3-S/ICH3-M) */
-static const struct pci_driver i82801ca_ac97_audio __pci_driver = {
- .ops = &ac97_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801CA_AC97_AUDIO,
-};
-
-static const struct pci_driver i82801ca_ac97_modem __pci_driver = {
- .ops = &ac97_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801CA_AC97_MODEM,
-};
-
-/* 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) */
-static const struct pci_driver i82801db_ac97_audio __pci_driver = {
- .ops = &ac97_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801DB_AC97_AUDIO,
-};
-
-static const struct pci_driver i82801db_ac97_modem __pci_driver = {
- .ops = &ac97_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801DB_AC97_MODEM,
-};
-
-/* 82801EB/ER (ICH5/ICH5R) */
-static const struct pci_driver i82801eb_ac97_audio __pci_driver = {
- .ops = &ac97_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801EB_AC97_AUDIO,
-};
-
-static const struct pci_driver i82801eb_ac97_modem __pci_driver = {
- .ops = &ac97_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801EB_AC97_MODEM,
-};
-
-/* 82801FB/FR/FW/FRW/FBM (ICH6/ICH6R/ICH6W/ICH6RW/ICH6-M) */
-static const struct pci_driver i82801fb_ac97_audio __pci_driver = {
- .ops = &ac97_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801FB_AC97_AUDIO,
-};
-
-static const struct pci_driver i82801fb_ac97_modem __pci_driver = {
- .ops = &ac97_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801FB_AC97_MODEM,
-};
device_t dev;
uint16_t device_id;
- /* Set the SMBus device statically. */
+ /* Set the SMBus device statically (D31:F3). */
dev = PCI_DEV(0x0, 0x1f, 0x3);
- /* Check to make sure we've got the right device. */
- device_id = pci_read_config16(dev, 0x2);
-
- /* Clear bits 7-4 (the only bits that vary between models). */
- device_id &= 0xff0f;
-
- if (device_id != 0x2403) {
- die("Device not found, Corey probably screwed up!");
- }
-
/* Set SMBus I/O base. */
pci_write_config32(dev, SMB_BASE,
SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
static void ide_init(struct device *dev)
{
- /* Get the chip configuration */
- config_t *config = dev->chip_info;
+ u16 reg16;
+ config_t *conf = dev->chip_info;
- /* TODO: Needs to be tested for compatibility with ICH5(R). */
- /* Enable IDE devices so the Linux IDE driver will work. */
- uint16_t ideTimingConfig;
+ reg16 = pci_read_config16(dev, IDE_TIM_PRI);
+ reg16 &= ~IDE_DECODE_ENABLE;
+ if (!conf || conf->ide0_enable)
+ reg16 |= IDE_DECODE_ENABLE;
+ printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Primary",
+ conf->ide0_enable ? "on" : "off");
+ pci_write_config16(dev, IDE_TIM_PRI, reg16);
- ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI);
- ideTimingConfig &= ~IDE_DECODE_ENABLE;
- if (!config || config->ide0_enable) {
- /* Enable primary IDE interface. */
- ideTimingConfig |= IDE_DECODE_ENABLE;
- printk(BIOS_DEBUG, "IDE0: Primary IDE interface is enabled\n");
- } else {
- printk(BIOS_INFO, "IDE0: Primary IDE interface is disabled\n");
- }
- pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig);
-
- ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC);
- ideTimingConfig &= ~IDE_DECODE_ENABLE;
- if (!config || config->ide1_enable) {
- /* Enable secondary IDE interface. */
- ideTimingConfig |= IDE_DECODE_ENABLE;
- printk(BIOS_DEBUG, "IDE1: Secondary IDE interface is enabled\n");
- } else {
- printk(BIOS_INFO, "IDE1: Secondary IDE interface is disabled\n");
- }
- pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig);
+ reg16 = pci_read_config16(dev, IDE_TIM_SEC);
+ reg16 &= ~IDE_DECODE_ENABLE;
+ if (!conf || conf->ide1_enable)
+ reg16 |= IDE_DECODE_ENABLE;
+ printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Secondary",
+ conf->ide0_enable ? "on" : "off");
+ pci_write_config16(dev, IDE_TIM_SEC, reg16);
}
static struct device_operations ide_ops = {
.enable = i82801bx_enable,
};
-/* 82801AA */
-static const struct pci_driver i82801aa_ide __pci_driver = {
- .ops = &ide_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x2411,
-};
-
-/* 82801AB */
-static const struct pci_driver i82801ab_ide __pci_driver = {
- .ops = &ide_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x2421,
-};
-
-/* 82801BA */
+/* 82801BA/BAM (ICH2/ICH2-M) */
static const struct pci_driver i82801ba_ide __pci_driver = {
.ops = &ide_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x244b,
};
-
-/* 82801CA */
-static const struct pci_driver i82801ca_ide __pci_driver = {
- .ops = &ide_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x248b,
-};
-
-/* 82801DB */
-static const struct pci_driver i82801db_ide __pci_driver = {
- .ops = &ide_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x24cb,
-};
-
-/* 82801DBM */
-static const struct pci_driver i82801dbm_ide __pci_driver = {
- .ops = &ide_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x24ca,
-};
-
-/* 82801EB & 82801ER */
-static const struct pci_driver i82801ex_ide __pci_driver = {
- .ops = &ide_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x24db,
-};
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-/* From 82801DBM, needs to be fixed to support everything the 82801ER does. */
-
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
* 0x0D - 1101 = Reserved
* 0x0E - 1110 = IRQ14
* 0x0F - 1111 = IRQ15
- * PIRQ[n]_ROUT[7] - PIRQ Routing Control
- * 0x80 - The PIRQ is not routed.
+ *
+ * PIRQ[n]_ROUT[7] - Interrupt Routing Enable (IRQEN)
+ * 0 - The PIRQ is routed to the ISA-compatible interrupt specified above.
+ * 1 - The PIRQ is not routed to the 8259.
*/
#define PIRQA 0x03
* Use the defined IRQ values above or set mainboard
* specific IRQ values in your mainboards Config.lb.
*/
-
static void i82801bx_enable_apic(struct device *dev)
{
uint32_t reg32;
/* Set ACPI base address (I/O space). */
pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
- /* Enable ACPI I/O and power management. */
- pci_write_config8(dev, ACPI_CNTL, 0x10);
+ /* Enable ACPI I/O range decode and ACPI power management. */
+ pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
reg32 = pci_read_config32(dev, GEN_CNTL);
- reg32 |= (3 << 7); /* Enable IOAPIC */
- reg32 |= (1 << 13); /* Coprocessor error enable */
- reg32 |= (1 << 1); /* Delayed transaction enable */
- reg32 |= (1 << 2); /* DMA collection buffer enable */
+ reg32 |= (1 << 13); /* Coprocessor error enable (COPR_ERR_EN) */
+ reg32 |= (3 << 7); /* IOAPIC enable (APIC_EN) */
+ reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */
+ reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */
pci_write_config32(dev, GEN_CNTL, reg32);
printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
static void i82801bx_pirq_init(device_t dev, uint16_t ich_model)
{
- /* Get the chip configuration */
+ u8 reg8;
config_t *config = dev->chip_info;
- if (config->pirqa_routing) {
- pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
- } else {
- pci_write_config8(dev, PIRQA_ROUT, PIRQA);
- }
+ reg8 = (config->pirqa_routing) ? config->pirqa_routing : PIRQA;
+ pci_write_config8(dev, PIRQA_ROUT, reg8);
- if (config->pirqb_routing) {
- pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
- } else {
- pci_write_config8(dev, PIRQB_ROUT, PIRQB);
- }
+ reg8 = (config->pirqb_routing) ? config->pirqb_routing : PIRQB;
+ pci_write_config8(dev, PIRQB_ROUT, reg8);
- if (config->pirqc_routing) {
- pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
- } else {
- pci_write_config8(dev, PIRQC_ROUT, PIRQC);
- }
+ reg8 = (config->pirqc_routing) ? config->pirqc_routing : PIRQC;
+ pci_write_config8(dev, PIRQC_ROUT, reg8);
- if (config->pirqd_routing) {
- pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
- } else {
- pci_write_config8(dev, PIRQD_ROUT, PIRQD);
- }
+ reg8 = (config->pirqd_routing) ? config->pirqd_routing : PIRQD;
+ pci_write_config8(dev, PIRQD_ROUT, reg8);
- /* Route PIRQE - PIRQH (for ICH2-ICH9). */
- if (ich_model >= 0x2440) {
-
- if (config->pirqe_routing) {
- pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
- } else {
- pci_write_config8(dev, PIRQE_ROUT, PIRQE);
- }
-
- if (config->pirqf_routing) {
- pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
- } else {
- pci_write_config8(dev, PIRQF_ROUT, PIRQF);
- }
-
- if (config->pirqg_routing) {
- pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
- } else {
- pci_write_config8(dev, PIRQG_ROUT, PIRQG);
- }
-
- if (config->pirqh_routing) {
- pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
- } else {
- pci_write_config8(dev, PIRQH_ROUT, PIRQH);
- }
- }
+
+ reg8 = (config->pirqe_routing) ? config->pirqe_routing : PIRQE;
+ pci_write_config8(dev, PIRQE_ROUT, reg8);
+
+ reg8 = (config->pirqf_routing) ? config->pirqf_routing : PIRQF;
+ pci_write_config8(dev, PIRQF_ROUT, reg8);
+
+ reg8 = (config->pirqg_routing) ? config->pirqg_routing : PIRQG;
+ pci_write_config8(dev, PIRQG_ROUT, reg8);
+
+ reg8 = (config->pirqh_routing) ? config->pirqh_routing : PIRQH;
+ pci_write_config8(dev, PIRQH_ROUT, reg8);
}
static void i82801bx_power_options(device_t dev)
{
/* Set the value for GPIO base address register and enable GPIO. */
pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1));
- pci_write_config8(dev, GPIO_CNTL, 0x10);
+ pci_write_config8(dev, GPIO_CNTL, GPIO_EN);
}
static void i82801bx_rtc_init(struct device *dev)
* LPT decode defaults to 0x378-0x37F and 0x778-0x77F.
* Floppy decode defaults to 0x3F0-0x3F5, 0x3F7.
* We also need to set the value for LPC I/F Enables Register.
- * Note: ICH-ICH5 registers differ from ICH6-ICH9.
*/
- if (ich_model <= 0x24D0) {
- pci_write_config8(dev, COM_DEC, 0x10);
- pci_write_config16(dev, LPC_EN_ICH0_5, 0x300F);
- } else if (ich_model >= 0x2640) {
- pci_write_config8(dev, LPC_IO_DEC, 0x10);
- pci_write_config16(dev, LPC_EN_ICH6_9, 0x300F);
- }
+ pci_write_config8(dev, COM_DEC, 0x10);
+ pci_write_config16(dev, LPC_EN, 0x300F);
}
static void lpc_init(struct device *dev)
.enable = i82801bx_enable,
};
-static const struct pci_driver i82801aa_lpc __pci_driver = {
- .ops = &lpc_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x2410,
-};
-
-static const struct pci_driver i82801ab_lpc __pci_driver = {
- .ops = &lpc_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x2420,
-};
-
+/* 82801BA/BAM (ICH2/ICH2-M) */
static const struct pci_driver i82801ba_lpc __pci_driver = {
.ops = &lpc_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x2440,
};
-
-static const struct pci_driver i82801ca_lpc __pci_driver = {
- .ops = &lpc_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x2480,
-};
-
-static const struct pci_driver i82801db_lpc __pci_driver = {
- .ops = &lpc_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x24c0,
-};
-
-static const struct pci_driver i82801dbm_lpc __pci_driver = {
- .ops = &lpc_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x24cc,
-};
-
-/* 82801EB and 82801ER */
-static const struct pci_driver i82801ex_lpc __pci_driver = {
- .ops = &lpc_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x24d0,
-};
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-/* This code should work for all ICH* southbridges with a NIC. */
-
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
.scan_bus = 0,
};
-/* Note: There's no NIC on 82801AA/AB (ICH/ICH0). */
-
-/* 82801BA/BAM/CA/CAM (ICH2/ICH2-M/ICH3-S/ICH3-M) */
+/* 82801BA/BAM (ICH2/ICH2-M) */
static const struct pci_driver i82801ba_nic __pci_driver = {
.ops = &nic_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_82801BA_LAN,
};
-
-/* 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) */
-static const struct pci_driver i82801db_nic __pci_driver = {
- .ops = &nic_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801DB_LAN,
-};
-
-/* 82801EB/ER (ICH5/ICH5R) */
-static const struct pci_driver i82801eb_nic __pci_driver = {
- .ops = &nic_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801EB_LAN,
-};
-
-/* 82801FB/FR/FW/FRW/FBM (ICH6/ICH6R/ICH6W/ICH6RW/ICH6-M) */
-static const struct pci_driver i82801fb_nic __pci_driver = {
- .ops = &nic_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801FB_LAN,
-};
-
-/* 82801E (C-ICH) */
-static const struct pci_driver i82801e_nic1 __pci_driver = {
- .ops = &nic_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801E_LAN1,
-};
-
-static const struct pci_driver i82801e_nic2 __pci_driver = {
- .ops = &nic_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801E_LAN2,
-};
-
static void pci_init(struct device *dev)
{
- uint16_t reg16;
+ u16 reg16;
/* Clear system errors */
- reg16 = pci_read_config16(dev, 0x06);
+ reg16 = pci_read_config16(dev, PCI_STATUS);
reg16 |= 0xf900; /* Clear possible errors */
- pci_write_config16(dev, 0x06, reg16);
+ pci_write_config16(dev, PCI_STATUS, reg16);
- reg16 = pci_read_config16(dev, 0x1e);
+ reg16 = pci_read_config16(dev, SECSTS);
reg16 |= 0xf800; /* Clear possible errors */
- pci_write_config16(dev, 0x1e, reg16);
+ pci_write_config16(dev, SECSTS, reg16);
}
static struct device_operations pci_ops = {
.scan_bus = pci_scan_bridge,
};
-static const struct pci_driver i82801aa_pci __pci_driver = {
- .ops = &pci_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x2418,
-};
-
-static const struct pci_driver i82801ab_pci __pci_driver = {
- .ops = &pci_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x2428,
-};
-
-/* 82801BA, 82801CA, 82801DB, 82801EB, and 82801ER */
+/* 82801BA/BAM (ICH2/ICH2-M) */
static const struct pci_driver i82801misc_pci __pci_driver = {
.ops = &pci_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x244e,
};
-
-static const struct pci_driver i82801dbm_pci __pci_driver = {
- .ops = &pci_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x2448,
-};
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 Tyan Computer
- * (Written by Yinghai Lu <yinghailu@gmail.com> for Tyan Computer)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include "i82801bx.h"
-
-/* TODO: Set dynamically, if the user only wants one SATA channel or none
- * at all.
- */
-static void sata_init(struct device *dev)
-{
- /* SATA configuration */
- pci_write_config8(dev, 0x04, 0x07);
- pci_write_config8(dev, 0x09, 0x8f);
-
- /* Set timmings */
- pci_write_config16(dev, 0x40, 0x0a307);
- pci_write_config16(dev, 0x42, 0x0a307);
-
- /* Sync DMA */
- pci_write_config16(dev, 0x48, 0x000f);
- pci_write_config16(dev, 0x4a, 0x1111);
-
- /* 66 MHz */
- pci_write_config16(dev, 0x54, 0xf00f);
-
- /* Combine IDE - SATA configuration */
- pci_write_config8(dev, 0x90, 0x0);
-
- /* Port 0 & 1 enable */
- pci_write_config8(dev, 0x92, 0x33);
-
- /* Initialize SATA. */
- pci_write_config16(dev, 0xa0, 0x0018);
- pci_write_config32(dev, 0xa4, 0x00000264);
- pci_write_config16(dev, 0xa0, 0x0040);
- pci_write_config32(dev, 0xa4, 0x00220043);
-}
-
-static struct device_operations sata_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = sata_init,
- .scan_bus = 0,
- .enable = i82801bx_enable,
-};
-
-/* 82801EB */
-static const struct pci_driver i82801eb_sata_driver __pci_driver = {
- .ops = &sata_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x24d1,
-};
-
-/* 82801ER */
-static const struct pci_driver i82801er_sata_driver __pci_driver = {
- .ops = &sata_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x24df,
-};
.ops_smbus_bus = &lops_smbus_bus,
};
-/* 82801AA (ICH) */
-static const struct pci_driver i82801aa_smb __pci_driver = {
- .ops = &smbus_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801AA_SMB,
-};
-
-/* 82801AB (ICH0) */
-static const struct pci_driver i82801ab_smb __pci_driver = {
- .ops = &smbus_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801AB_SMB,
-};
-
/* 82801BA/BAM (ICH2/ICH2-M) */
static const struct pci_driver i82801ba_smb __pci_driver = {
.ops = &smbus_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_82801BA_SMB,
};
-
-/* 82801CA/CAM (ICH3-S/ICH3-M) */
-static const struct pci_driver i82801ca_smb __pci_driver = {
- .ops = &smbus_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801CA_SMB,
-};
-
-/* 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) */
-static const struct pci_driver i82801db_smb __pci_driver = {
- .ops = &smbus_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801DB_SMB,
-};
-
-/* 82801EB/ER (ICH5/ICH5R) */
-static const struct pci_driver i82801eb_smb __pci_driver = {
- .ops = &smbus_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801EB_SMB,
-};
-
-/* 82801FB/FR/FW/FRW/FBM (ICH6/ICH6R/ICH6W/ICH6RW/ICH6-M) */
-static const struct pci_driver i82801fb_smb __pci_driver = {
- .ops = &smbus_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801FB_SMB,
-};
-
-/* 82801E (C-ICH) */
-static const struct pci_driver i82801e_smb __pci_driver = {
- .ops = &smbus_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801E_SMB,
-};
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-/* This code should work for all ICH* southbridges with USB. */
-
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
.enable = i82801bx_enable,
};
-/* 82801AA (ICH) */
-static const struct pci_driver i82801aa_usb1 __pci_driver = {
- .ops = &usb_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801AA_USB,
-};
-
-/* 82801AB (ICH0) */
-static const struct pci_driver i82801ab_usb1 __pci_driver = {
- .ops = &usb_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801AB_USB,
-};
-
/* 82801BA/BAM (ICH2/ICH2-M) */
static const struct pci_driver i82801ba_usb1 __pci_driver = {
.ops = &usb_ops,
.vendor = PCI_VENDOR_ID_INTEL,
.device = PCI_DEVICE_ID_INTEL_82801BA_USB2,
};
-
-/* 82801CA/CAM (ICH3-S/ICH3-M) */
-static const struct pci_driver i82801ca_usb1 __pci_driver = {
- .ops = &usb_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801CA_USB1,
-};
-
-static const struct pci_driver i82801ca_usb2 __pci_driver = {
- .ops = &usb_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801CA_USB2,
-};
-
-static const struct pci_driver i82801ca_usb3 __pci_driver = {
- .ops = &usb_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801CA_USB3,
-};
-
-/* 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) */
-static const struct pci_driver i82801db_usb1 __pci_driver = {
- .ops = &usb_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801DB_USB1,
-};
-
-static const struct pci_driver i82801db_usb2 __pci_driver = {
- .ops = &usb_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801DB_USB2,
-};
-
-static const struct pci_driver i82801db_usb3 __pci_driver = {
- .ops = &usb_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801DB_USB3,
-};
-
-/* 82801EB/ER (ICH5/ICH5R) */
-static const struct pci_driver i82801eb_usb1 __pci_driver = {
- .ops = &usb_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801EB_USB1,
-};
-
-static const struct pci_driver i82801eb_usb2 __pci_driver = {
- .ops = &usb_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801EB_USB2,
-};
-
-static const struct pci_driver i82801eb_usb3 __pci_driver = {
- .ops = &usb_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801EB_USB3,
-};
-
-static const struct pci_driver i82801eb_usb4 __pci_driver = {
- .ops = &usb_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801EB_USB4,
-};
-
-/* 82801FB/FR/FW/FRW/FBM (ICH6/ICH6R/ICH6W/ICH6RW/ICH6-M) */
-static const struct pci_driver i82801fb_usb1 __pci_driver = {
- .ops = &usb_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801FB_USB1,
-};
-
-static const struct pci_driver i82801fb_usb2 __pci_driver = {
- .ops = &usb_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801FB_USB2,
-};
-
-static const struct pci_driver i82801fb_usb3 __pci_driver = {
- .ops = &usb_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801FB_USB3,
-};
-
-static const struct pci_driver i82801fb_usb4 __pci_driver = {
- .ops = &usb_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801FB_USB4,
-};
-
-/* 82801E (C-ICH) */
-static const struct pci_driver i82801e_usb __pci_driver = {
- .ops = &usb_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801E_USB,
-};
+++ /dev/null
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 Tyan Computer
- * (Written by Yinghai Lu <yinghailu@gmail.com> for Tyan Computer>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include "i82801bx.h"
-
-static void usb_ehci_init(struct device *dev)
-{
- /* TODO: Is any special init really needed? */
- uint32_t cmd;
-
- printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
- cmd = pci_read_config32(dev, PCI_COMMAND);
- pci_write_config32(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER);
-
- printk(BIOS_DEBUG, "done.\n");
-}
-
-static void usb_ehci_set_subsystem(device_t dev, unsigned vendor,
- unsigned device)
-{
- uint8_t access_cntl;
-
- access_cntl = pci_read_config8(dev, 0x80);
-
- /* Enable writes to protected registers. */
- pci_write_config8(dev, 0x80, access_cntl | 1);
-
- /* Write the subsystem vendor and device ID. */
- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
-
- /* Restore protection. */
- pci_write_config8(dev, 0x80, access_cntl);
-}
-
-static struct pci_operations lops_pci = {
- .set_subsystem = &usb_ehci_set_subsystem,
-};
-
-static struct device_operations usb_ehci_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = usb_ehci_init,
- .scan_bus = 0,
- .enable = i82801bx_enable,
- .ops_pci = &lops_pci,
-};
-
-/* 82801DB and 82801DBM */
-static const struct pci_driver i82801db_usb_ehci __pci_driver = {
- .ops = &usb_ehci_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x24cd,
-};
-
-/* 82801EB and 82801ER */
-static const struct pci_driver i82801ex_usb_ehci __pci_driver = {
- .ops = &usb_ehci_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x24dd,
-};
projects / coreboot.git / commitdiff