RS780 function ProgK8TempMmioBase is setting a reserved

bit in the AMD processor 'MMIO Limit Address Register'.
I suspect it is because of a typo where 0x80 was entered
as 0x8. If 0x80 is used, then the strap configuration
register accesses become non-posted, which is how the
Shiner reference BIOS does it.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5919 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/southbridge/amd/rs690/rs690_cmn.c b/src/southbridge/amd/rs690/rs690_cmn.c
index 026341394a670cceb887eabd5ececc42453db503..22d80fcf32696dd44c09b2610aee175dc129df13 100644 (file)
--- a/src/southbridge/amd/rs690/rs690_cmn.c
+++ b/src/southbridge/amd/rs690/rs690_cmn.c
@@ -206,7 +206,7 @@ void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add)
        if (in_out) {
                pci_write_config32(k8_f1, 0xbc,
                                   (((pcie_base_add + 0x10000000 -
-                                    1) >> 8) & 0xffffff00) | 0x8);
+                                    1) >> 8) & 0xffffff00) | 0x80);
                pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3);
                pci_write_config32(k8_f1, 0xb4,
                                   ((mmio_base_add + 0x10000000 -

diff --git a/src/southbridge/amd/rs780/rs780_cmn.c b/src/southbridge/amd/rs780/rs780_cmn.c
index 65dbcb9703da2ab6c770a35011189d0bf07554e3..e4eee3324ca04cc262de68307aad43314c55e206 100644 (file)
--- a/src/southbridge/amd/rs780/rs780_cmn.c
+++ b/src/southbridge/amd/rs780/rs780_cmn.c
@@ -204,7 +204,7 @@ void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add)
        if (in_out) {
                pci_write_config32(k8_f1, 0xbc,
                                   (((pcie_base_add + 0x10000000 -
-                                    1) >> 8) & 0xffffff00) | 0x8);
+                                    1) >> 8) & 0xffffff00) | 0x80);
                pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3);
                pci_write_config32(k8_f1, 0xb4,
                                   ((mmio_base_add + 0x10000000 -