Convert all Intel i810 boards to CAR.

 - Drop "select ROMCC" from the boards, as well as early_mtrr stuff.

 - Add "select CACHE_AS_RAM" to socket_PGA370/Kconfig, as well as the
   usual DCACHE_RAM_BASE and DCACHE_RAM_SIZE variables.

 - In socket_PGA370/Makefile.inc add:
   cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc

 - Other smaller related fixes.

Abuild-tested and boot-tested on MSI MS-6178.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5949 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/cpu/intel/socket_PGA370/Kconfig b/src/cpu/intel/socket_PGA370/Kconfig
index 1805e6a294e6268d6f379a9ab98e0078b49ba7e1..bfabfb847172502b1eebd1adbc6d7594c08f6e6a 100644 (file)
--- a/src/cpu/intel/socket_PGA370/Kconfig
+++ b/src/cpu/intel/socket_PGA370/Kconfig
@@ -21,10 +21,22 @@ config CPU_INTEL_SOCKET_PGA370
        bool
        select MMX
        select UDELAY_TSC
+       select CACHE_AS_RAM
+
+if CPU_INTEL_SOCKET_PGA370
 
 # Not all CPUs for Socket 370 can do SSE2
 config SSE2
        bool
        default n
-       depends on CPU_INTEL_SOCKET_PGA370
+
+config DCACHE_RAM_BASE
+       hex
+       default 0xc0000
+
+config DCACHE_RAM_SIZE
+       hex
+       default 0x01000
+
+endif
 

diff --git a/src/cpu/intel/socket_PGA370/Makefile.inc b/src/cpu/intel/socket_PGA370/Makefile.inc
index c857bcee45570a9c2f824276dbe64bb422ad2571..8e590506e624a5b680eaf18a787ee30e5b811ac9 100644 (file)
--- a/src/cpu/intel/socket_PGA370/Makefile.inc
+++ b/src/cpu/intel/socket_PGA370/Makefile.inc
@@ -27,3 +27,5 @@ subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 
+cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc
+

diff --git a/src/cpu/intel/socket_PGA370/socket_PGA370.c b/src/cpu/intel/socket_PGA370/socket_PGA370.c
index 1fc62ba7600c593d40b2d5227b1d4efe32890dc2..fffd983a41731b35ada9514c223e64e748952079 100644 (file)
--- a/src/cpu/intel/socket_PGA370/socket_PGA370.c
+++ b/src/cpu/intel/socket_PGA370/socket_PGA370.c
@@ -1,7 +1,6 @@
 #include <device/device.h>
 #include "chip.h"
 
-
 struct chip_operations cpu_intel_socket_PGA370_ops = {
        CHIP_NAME("Socket PGA370 CPU")
 };

diff --git a/src/mainboard/asus/mew-am/Kconfig b/src/mainboard/asus/mew-am/Kconfig
index afe6a0dee3a5063a6d9e96dc15fd8413b4551d2f..68ac160b33ab66187cc9bfbe3a08db889048cc91 100644 (file)
--- a/src/mainboard/asus/mew-am/Kconfig
+++ b/src/mainboard/asus/mew-am/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select NORTHBRIDGE_INTEL_I82810
        select SOUTHBRIDGE_INTEL_I82801AX
        select SUPERIO_SMSC_SMSCSUPERIO
-       select ROMCC
        select HAVE_PIRQ_TABLE
        select UDELAY_TSC
        select BOARD_ROMSIZE_KB_512

diff --git a/src/mainboard/asus/mew-am/romstage.c b/src/mainboard/asus/mew-am/romstage.c
index 51d97a37dcf0e4f61b8538bc243230f6c727119a..402789c0af9832d0efc17f9453b195da87f2193f 100644 (file)
--- a/src/mainboard/asus/mew-am/romstage.c
+++ b/src/mainboard/asus/mew-am/romstage.c
@@ -26,31 +26,21 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c"
 #include "northbridge/intel/i82810/raminit.h"
 #include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
-
-static inline int spd_read_byte(unsigned int device, unsigned int address)
-{
-       return smbus_read_byte(device, address);
-}
-
 #include "northbridge/intel/i82810/raminit.c"
 /* #include "northbridge/intel/i82810/debug.c" */
+#include <lib.h>
 
-static void main(unsigned long bist)
-{
-       if (bist == 0)
-               early_mtrr_init();
+#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
 
+void main(unsigned long bist)
+{
        smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
        uart_init();
        console_init();
@@ -60,6 +50,4 @@ static void main(unsigned long bist)
        sdram_set_registers();
        sdram_set_spd_registers();
        sdram_enable();
-       /* ram_check(0, 640 * 1024); */
 }
-

diff --git a/src/mainboard/asus/mew-vm/Kconfig b/src/mainboard/asus/mew-vm/Kconfig
index bc952dccbd32484d3d264fe520c409d0712ec881..4e461923add7c0dc45f7fb4fd4786360b051cfc1 100644 (file)
--- a/src/mainboard/asus/mew-vm/Kconfig
+++ b/src/mainboard/asus/mew-vm/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select NORTHBRIDGE_INTEL_I82810
        select SOUTHBRIDGE_INTEL_I82801AX
        select SUPERIO_SMSC_LPC47B272
-       select ROMCC
        select HAVE_OPTION_TABLE
        select HAVE_PIRQ_TABLE
        select UDELAY_TSC

diff --git a/src/mainboard/asus/mew-vm/romstage.c b/src/mainboard/asus/mew-vm/romstage.c
index 30d6a87214b090323465fcdb43da62c294dfdb13..e4c551eb60fd6e247eca7588a80e8d76dbb886f3 100644 (file)
--- a/src/mainboard/asus/mew-vm/romstage.c
+++ b/src/mainboard/asus/mew-vm/romstage.c
@@ -26,42 +26,28 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "superio/smsc/lpc47b272/lpc47b272_early_serial.c"
 #include "northbridge/intel/i82810/raminit.h"
-#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
-
-#define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1)
-
 #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c"
 #include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "northbridge/intel/i82810/raminit.c"
 #include "northbridge/intel/i82810/debug.c"
+#include <lib.h>
 
-static void main(unsigned long bist)
-{
-       if (bist == 0)
-               early_mtrr_init();
+#define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1)
 
+void main(unsigned long bist)
+{
        lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
        uart_init();
        console_init();
-
        enable_smbus();
-
-       /* Halt if there was a built in self test failure. */
        report_bist_failure(bist);
-
-       /* dump_spd_registers(); */
-
+       dump_spd_registers();
        sdram_set_registers();
        sdram_set_spd_registers();
        sdram_enable();
-
-       /* Check RAM. */
-       /* ram_check(0, 640 * 1024); */
 }
-

diff --git a/src/mainboard/ecs/p6iwp-fe/Kconfig b/src/mainboard/ecs/p6iwp-fe/Kconfig
index eecae4d4bd0bc650c47517401134d4bfe0201773..7d377f471741ae75594ef4105c22187e18f066b5 100644 (file)
--- a/src/mainboard/ecs/p6iwp-fe/Kconfig
+++ b/src/mainboard/ecs/p6iwp-fe/Kconfig
@@ -26,7 +26,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select NORTHBRIDGE_INTEL_I82810
        select SOUTHBRIDGE_INTEL_I82801AX
        select SUPERIO_ITE_IT8712F
-       select ROMCC
        select HAVE_PIRQ_TABLE
        select UDELAY_TSC
        select BOARD_ROMSIZE_KB_512

diff --git a/src/mainboard/ecs/p6iwp-fe/romstage.c b/src/mainboard/ecs/p6iwp-fe/romstage.c
index f84ff465c903dcc117652d77955579dee59dec22..b899d938af3f7f8f1df865b0c6cc2fcbb456dc87 100644 (file)
--- a/src/mainboard/ecs/p6iwp-fe/romstage.c
+++ b/src/mainboard/ecs/p6iwp-fe/romstage.c
@@ -27,37 +27,21 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c"
 #include "northbridge/intel/i82810/raminit.h"
 #include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "superio/ite/it8712f/it8712f_early_serial.c"
-
-static inline int spd_read_byte(unsigned int device, unsigned int address)
-{
-       return smbus_read_byte(device, address);
-}
-
 #include "northbridge/intel/i82810/raminit.c"
 #include "northbridge/intel/i82810/debug.c"
+#include <lib.h>
 
-/* Early mainboard specific GPIO setup. */
-static void mb_gpio_init(void)
+void main(unsigned long bist)
 {
-}
-
-static void main(unsigned long bist)
-{
-       if (bist == 0)
-               early_mtrr_init();
-
        it8712f_24mhz_clkin();
        it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter
-       mb_gpio_init();
        uart_init();
        console_init();
        report_bist_failure(bist);
@@ -67,6 +51,4 @@ static void main(unsigned long bist)
        sdram_set_spd_registers();
        sdram_enable();
        dump_spd_registers();
-       /* ram_check(0, 640 * 1024); */
 }
-

diff --git a/src/mainboard/hp/e_vectra_p2706t/Kconfig b/src/mainboard/hp/e_vectra_p2706t/Kconfig
index 7186dae60533a86d03e3d5124335fa7c377608cd..5fab95a2c64f984408a810b7bf43b348d1485172 100644 (file)
--- a/src/mainboard/hp/e_vectra_p2706t/Kconfig
+++ b/src/mainboard/hp/e_vectra_p2706t/Kconfig
@@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select NORTHBRIDGE_INTEL_I82810
        select SOUTHBRIDGE_INTEL_I82801AX
        select SUPERIO_NSC_PC87360
-       select ROMCC
        select HAVE_PIRQ_TABLE
        select UDELAY_TSC
        select BOARD_ROMSIZE_KB_512

diff --git a/src/mainboard/hp/e_vectra_p2706t/romstage.c b/src/mainboard/hp/e_vectra_p2706t/romstage.c
index 50f59df2bac39ef72f3f2274689df5ee469788bf..39cb2669c0a93210a66143fbc101a9ff706086e0 100644 (file)
--- a/src/mainboard/hp/e_vectra_p2706t/romstage.c
+++ b/src/mainboard/hp/e_vectra_p2706t/romstage.c
@@ -26,40 +26,30 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 /* TODO: It's a PC87364 actually! */
 #include "superio/nsc/pc87360/pc87360_early_serial.c"
 /* TODO: It's i810E actually! */
 #include "northbridge/intel/i82810/raminit.h"
-#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c"
 #include "pc80/udelay_io.c"
 #include "lib/debug.c"
 #include "northbridge/intel/i82810/raminit.c"
+#include <lib.h>
 
 /* TODO: It's a PC87364 actually! */
 #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
 
-static void main(unsigned long bist)
+void main(unsigned long bist)
 {
-       if (bist == 0)
-               early_mtrr_init();
-
        /* TODO: It's a PC87364 actually! */
        pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
        uart_init();
        console_init();
-
        enable_smbus();
-
        report_bist_failure(bist);
-
        /* dump_spd_registers(); */
        sdram_set_registers();
        sdram_set_spd_registers();
        sdram_enable();
-       /* ram_check(0, 640 * 1024); */
 }
-

diff --git a/src/mainboard/intel/d810e2cb/romstage.c b/src/mainboard/intel/d810e2cb/romstage.c
index 34371f5834f00046b43ee749bcf3bc0cb2a55693..94f1170534e0ffc5e54336f7f21fef346dd9958b 100644 (file)
--- a/src/mainboard/intel/d810e2cb/romstage.c
+++ b/src/mainboard/intel/d810e2cb/romstage.c
@@ -35,21 +35,15 @@
 #include "cpu/x86/bist.h"
 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
 #include "gpio.c"
+#include "northbridge/intel/i82810/raminit.c"
+/* #include "northbridge/intel/i82810/debug.c" */
 #include <lib.h>
 
 #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
 
-static inline int spd_read_byte(unsigned int device, unsigned int address)
-{
-       return smbus_read_byte(device, address);
-}
-
-#include "northbridge/intel/i82810/raminit.c"
-/* #include "northbridge/intel/i82810/debug.c" */
-
 void main(unsigned long bist)
 {
-       /* Set southbridge and superio gpios */
+       /* Set southbridge and Super I/O GPIOs. */
        mb_gpio_init();
 
        smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
@@ -62,6 +56,4 @@ void main(unsigned long bist)
        sdram_set_registers();
        sdram_set_spd_registers();
        sdram_enable();
-       /* ram_check(0, 640 * 1024); */
 }
-

diff --git a/src/mainboard/mitac/6513wu/Kconfig b/src/mainboard/mitac/6513wu/Kconfig
index 77ed6e9153db5a71f97a6591bac3df00624959cb..fac565e97d687469e61e1e3f86a4eaa891fee211 100644 (file)
--- a/src/mainboard/mitac/6513wu/Kconfig
+++ b/src/mainboard/mitac/6513wu/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select NORTHBRIDGE_INTEL_I82810
        select SOUTHBRIDGE_INTEL_I82801AX
        select SUPERIO_SMSC_SMSCSUPERIO
-       select ROMCC
        select HAVE_PIRQ_TABLE
        select UDELAY_TSC
        select BOARD_ROMSIZE_KB_512

diff --git a/src/mainboard/mitac/6513wu/romstage.c b/src/mainboard/mitac/6513wu/romstage.c
index bbf87568c6af245a76bd4319f83f7ec4a2b89a49..1a2d7c4f0ccbefaf3fdf113433cfe38bb60664c3 100644 (file)
--- a/src/mainboard/mitac/6513wu/romstage.c
+++ b/src/mainboard/mitac/6513wu/romstage.c
@@ -26,31 +26,21 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c"
 #include "northbridge/intel/i82810/raminit.h"
 #include "lib/debug.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
-
-#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
-
-static inline int spd_read_byte(unsigned int device, unsigned int address)
-{
-       return smbus_read_byte(device, address);
-}
-
 #include "northbridge/intel/i82810/raminit.c"
 /* #include "northbridge/intel/i82810/debug.c" */
+#include <lib.h>
 
-static void main(unsigned long bist)
-{
-       if (bist == 0)
-               early_mtrr_init();
+#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
 
+void main(unsigned long bist)
+{
        smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
        uart_init();
        console_init();
@@ -61,6 +51,4 @@ static void main(unsigned long bist)
        sdram_set_registers();
        sdram_set_spd_registers();
        sdram_enable();
-       /* ram_check(0, 640 * 1024); */
 }
-

diff --git a/src/mainboard/msi/ms6178/Kconfig b/src/mainboard/msi/ms6178/Kconfig
index fc8f425d2992ed0cae935ce58bf47a2d2d403d4f..4b6d4e46df6fadc48fce9ef5bf567069a422848d 100644 (file)
--- a/src/mainboard/msi/ms6178/Kconfig
+++ b/src/mainboard/msi/ms6178/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select NORTHBRIDGE_INTEL_I82810
        select SOUTHBRIDGE_INTEL_I82801AX
        select SUPERIO_WINBOND_W83627HF
-       select ROMCC
        select HAVE_PIRQ_TABLE
        select BOARD_ROMSIZE_KB_512
        select HAVE_MAINBOARD_RESOURCES

diff --git a/src/mainboard/msi/ms6178/romstage.c b/src/mainboard/msi/ms6178/romstage.c
index 6d25c4d2e7885f9bbc2e5b643cff327107686866..5aab983c572959645b4198c46e95cd3fccae3dda 100644 (file)
--- a/src/mainboard/msi/ms6178/romstage.c
+++ b/src/mainboard/msi/ms6178/romstage.c
@@ -26,23 +26,19 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "northbridge/intel/i82810/raminit.h"
-#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c"
 #include "pc80/udelay_io.c"
 #include "lib/debug.c"
 #include "northbridge/intel/i82810/raminit.c"
+#include <lib.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-static void main(unsigned long bist)
+void main(unsigned long bist)
 {
-       if (bist == 0)
-               early_mtrr_init();
-
        /* FIXME */
        outb(0x87, 0x2e);
        outb(0x87, 0x2e);
@@ -61,6 +57,4 @@ static void main(unsigned long bist)
        sdram_set_registers();
        sdram_set_spd_registers();
        sdram_enable();
-       /* ram_check(0, 640 * 1024); */
 }
-

diff --git a/src/mainboard/nec/powermate2000/Kconfig b/src/mainboard/nec/powermate2000/Kconfig
index d0f29bb255c53e46bdeb91555313c0a8be528e8f..55050c00016e48f95338cfb4338aab80024fec01 100644 (file)
--- a/src/mainboard/nec/powermate2000/Kconfig
+++ b/src/mainboard/nec/powermate2000/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select NORTHBRIDGE_INTEL_I82810
        select SOUTHBRIDGE_INTEL_I82801AX
        select SUPERIO_SMSC_SMSCSUPERIO
-       select ROMCC
        select HAVE_PIRQ_TABLE
        select UDELAY_TSC
        select BOARD_ROMSIZE_KB_512

diff --git a/src/mainboard/nec/powermate2000/romstage.c b/src/mainboard/nec/powermate2000/romstage.c
index b9a3744e3c18a7099a16c4e8cf626d16add90a18..8f71cc9d4b2c1a1cd657ed71b87e4d67b8a9b56f 100644 (file)
--- a/src/mainboard/nec/powermate2000/romstage.c
+++ b/src/mainboard/nec/powermate2000/romstage.c
@@ -26,34 +26,25 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include <console/console.h>
-#include "lib/ramtest.c"
 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
 #include "northbridge/intel/i82810/raminit.h"
-#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
 #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c"
 #include "pc80/udelay_io.c"
 #include "northbridge/intel/i82810/raminit.c"
+#include <lib.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
 
-static void main(unsigned long bist)
+void main(unsigned long bist)
 {
-       if (bist == 0)
-               early_mtrr_init();
-
        smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
        uart_init();
        console_init();
-
        enable_smbus();
-
        report_bist_failure(bist);
-
        /* dump_spd_registers(); */
        sdram_set_registers();
        sdram_set_spd_registers();
        sdram_enable();
-       /* ram_check(0, 640 * 1024); */
 }
-

diff --git a/src/northbridge/intel/i82810/debug.c b/src/northbridge/intel/i82810/debug.c
index 5bddbb60a329ebafec8955324bf7d882dfd8896c..55af01bc22fcc974840b860fc3ca9f24275e736a 100644 (file)
--- a/src/northbridge/intel/i82810/debug.c
+++ b/src/northbridge/intel/i82810/debug.c
@@ -1,6 +1,6 @@
-
 static void dump_spd_registers(void)
 {
+#if CONFIG_DEBUG_RAM_SETUP
        int i;
        print_debug("\n");
        for(i = 0; i < DIMM_SOCKETS; i++) {
@@ -32,4 +32,5 @@ static void dump_spd_registers(void)
                        print_debug("\n");
                }
        }
+#endif
 }

diff --git a/src/northbridge/intel/i82810/raminit.c b/src/northbridge/intel/i82810/raminit.c
index 9927cb65c0e1b0844d907c7aff1a36f133e7c94a..3ddc8a02e66811132a8fc6e1ea4b6c178020d5b5 100644 (file)
--- a/src/northbridge/intel/i82810/raminit.c
+++ b/src/northbridge/intel/i82810/raminit.c
@@ -137,6 +137,11 @@ struct dimm_info {
 SDRAM configuration functions.
 -----------------------------------------------------------------------------*/
 
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+       return smbus_read_byte(device, address);
+}
+
 /**
  * Send the specified RAM command to all DIMMs.
  *