Use void pointers for untyped memory

To avoid unnecessary casts, we can use untyped pointers when accessing
individual records.

Change-Id: I1d628d6e25f1e53b4fee34e7c2c4688a789c45a3
Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
Reviewed-on: http://review.coreboot.org/498
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Use convenience function to checksum

That coreboot uses the IP checksum is an artifact, not a deliberate
requirement to be compatible with the Internet Protocole suite. Use
a wrapper to abstract the computation of coreboot's checksum.

Change-Id: I6491b9ba5efb9ffe5cb12a6172653a6ac80a1370
Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
Reviewed-on: http://review.coreboot.org/497
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Replace UNPACK_CB64 macro with inline

Having submitted a module based on coreboot to LKML for acceptance,
it was requested that fewer macros and more inlines be used (because
of their superior type-checking when performing pointer casts, etc).

This is the first of several changes to make the relevant parts of
coreboot comply to linux code standards.

Change-Id: Iffe7061fa62fa639e0cb6ccb9125eb3403d06b1a
Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
Reviewed-on: http://review.coreboot.org/495
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

south_station: Enable GNB hd audio

Enable HD audio over HDMI.
Tested in Ubuntu-11.10 with ATI Catalyst Proprietary Driver installed.

Change-Id: I013c2c15ee56a7b134d980da1aa1856778a1eb4c
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Reviewed-on: http://review.coreboot.org/450
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

Add RS780 defaut graphics ID to AMD Mahogany mainboard.

Added the default ID to the mainboard Kconfig.

Change-Id: Ie5d39ccdda9d4f5a86214b5bd9ca629070ff152a
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/488
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)

Respect linker order

Linking fails when using -Wl,--as-needed and/or esp. when forcing --as-needed
through a compiler specs file.
A proper compile/link command would look like: $(CC) $(CFLAGS) $(LDFLAGS) -o foo
$(OBJS) $(LIBS). So the *FLAGS must be passed *before* the objects while the
libraries/dependencies must be passed *after* the objects.
For more details see: http://www.gentoo.org/proj/en/qa/asneeded.xml

Change-Id: I5a5b05e1cab8a2d88ce56c92d9b2f991ca1ee6c0
Signed-off-by: Christian Ruppert <idl0r@qasl.de>
Reviewed-on: http://review.coreboot.org/494
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

kbd: wait longer for self-test on keyboard reset

Some keyboards take pretty long to respond to a reset command, some even
delay the ACK to the command. To make the keyboard driver more robust,
increase the timeout for this special command. Also do an interface test
after the self-test to ensure the keyboard is functioning properly.

Another point is to reenable the keyboard *after* the scancode was set,
not before. We also set the system bit when enabling the keyboard
because this seems to be what older operating systems do expect.

One of the problematic keyboards, which will work with this patch
applied, is the DELL RT7D20. Without the patch an overly optimistic
operating system, read Linux 2.4, will not recognise the keyboard
because coreboot didn't fully initialize it.

Change-Id: I28c8e05bdde61f71b7de084c96bc2447c1b9575e
Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
Reviewed-on: http://review.coreboot.org/486
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Persimmon audio codec verb patch.

Verb data is required for the HDA audio codec in the sb800 southbridge. Verb
data is not required for mainboards that use G-Series HDMI. It is also a setting
the may be boards specific. This fixes issues with Windows audio on Persimmon.

Change-Id: I067506871e92078d122cf79872363d8937d47e50
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/490
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

.gitignore util/crossgcc/build-* and unpacked source directories

Change-Id: I85b9dffbbe0c7f1ae8cc2b584196775ba2f816df
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/484
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Lenovo X60/T60: add first_battery setting

The EC allows to select the order in which batteries are (dis)charged.
Make this setting available to the user.

Change-Id: Id2a98192565419dbb53f3a7cf0b2c46b672a3ed8
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/475
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Peter Stuge <peter@stuge.se>

asus k8v-x: explicitly set RAM and bus voltages

Change-Id: I9426cafc252ee765d723af569c4a90e090d313d9
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/482
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>

k8: add CONFIG_K8_FORCE_2T_DRAM_TIMING and enable it for asus k8v-x

Change-Id: Ia457f92f6fb7e287defb838db07f12d0f1766757
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/481
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>

Fix console output in real mode int10 implementation.

Checking RBIL, int10 AH=0x10 does never output a character.
The two output functions are AH=0x09 and AH=0x0e.

Change-Id: Id7f4d260b63024748ef771f949e8b60f934bacbc
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/483
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

libpayload: add set_option() function

It allows to change CMOS values from payloads

Change-Id: I4872fc27476923adafe13504126235b92b30de85
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/445
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Fix CMOS handling for non-USE_OPTION_TABLE configuration

The read_option macro still emitted CMOS_VSTART_*/CMOS_VEND_* symbols,
which fail without an option table (as no option_table.h defines them).

Discard them by using a macro instead of a static inline function.

Change-Id: I8d001f971681277a344b6788725746491546b607
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/442
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Use MMCONF for all AMD family 10 CPUs.

This fixes problems in AP init when multiple APs are trying to access
PCI config space. All Fam10 CPUs setup and support MMCONF.

Change-Id: I00a25bbf4e4152c89024f14a3c4c1c36b48d0128
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/455
Tested-by: build bot (Jenkins)
Reviewed-by: Alec Ari <neotheuser@ymail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Change DSDT Table ID for M4A785T-M board

Change the DSDT Table ID for M4A785T-M
from M4A785-M to M4A785T-M.

This fixes a small copypasta.

This is an updated patch set.

Change-Id: I43ee024222cf04d03685ffaee616971100cc9e6c
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/474
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Fix ldscript for bootblock .rom section

Allocation size for the section was miscalculated, so the section
did not honour its upper-bound address.

Also align the section start to 4 bytes, so it starts with code
instead of pad bytes.

Change-Id: Ic2a43981836a0873b50abecfcad2def7b6586a5d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/453
Tested-by: build bot (Jenkins)
Reviewed-by: Alec Ari <neotheuser@ymail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Fix AMD 8132 and 8151 southbridge builds

Untested, changes ramstage build for boards:
  supermicro/h8qme_fam10
  amd/serengeti_cheetah
  amd/serengeti_cheetah_fam10

AMD 8132 was not built for any mainboard due to a typo.

AMD Serengeti Cheetah:
  Chip 8151 is referenced in devicetree.cb but was not built.

AMD Serengeti Cheetah Family10:
  There are indications the board has 8151, but it is not listed
  in the devicetree.cb. The 8151 chip is not added in the build.

Change-Id: I03acdfcc3f3440bd32e81a9a696159903bbbcb50
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/471
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

Bootblock does not need a unique boot_cpu()

Detection of a CPU being a BSP CPU is not dependent of the existence
of northbridge and/or southbridge init code in the bootblock.

Even if CONFIG_LOGICAL_CPUS==0, boot_cpu() can get executed on an AP
CPU of a hyper-threading CPU and needs to return actual BSP bit from
MSR.

Change-Id: I9187f954bb357ba1dbd459cfe11cc96cb7567968
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/447
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

RS780: print the vgainfo

With this commit the vgainfo is printed and looks like that on the serial console:
vgainfo:
  ulBootUpEngineClock:50000
  ulBootUpUMAClock:66700
  ulBootUpSidePortClock:0
  ulMinSidePortClock:0
  ulSystemConfig:0
  ulBootUpReqDisplayVector:0
  ulOtherDisplayMisc:0
  ulDDISlot1Config:0
  ulDDISlot2Config:0
  ucMemoryType:0
  ucUMAChannelNumber:1
  ucDockingPinBit:0
  ucDockingPinPolarity:0
  ulDockingPinCFGInfo:0
  ulCPUCapInfo: 2
  usNumberOfCyclesInPeriod:0
  usMaxNBVoltage:0
  usMinNBVoltage:0
  usBootUpNBVoltage:0
  ulHTLinkFreq:20000
  usMinHTLinkWidth:8
  usMaxHTLinkWidth:8
  usUMASyncStartDelay:100
  usUMADataReturnTime:300
  usLinkStatusZeroTime:600
  ulHighVoltageHTLinkFreq:20000
  ulLowVoltageHTLinkFreq:20000
  usMaxUpStreamHTLinkWidth:8
  usMaxDownStreamHTLinkWidth:8
  usMinUpStreamHTLinkWidth:8
  usMinDownStreamHTLinkWidth:8

Change-Id: I17c2a13ab52a0f78588f812d4f42f45f9a7b7524
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/456
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

adding support for the Asus K8V-X

This pulls it all together and adds the real board-specific code.

Confirmed to be working:
- IDE
- SATA
- floppy
- USB1.1
- USB2.0
- PS/2 keyboard
- PS/2 mouse
- serial
- parport
- sound
- ethernet
- PCI slots
- AGP
- powernow
- fan speed monitoring
- flashrom write

Change-Id: Ifb97714c2f009d688be0ca3c38ddc01599ffd799
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/390
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Tested-by: build bot (Jenkins)

Fix Asus A8V-E SE DIMM slot mapping

Fix the DIMM mappings, channel 0 is "B" on board,
and secondary channel is on 0x51,0x53

Change-Id: I8c49c4efb90a4297aaea0be2159435dadab9ac0a
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/449
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

make GPIOs and misc configurable via devicetree

Change-Id: I9f70da76b5ea451f28a1ad9252c5d879fc4fe315
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/387
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

make INT[EFGH]# of vt8237 configurable as gpio via devicetree

Change-Id: I70202d81ddd1b0a00eddca4acabc621e5783e805
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/386
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

copied asus a8v-e_se to k8v-x

Change-Id: Ib66e8c5102ad45e73977a06aea109ed9544f4d08
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/389
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

some black magic for initializing the old version of the k8t800

Change-Id: I1b5d23cee9f933aa090c9bd09890c7b335567e17
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/388
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

implement usb2 termination and dpll delay setting for vt8237r

Change-Id: I830c9a3daf5ac2e1ecd9a3e725a0b98f06509769
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/385
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

i3100: Add HAVE_HARD_RESET

and remove it from mainboard/intel/mtarvon, as this function
is implemented in the southbridge code.

Change-Id: Id3669aaf99b96b4a7a965f4957e5de7c365acaa6
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/469
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Mirror Fix coreinfo usage of cb_info

fix cb_info.serial.ioport to cb_info.serial.baseaddr

Change-Id: I32f261e4be927555979eb833d0251fce2c6a5c47
Signed-off-by: QingPei Wang <wangqingpei@gmail.com>
Reviewed-on: http://review.coreboot.org/441
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

M4A785T-M: fix ACPI's P-States Table

Without that fix the linux kernel cannot change the frequency
  of the CPUs with cpufreq.

Change-Id: Ie00e4b11b2561356952d8ae28bd0a00523b6d85f
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/458
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Add ASUS M4A785T-M mainboard support

This mainboard is very similar to the M4A785-M, but it has
  DDR3 instead of DDR2.

That's why most of the code was copied or included from
  the m4a785-m directory

Notable changes between the two mainboards include:
 * the selection of the last microcode (mc_patch_010000b6.h)
   which made it pass the CPU init.
 * the selection of DDR3 which made it pass the ram init

This change was tested with the Trisquel 5.0 GNU/Linux distribution
  which uses the linux-libre version 2.6.38-12-generic

The mainboard boots fine, however some special care is required for
  the onboard sound CODEC, and the onboard video chip:
  * the onboard sound CODEC(snd-hda-* has to be blacklisted), the issue
    is the same than the ASUS M4A785-M mainboard:
    It causes a flood of interupts which prevents booting
  * The internal video chip currently requires pci=nocrs, else
    the graphics are frozen as soon as the radeon module loads,
    and dmesg would print the following(the card only has 256M,
    and the mainboard was equiped with 2G of RAM):
      [    3.674762] [drm] radeon: 3584M of VRAM memory ready
      [    3.679863] [drm] radeon: 512M of GTT memory ready.
    instead of :
      [   45.876088] [drm] radeon: 256M of VRAM memory ready
      [   45.876089] [drm] radeon: 512M of GTT memory ready.
  * The screen(both VGA and HDMI) flickers at high resolution
  * Sometimes the computer freeze while changing the resolution
    (even the serial console stops responding)

The following peripherals were tested:
 * The ath9k PCI wireless card was tested
 * The SATA hard disk works fine
 * the USB keyboard and mouse work fine
 * htop see 2 cores
 * serial port works under coreboot and GNU/Linux
 * power off and reboot works

CPU frequency cannot be changed yet, this is addressed
  in a new commit.

More detail are available here:
  http://www.coreboot.org/ASUS_M4A785T-M

dmesg is available here:
  http://www.coreboot.org/pipermail/coreboot/2011-November/067604.html

The mailing list thread on the graphic problem is here:
  http://www.coreboot.org/pipermail/coreboot/2011-November/067466.html

Change-Id: I5df0bc1f9f0071b1e1ee7c8a356bf517aa8cf732
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/457
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Remove obsolete TINY_BOOTBLOCK

Change-Id: I0edc69dc5f95cc32ee648eb094c9e5387f80db47
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/470
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Change AMD vendorcode build

Apply the normal method of recursively including subdirectories
for src/vendorcode. Remove redundant references under
mainboard and northbridge.

Change-Id: I914a6e262ed2abe83f407df36fe5c1af5eb4bcb0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/468
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

X60/T60: reset baudrate loglevel to sane values

Change-Id: Iaf5861e9db0a41a184da6d2e515e3b9afe0655d6
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/459
Tested-by: build bot (Jenkins)

Remove unused code files and cosmetic changes

Following files were no longer used in the build and are deleted:
   src/arch/x86/init/entry.S
   src/arch/x86/init/ldscript.ld

Also fix ugly whitespace in code copyrights and comments.

Change-Id: Ia6360b0ffc227f372d5f997495697a101f7ad81b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/440
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

vt8237: add support for setting the power state after loss of power

Change-Id: Ia7e3e77235530e952b2e84fdec8373b90fa59b7a
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/437
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

k8 raminit: fix bug, improve clock selection, add clock limit for sock754

in amdk8 raminit:
- fix DDR SPD offset for (CLX - 1) (25 instead of 26)
- improve clock/CL selection algorithm
- implement load-dependent clock limiting for socket 754

Change-Id: I5eb8a3e02eaca18f3bef9a98de22f23b23650762
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/377
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

implement hwmon fan divisor setting for w83697hf

Change-Id: I887ac1142875ca1dc1a1eb8eebec402fbe7512c3
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/384
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Tested-by: build bot (Jenkins)

k8 raminit: add workaround for erratum #181 on non-fam-f

Disable DRAM controller on non-fam-f CPUs not using fam-f register layout.

Change-Id: I2cc87857452555011d69bfebe9f9c4c17cef8f6c
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/448
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

Fix post_code in 16bit entry

Relocate early post_code() so it gets executed and does not corrupt
BIST at %eax.

Change-Id: Ieeebcb23f7c327e501b410eaa60d1e49110ee988
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/439
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

mainboard: Add AMD unionstation RDK support

AMD unionstation Reference Design Kit is Designed for hd settop box application.
This platform using family14 APU, SB800 southbridge.
Vgabios is required, can download vgabios from AMD NDA website.
Verified Feature:
 HDMI, LAN, mini-pcie slots, sata, usb, analog audio and
 optical fiber digital audio output.

Change-Id: Ib1d1d8c889d6fb29f4298b57dfe5c5c1cea1431c
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/434
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

mainboard: Add AMD southstation RDK support

AMD southstation Reference Design Kit is designed for NAS application.
This platform using family14 RevC0 processor, SB850 southbridge.
Vgabios and Promise RAID Option ROM is required for hardware RAID support,
can retrieve from the AMD NDA website.
Verified feature:
 HDMI, LAN, usb and mini-pcie slot.
 RAID0, RAID1 RAID10 and RAID5 upto 6 sata hard drive with ubuntu server 10.10.

Change-Id: I16e6f5dab8b0d634e186068c81436db77fb4475a
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/433
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminit

Change-Id: Ibdce9712f5019863b1cd61b68da11d7c46c6b6f8
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/376
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

libpayload: Enable colors in PDcurses

PDcurses wants set_blink to determine color count. Not exactly
obvious.

Change-Id: I8b2a32f0095d5900fa7e01f04f3f1d565dc2bedf
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/432
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

compile code for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD

make code dependent on CONFIG_SOUTHBRIDGE_VIA_K8T800 also be included
for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD

Change-Id: I9f4624d08de2790fb513a88ed6207e28e7fbc733
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/374
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

support for different location of HT registers in old version of K8T800

Change-Id: I2ad82b8059efb09f0593933cb6f53b51b653d494
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/373
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

libpayload: Fix handling of CAPS LOCK key on PS/2 keyboards

The PS/2 keyboard driver set and reset the caps LED to show the
keyboard status. Unfortunately, that configuration happens over
the same path used to transmit keypresses.

In face of certain error conditions, the keyboard stopped working.
This change makes keyboard handling more robust.

Change-Id: I0489a9983ea7dab00357220e09398dd1a8538839
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/430
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Fixed whitespace and indentation

Code style fixes for the hp/dl145_g1 system board code.

Change-Id: I3c1a175d954e2d340e82c03c9f984699dcff865e
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Reviewed-on: http://review.coreboot.org/428
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

buildgcc: Add option to use ccache

This mimicks abuild: -y enables ccache.

Change-Id: I3ac1f809729af816efbc64f5789ab430e1a6a6b2
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/400
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

make w83697hf_set_clksel_48() non-static and add a prototype

make w83697hf_set_clksel_48() non-static and add a prototype so as to
get rid of warnings about it being unused

Change-Id: I8ae94cfd61ae4774a367f83dd37e488987e2451a
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/380
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

selfboot: Don't include unneeded ip_checksum.h

Change-Id: I09b888e70f7432f7025b0b851acfb0279553400f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/426
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

selfboot: fix bug in valid_area()

valid_area will accept a region as valid for the payload if only a part
of coreboot fits in that region. This means if a payload reaches into a
neighboring RESERVED region, coreboot would not care and happily
overwrite that region, as long as the payload also writes to some RAM.

Change-Id: Ie263f83be18009b01a31c71e7285c998747d097f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/425
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

move function from header file to .c file

http://review.coreboot.org/#change,378 introduced a function in k8x8xx.h
move this function to ctrl.c and add a prototype to the header file instead.

Change-Id: I0919ffb2030c53669b95f58b649d4a160f660923
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/429
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Cleanup Persimmon mainboard whitespace.

Change-Id: I389bde86c5583a4fb37a699162b65b475ed94ddc
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/427
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

selfboot: cleanup

- move cbfs_load_payload to the end so we can drop the prototype
- move lb_start and lb_end to the beginning so they can be used
  in other functions.
- drop two unused function declarations
- break a 80+ characters line
- fix a comment

Change-Id: I460aa1e2ccf9d95ac12233af001076f73ab0268e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/424
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Added RAMINIT_SYSINFO and declared the necessary structs

Using RAMINIT_SYSINFO should be beneficial for this platform.
It is also more clean/safe to put data in struct mb_sysconf_t.
It's more consistent with other MB's and I've tested it
thoroughly on my DL145.

Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Change-Id: Ie90a134a1efc9605b3fe17a5b5008856226984be
Reviewed-on: http://review.coreboot.org/236
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Add code to set the clock speed for Winbond W83627THF/THG.

Change-Id: I984404dd1df50b3ba423ac610283b9bf8bca5a31
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/412
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

superiotool: add detection and dump of Infineon SLB9635 TPM

Change-Id: If94ea5f45135a4b65bdd37532851fa0ba864bb73
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/421
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

buildgcc: don't download python and expat if disabled

Change-Id: I18cb1426e935c46ead30c72685829c20d186f9d8
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/423
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

abuild: Don't try to use files that don't exist

Collecting per-board abuild.xml is bound to fail if there
are no such files.

Change-Id: I6bd6b4389beda51654005e0380f0e52f006642db
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/422
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

rename vt8237r_cfg() to k8x8xx_vt8237r_cfg() and make publicly accessible

Change-Id: I82d1ec5117a58aaa8cfd2a342b7172a2786f5680
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/379
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

factor out common config for k8x8xx's dram_enable() and vt8237r_cfg()

Instead of writing to config registers in k8x8xx's dram_enable()
and reading those back in vt8237r_cfg(), factor out generation of
the values and reuse that in both places.

Change-Id: I87a37398efe84b33e6678df74cd40b5abfe4f879
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/378
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

add support for 1106:3188 (host controller of the old version of k8t800)

Change-Id: Id61678f03e1f7d964f7180a062dd6a689852d4ac
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/401
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Avoid false detection of SMSC FDC37N972 when Infineon TPM is present

Change-Id: Ibfb3af4c5d7675a5d4e27021cbb988c2ce00fd9f
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/420
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

in vt8237r_enable(), write function enables only to ISA bridge config space

vt8237r_enable() so far wrote the function enable values to the same
offset in the config space of every one of the vt8237's functions,
even though the register is located in the ISA bridge only.

Change-Id: I639586dc238132f5b8d2f320b794948718281b9c
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/368
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26

Change-Id: Ic77854130ad43715daa7c0eb462291db48df9f84
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/370
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

buildgcc: Explicitely state CC everywhere

This should fix issues with the iasl Makefile on Debian and
prepares ccache support for buildgcc.

Change-Id: Id9e6b2044b159b19bf013ec5c47b60ca1c2f2991
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/399
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

kconfig: Use more collision resistant temporary filenames

kconfig creates reasonably safe filenames for its temporary files
except for two of them.

Change-Id: I6861f55ae2a5311e3fb7919333ce9af1e39ce78b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/408
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

abuild: Write XML/JUnit files per board

Write them per-board and merge them after everything is done.
This prepares for build parallelization.

Change-Id: Ia4e7ce03473bcf8861fb9ae06e9c1270292401ac
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/407
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

abuild: Refactor parallelization support

Use MAKEFLAGS to propagate the parallelization configuration to
the build

Change-Id: If90ed446edd8e6dc679d284ee9db7a24269edd36
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/406
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

abuild: Avoid race condition when running abuild parallely

By moving the just-created file away, parallel runs of abuild might break.

Change-Id: I03368f00e9b11dad4c80d41279970e28debc7ed5
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/405
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Inline Makefile.bootblock.inc

This was split out when we had separate rules for big bootblock.

Change-Id: Id0a117f6996fb6bdef7bf97e7d80c36f5dec0ad7
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/404
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Fix typo

Change-Id: I195ea15ddbc725091e32191fac3b84d01b456580
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/410
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

w83627hf: multiple fixes and enhancements in ASL include

Fix multiple copy&paste errors and some other bugs in
devtree.asl. Redesign ENCM method to enter configuration mode
and set LDN by parameter. Reordered and commented some
statements to make the code a bit more readable. Add an ifdef
to enable never showing the keyboard controller as disabled,
which seems to cause bugs at least with some Linux kernels.
Remove keyboard controller IO regions from PS/2 mouse device
as e.g. Linux infers them from the keyboard controller device.

Change-Id: I44611339fabe31a8a584a3e6bd225082bfdd0b8e
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/357
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

w83627hf: drop Scope(\_SB) from ASL include

Drop explicit Scope(\_SB) from devtree.asl as it forces the SuperIO
to appear as child of the root device.
devtree.asl then needs to be included at a reasonable position inside
the \_SB device tree.

Change-Id: I72a57eddc5ec5f9763fdf789094a7be042758256
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/298
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

buildgcc: Fix wrapper Makefile

buildgcc moved from building gdb by default (with opt-out) to
gdb being optional. Adapt Makefile so it works again

Change-Id: I663a8c70db4f7b5d07456fb67a223dbb2de2c133
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/417
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

libpayload: Implement usb_exit

So far it was empty and never published. It now exists and shuts down
all controllers (esp. EHCI which resets the port routers).

Change-Id: I81e355e8a05778d6397675417b085a094a6f48ee
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/397
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

libpayload: Tell EHCI to re-enable USB1 controllers

EHCI can take over all ports (and then reroute devices to
companion controllers if needs be). We do that, and then never
reset it.

Consequence:
Systems with only USB1 HC drivers (OHCI/UHCI) never see any devices.

Change-Id: If1d91e9142a6618289b0b3f6b56587ec857158e3
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/396
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)

libpayload: Drop usb_fatal()

We have fatal(), which is just as good.

Coccinelle script:
  @@
  expression E;
  @@
  -usb_fatal(E)
  +fatal(E)

Change-Id: Iabecbcc7d068cc0f82687bf51d89c2626642cd86
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/395
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)

Revert "add support for 1106:3188 (host controller of the old version of k8t800)" due to dependency issues.

This reverts commit 68c554550f59bd96caace96260ae2e30ed55ceb4

Change-Id: I353bd36b008f489a972c7c656d7ad07416f01387
Reviewed-on: http://review.coreboot.org/398
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

add support for writing to SMBus with vt8237

Change-Id: I70fe072f8f3447d0be7b7ac64508a954fe47091d
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/372
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

add support for 1106:3188 (host controller of the old version of k8t800)

Change-Id: I10135b37a6cef460be9bfbfd34746140310859a6
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/381
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

libpayload: Reduce verbosity in USB stack

The USB stack is pretty noisy. Reduce the output to a sane level.

Change-Id: I250949e5cf74a8c6d43822b2e7487143b2ae1c65
Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
Reviewed-on: http://review.coreboot.org/393
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

libpayload: Put coreboot version into lib_sysinfo

Change-Id: I22319efe90e475c66b9556f734a7a5e54f7c59bc
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/394
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

fix superiotool for NCT6776F

The current code exits config mode of the NCT6776F immediately after
detection, so the register dump shows all 0xffs. This patch adds code to
re-enter config mode for the register dump so that the register contents
can be read.

Change-Id: I4ad0c108b6411a665e31f55dea4b91ca77d1a5f7
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/391
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

simplify IDE cable detection for Asus M2V

Change-Id: If8e4dcf405e24b744ac34f581c5609fcce96fd07
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/371
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

buildgcc: Update coreboot reference toolchain to gcc 4.6.2

In addition:
- drop some unneeded patches
- make the scripting support depend on SKIPPYTHON not SKIPGDB
  so it is possible to build GDB with and without scripting support
- rename the repository checkout version of GCC trunk, not X+1
  so we don't have to change it on every version upgrade.

Change-Id: I1b7d5b8921187c1c1d39b04f20bb715ddba72fe8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/367
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

don't scan beyond end of CBFS

Change-Id: I66e535f77e513dbfa5fc906ecf288193af78ae62
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/369
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Add Python scripting to GDB.

This allows GDB to run Python scripts. The Python build is dependant on the GDB
build flag.

Changes by Stefan Reinauer:
- update to latest buildgcc script
- disable GDB per default
- disable python scripting, if GDB is not enabled
- bump version number to 1.06

Change-Id: Ie7fc8706deec41c804870415d3c79d225c98cd31
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/153
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)

libpayload: remove trailing whitespace and run dos2unix

Change-Id: Iffed3602456f5306711c65f06c873c58d4086e11
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/363
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

libpayload: Fix OHCI some more

OHCI works when USB_DEBUG is disabled, but not, when disabled.
This is because the controller requires some more time after a
schedule has finished.

Also improve compliance with the OHCI spec.

Change-Id: I4685cc485ff9c52b489fbaa352ab889671cff876
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/365
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

remove trailing whitespace

Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/364
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

Remove XIP_ROM_BASE

The base is now calculated automatically, and all mentions of that
config option were typical anyway (4GB - XIP_ROM_SIZE).

Change-Id: Icdf908dc043719f3810f7b5b85ad9938f362ea40
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/366
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Run dos2unix on bayou and remove white space at the end of lines.

Change-Id: If13d9a49ece2699885ae3e998173d3d44507b302
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/362
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>

buildgcc: Fix colors for dash

The previous fix broke buildgcc colors on MacOS X.
This uses an encoding that should be more universal.

Change-Id: I31ac6090ffb7c04784cf6566823652f229aebbb5
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/361
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Add support for E7505 northbridge.

Adapted from northbridge/intel/e7501 with only minor changes.
This commit provides minimal patch from e7501 and I prefer any
cosmetic clean-up to be done after initial merge.

Due the incomplete register specifications, it is safer to have
e7505 as a separate directory in case I improve it to support
wider range of memory configurations. I have no e7501 to test with.

Change-Id: Iba3bf9d69ff5e9d9ef3a6ebf8259f048c55d637d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/295
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Fix usb debug dongle support

- move enable_usbdebug() declaration to usbdebug.h
- reinitialize debug driver in ramstage, as copying the data
  structure from romstage doesn't work right now. This way of copying
  data from romstage to ramstage is really board/cpu specific, and is
  likely to break often. So don't do it.

Change-Id: I394678ded6679c1803e29eb691b926182bdcab68
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/355
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

crossgcc: Fix colors with dash

Ubuntu (and probably other distros) have dash as /bin/sh, which
doesn't display colors by itself. If /usr/bin/printf is found, it's
used instead of the internal printf to re-enable colors.

Change-Id: I3e6d413cd0c8a46ef91821d8c07e88166de58af4
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/352
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Fix slow CAR execution introduced by 7c7d87182feb78cb2bc02fb3558bef56a41682c9

It is meant to be a address and not a dereference. Otherwise MTRR
is filled with code and not with the address.

This is what I hate at most on the AT&T syntax. Instead of taking
the address, it was a dereference. Not greatly visible, except
I wondered why opcode is not 0xb4 but 0xa1 and it took another
half an our to see it.

Change-Id: I6b339656024de8f6e6b3cde63b16b7ff5562d055
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/358
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)