compile code for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD

make code dependent on CONFIG_SOUTHBRIDGE_VIA_K8T800 also be included
for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD

Change-Id: I9f4624d08de2790fb513a88ed6207e28e7fbc733
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/374
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

diff --git a/src/southbridge/via/k8t890/romstrap.inc b/src/southbridge/via/k8t890/romstrap.inc
index 5b24948df515e3a0a1716ceeba48e9a6cda579d1..a3814b096b9fce9a95297e6ff7c7927ce5554f5e 100644 (file)
--- a/src/southbridge/via/k8t890/romstrap.inc
+++ b/src/southbridge/via/k8t890/romstrap.inc
@@ -33,7 +33,7 @@ __romstrap_start:
  * Below are some Dev0 Func2 HT control registers values,
  * depending on strap pin, one of below lines is used.
  */
-#if CONFIG_SOUTHBRIDGE_VIA_K8M800 || CONFIG_SOUTHBRIDGE_VIA_K8T800
+#if CONFIG_SOUTHBRIDGE_VIA_K8M800 || CONFIG_SOUTHBRIDGE_VIA_K8T800 || CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD
 
 tblpointer:
 .long 0x50220000, 0X619707C2

diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index e59951702f00094fb5c5b5ba8820438e35991d02..b1e1afe9c25a0f84ef6df6e559298eb0ae9ae8c6 100644 (file)
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -298,7 +298,7 @@ static void vt8237r_init(struct device *dev)
        pci_write_config8(dev, 0x48, 0x0c);
 #else
 
-  #if CONFIG_SOUTHBRIDGE_VIA_K8T800
+  #if CONFIG_SOUTHBRIDGE_VIA_K8T800 || CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD
        /* It seems that when we pair with the K8T800, we need to disable
         * the A2 mask
         */