make INT[EFGH]# of vt8237 configurable as gpio via devicetree

Change-Id: I70202d81ddd1b0a00eddca4acabc621e5783e805
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/386
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

diff --git a/src/southbridge/via/vt8237r/chip.h b/src/southbridge/via/vt8237r/chip.h
index 2e24fac4f89d396fdd236ad5e05a3ebdfe4c211e..bbba5e4d85475fb58cab91939f7bb0ec91e83b12 100644 (file)
--- a/src/southbridge/via/vt8237r/chip.h
+++ b/src/southbridge/via/vt8237r/chip.h
@@ -69,6 +69,8 @@ struct southbridge_via_vt8237r_config {
 
        u8 usb2_dpll_set;
        u8 usb2_dpll_delay;
+
+       u8 int_efgh_as_gpio;
 };
 
 #endif /* SOUTHBRIDGE_VIA_VT8237R_CHIP_H */

diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index 207dfdb33539a989dc465b32b7d7d84e4e85f228..43a9394bfae21e0de13234342c8305811a3dc153 100644 (file)
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -421,10 +421,13 @@ static void vt8237s_init(struct device *dev)
 static void vt8237_common_init(struct device *dev)
 {
        u8 enables, byte;
+       struct southbridge_via_vt8237r_config *cfg;
 #if !CONFIG_EPIA_VT8237R_INIT
        unsigned char pwr_on;
 #endif
 
+       cfg = dev->chip_info;
+
        /* Enable addr/data stepping. */
        byte = pci_read_config8(dev, PCI_COMMAND);
        byte |= PCI_COMMAND_WAIT;
@@ -509,7 +512,11 @@ static void vt8237_common_init(struct device *dev)
         *     | bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch
         *   0 | Dynamic Clock Gating Main Switch (1=Enable)
         */
-       pci_write_config8(dev, 0x5b, 0xb);
+       if (cfg && cfg->int_efgh_as_gpio) {
+               pci_write_config8(dev, 0x5b, 0x9);
+       } else {
+               pci_write_config8(dev, 0x5b, 0xb);
+       }
 
        /* configure power state of the board after loss of power */
        if (get_option(&pwr_on, "power_on_after_fail") < 0)