Patrick Georgi [Thu, 24 Nov 2011 10:55:46 +0000 (11:55 +0100)]
libpayload: Remove bitfield use from UHCI data structures
We agreed that bitfields are a Bad Idea[tm].
Change-Id: I1b2bcda28c52ad10bbe9429e04d126b555f7828a
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/478
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Peter Stuge <peter@stuge.se>
Patrick Georgi [Thu, 24 Nov 2011 08:12:11 +0000 (09:12 +0100)]
libpayload: Remove bitfield use from OHCI data structures
We agreed that bitfields are a Bad Idea[tm].
Change-Id: Ic04f151091c359912835b8b3db488d2d41bd4bbb
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/479
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Peter Stuge <peter@stuge.se>
Patrick Georgi [Fri, 1 Jul 2011 22:35:02 +0000 (00:35 +0200)]
Un-perl commit-msg hook
To simplify installation on mingw a bit (even though git remains a pain),
drop the perl dependency the commit-msg hook introduced to the coreboot
development environment.
It's replaced by awk which we use elsewhere already (and is a more lightweight
utility in any case)
Change-Id: I67adfe1ec43c898735d4bae4819ceb53e83c303b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/78
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Nils Jacobs [Mon, 9 Jan 2012 19:27:07 +0000 (20:27 +0100)]
Fix Geode GX2 + LX caching for tiny bootblock.
Change-Id: If681a33deb7df752b37c6a8a20482d3c374af936
Signed-off-by: Nils Jacobs <njacobs8@adsltotaal.nl>
Reviewed-on: http://review.coreboot.org/528
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Philip Prindeville <philipp@redfish-solutions.com>
Sven Schnelle [Fri, 23 Dec 2011 09:29:09 +0000 (10:29 +0100)]
ACPI: mark empty get_cst_entries() weak
This function prevents the linker from choosing the right
get_cst_entries(), preventing writing the _CST tables.
Change-Id: I4bc0168aee110171faeaa081f217dfd1536bb821
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/496
Tested-by: build bot (Jenkins)
Jonathan A. Kollasch [Sat, 7 Jan 2012 16:17:50 +0000 (10:17 -0600)]
rs780: correct comment in switching_gpp_configurations()
Change-Id: I6417a92523eea7307d080669fbc4e16ee28c8a6c
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/524
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Vikram Narayanan [Sat, 7 Jan 2012 10:34:46 +0000 (16:04 +0530)]
adm1027: add return statement
Adds a missing return statment which will stop misleading the users
Change-Id: I53741f1136b396e9493ce959b54efc00c9b09764
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-on: http://review.coreboot.org/522
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Sven Schnelle [Sun, 8 Jan 2012 14:27:18 +0000 (15:27 +0100)]
inteltool: Add support for dumping AMB registers
Change-Id: I98615725afdb315caa67b2226224e3eb2a0e4393
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/525
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Peter Stuge [Wed, 14 Dec 2011 06:39:57 +0000 (07:39 +0100)]
.gitignore ectool, inteltool, msrtool, nvramtool and superiotool
Change-Id: I06e69d97ef3646f79104ec316ce932cc53894c92
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/485
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Philip Prindeville [Sat, 24 Dec 2011 01:45:33 +0000 (18:45 -0700)]
Eliminate magic numbers
Use sizeof() on vendor and part# rather than explicit memory length.
Change-Id: I2b7e0e4a8df6448d027cc61867382f161eb990d3
Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
Reviewed-on: http://review.coreboot.org/504
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Philip Prindeville [Sun, 25 Dec 2011 05:12:37 +0000 (22:12 -0700)]
Cleanup access to vendor/part # info
Instead of macros to access MAINBOARD record, use convenience functions.
Store pointers to MAINBOARD and HEADER for use outside of CB code.
Change-Id: I074e3a0df7d25726cbd942538bfdc5a63dd17e12
Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
Reviewed-on: http://review.coreboot.org/502
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Nils Jacobs [Fri, 30 Dec 2011 22:00:11 +0000 (23:00 +0100)]
Update geode GX2 tree to match LX.
Change-Id: I5b99c531e44ea09990b9da0b97213fb7945f34ee
Signed-off-by: Nils Jacobs <njacobs8@adsltotaal.nl>
Reviewed-on: http://review.coreboot.org/512
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Jonathan A. Kollasch [Thu, 5 Jan 2012 01:37:48 +0000 (19:37 -0600)]
rs780: use bitwise rather than boolean not
Change-Id: Ie3872c57990f9784aafda14f8c7fc842b3a65260
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/518
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Vikram Narayanan [Mon, 26 Dec 2011 17:22:01 +0000 (22:52 +0530)]
Indentation: Various indentation fixes
Fixed indentation using indent tool in the src/drivers/i2c tree
Change-Id: I5b396e5753544aff13ac5d16afc59e193a6b1da1
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-on: http://review.coreboot.org/506
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Marc Jones [Tue, 13 Dec 2011 05:04:25 +0000 (22:04 -0700)]
Fix Fam14 AGESA ACPI table generation
The AGESA wrapper init late call generates the SSDT and other ACPI tables. The
call was failing without heap space allocated causing the ASSERT messages in
the output. I think are there may still be other issues in integrating the
SSDT table with the DSDT, but now it is there to debug.
The changes were made in Persimmon and copied to the other Fam14 mainboards.
Change-Id: I2cfd14e07cb46d2f46f5a8cd21c4c9aab44e4ffd
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/517
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Marc Jones [Tue, 13 Dec 2011 04:12:43 +0000 (21:12 -0700)]
Clean up AMD Fam14 SSDT
The old SSDT ACPI code would only include the AGESA or the coreboot SSDT. Now
include both. AGESA generates the Pstate SSDT and the second coreboot SSDT is
for TOM and TOM2. Now, generate the coreboot SSDT instead of patching it. This
fixes some ACPI errors in Linux and Windows bluescreens.
The Persimmon acpi_tables.c is where the main changes were made and then
replicated in the other Fam14 boards. Please test the other mainbords if you
have one.
Change-Id: I808c863597e024e3e8aeec0821e8618d96cc96a6
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/516
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Marc Jones [Tue, 3 Jan 2012 23:02:07 +0000 (16:02 -0700)]
Fix Fam14 mainboard whitespace
Fix whitespace and tab issues on fam14 mainbords in preperations for upcoming
changes
Change-Id: I6d63d428dde0a5d9748027e603b03de25d3be472
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/515
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Jonathan A. Kollasch [Thu, 5 Jan 2012 01:43:49 +0000 (19:43 -0600)]
rs780: power down GPPSB SB lane pads in correct PCIe core
Change-Id: I059d5b155cae051f31cc2495f8a47d53e01af808
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/519
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Jonathan A. Kollasch [Tue, 3 Jan 2012 01:11:49 +0000 (19:11 -0600)]
Add missing EOT marker.
Omitted from commit
3d1d6bb4ecb15a12f48f871c623882bee9c0c576
Change-Id: Id3e94d615d50f0673cc5e3fde77ed6748d26ebd3
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Reviewed-on: http://review.coreboot.org/514
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
Reviewed-by: Philip Prindeville <pprindeville@gmail.com>
Kerry Sheh [Thu, 22 Dec 2011 04:18:26 +0000 (12:18 +0800)]
F14 mainboard: mptable update
Add GNB internal graphic interrupt,
correct southbridge hd audio device interrupt. and remove the
dead code already commented out.
south_station, union_station, inagua, persimmon and e350m1 mainboard
are included herein.
Change-Id: Ic7618d80e0432ed0e22d1c16e1adb8ba6cea2e59
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Reviewed-on: http://review.coreboot.org/451
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Kerry Sheh [Thu, 22 Dec 2011 04:18:37 +0000 (12:18 +0800)]
F14 mainboard: update acpi interrupt routing in pic and apic mode
Add interrupt routing for APU GNB internal Graphic and HD audio device, and
other pcie bridge device in GNB.
south_station, union_station, inagua, persimmon and e350m1 mainboard
are included herein.
Change-Id: I4b6e0fce8d34637c03de8ebfdadea008c98e193b
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Reviewed-on: http://review.coreboot.org/452
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Nils Jacobs [Fri, 30 Dec 2011 21:30:27 +0000 (22:30 +0100)]
White space and coding style fixes.
Change-Id: I14f39b5666fc18e8183723ec78a40a849d337736
Signed-off-by: Nils Jacobs <njacobs8@adsltotaal.nl>
Reviewed-on: http://review.coreboot.org/511
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Marc Jones [Wed, 14 Dec 2011 22:33:33 +0000 (15:33 -0700)]
Fix Fam10 MMCONF_SUPPORT_DEFAULT setting.
I misunderstood how kconfig select works. It needs to be selected with a config option. Moved the select to the correct location.
Change-Id: If9b1e21e6cbc5af4671efb76cf87dd18dbbe2234
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/487
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Vikram Narayanan [Sun, 25 Dec 2011 20:38:44 +0000 (02:08 +0530)]
trivial:change the value type of POST_PORT in Kconfig from int to hex
trivial change in src/console/Kconfig
Change-Id: Ib6bb4ccfabaa3af18b48a23a51a576b872d807a8
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-on: http://review.coreboot.org/505
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Kyösti Mälkki [Mon, 5 Dec 2011 18:33:55 +0000 (20:33 +0200)]
Sconfig: parse Kconfig options from devicetree.cb
Mainboard and chip Kconfig files have several build options that
are redundant with information in devicetree.cb. This patch enables
sconfig to auto-generate equivalent configuration.
sconfig -s
Generates mainboard's static.c file, as before.
sconfig -b
This operation creates mainboard's bootblock init code. By default,
for every chip listed in mainboard/devicetree.cb, if there is a
chip/bootblock.c file, the init function is called.
A mainboard/bootblock.c file can be added to override default
behaviour.
sconfig -k
This operation generates select -options for component paths.
Change-Id: I808d44af552dbc5e0565d6a0f4f72c7be9f5740e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/472
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Kyösti Mälkki [Mon, 5 Dec 2011 18:17:17 +0000 (20:17 +0200)]
Only BSP CPU writes CMOS in bootblock code
CMOS accesses are not safe for multi-processor and only the BSP CPU
should count reboots and test CMOS sanity.
A questionable single byte CMOS read access from AP CPUs remains.
AP CPUs should always select the same romstage prefix as BSP CPU.
Change-Id: I29118e33c07c0080c94abb90f703e38312c72432
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/446
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Patrick Georgi [Fri, 18 Nov 2011 13:44:16 +0000 (14:44 +0100)]
libpayload: remove uhci_reg_maskX
Not that good an idea to start with.
Coccinelle patch:
@@
@@
-void
(
-uhci_reg_mask8
|
-uhci_reg_mask16
|
-uhci_reg_mask32
)
- (...) { ... }
@@
@@
-void
(
-uhci_reg_mask8
|
-uhci_reg_mask16
|
-uhci_reg_mask32
)
- (...);
@@
expression ctrl, reg, ormask;
@@
-uhci_reg_mask32 (ctrl, reg, ~0, ormask)
+uhci_reg_write32 (ctrl, reg, uhci_reg_read32 (ctrl, reg) | ormask)
@@
expression ctrl, reg, ormask;
@@
-uhci_reg_mask16 (ctrl, reg, ~0, ormask)
+uhci_reg_write16 (ctrl, reg, uhci_reg_read16 (ctrl, reg) | ormask)
@@
expression ctrl, reg, ormask;
@@
-uhci_reg_mask8 (ctrl, reg, ~0, ormask)
+uhci_reg_write8 (ctrl, reg, uhci_reg_read8 (ctrl, reg) | ormask)
@@
expression ctrl, reg, andmask;
@@
-uhci_reg_mask32 (ctrl, reg, andmask, 0)
+uhci_reg_write32 (ctrl, reg, uhci_reg_read32 (ctrl, reg) & andmask)
@@
expression ctrl, reg, andmask;
@@
-uhci_reg_mask16 (ctrl, reg, andmask, 0)
+uhci_reg_write16 (ctrl, reg, uhci_reg_read16 (ctrl, reg) & andmask)
@@
expression ctrl, reg, andmask;
@@
-uhci_reg_mask16 (ctrl, reg, andmask, 0)
+uhci_reg_write16 (ctrl, reg, uhci_reg_read16 (ctrl, reg) & andmask)
Change-Id: Id0eb8327293831e54249d43fd06d50963c793699
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/477
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Philip Prindeville [Sat, 24 Dec 2011 01:33:05 +0000 (18:33 -0700)]
Let lib_get_sysinfo() pass through the success of get_coreboot_info()
The return status of get_coreboot_info() might be handy to a platform
driver calling lib_get_sysinfo() to test for the presence of coreboot.
Change-Id: I0176c93ee92c9dff733112026ee50f2ca797bdff
Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
Reviewed-on: http://review.coreboot.org/503
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Philip Prindeville [Sat, 24 Dec 2011 00:53:26 +0000 (17:53 -0700)]
Fix missing cast back to void *
MEM_RANGE_PTR() also needs to return a pointer to untyped memory.
Change-Id: I0ec64ad7bdb136d5e1a999bff3df6fa66eb29bf1
Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
Reviewed-on: http://review.coreboot.org/500
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Philip Prindeville [Sat, 24 Dec 2011 00:36:09 +0000 (17:36 -0700)]
Fix missing VM mapping
When processing FORWARD records, we weren't accounting for the pointer
being in the physical address space and not the virtual space instead.
Change-Id: I35ef637fbec7886d4cfeac5fd650a17eae8d555a
Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
Reviewed-on: http://review.coreboot.org/499
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Philip Prindeville [Sat, 24 Dec 2011 00:28:59 +0000 (17:28 -0700)]
Use void pointers for untyped memory
To avoid unnecessary casts, we can use untyped pointers when accessing
individual records.
Change-Id: I1d628d6e25f1e53b4fee34e7c2c4688a789c45a3
Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
Reviewed-on: http://review.coreboot.org/498
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Philip Prindeville [Sat, 24 Dec 2011 00:22:05 +0000 (17:22 -0700)]
Use convenience function to checksum
That coreboot uses the IP checksum is an artifact, not a deliberate
requirement to be compatible with the Internet Protocole suite. Use
a wrapper to abstract the computation of coreboot's checksum.
Change-Id: I6491b9ba5efb9ffe5cb12a6172653a6ac80a1370
Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
Reviewed-on: http://review.coreboot.org/497
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Philip Prindeville [Sat, 24 Dec 2011 00:09:02 +0000 (17:09 -0700)]
Replace UNPACK_CB64 macro with inline
Having submitted a module based on coreboot to LKML for acceptance,
it was requested that fewer macros and more inlines be used (because
of their superior type-checking when performing pointer casts, etc).
This is the first of several changes to make the relevant parts of
coreboot comply to linux code standards.
Change-Id: Iffe7061fa62fa639e0cb6ccb9125eb3403d06b1a
Signed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
Reviewed-on: http://review.coreboot.org/495
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Kerry Sheh [Wed, 23 Nov 2011 07:04:13 +0000 (15:04 +0800)]
south_station: Enable GNB hd audio
Enable HD audio over HDMI.
Tested in Ubuntu-11.10 with ATI Catalyst Proprietary Driver installed.
Change-Id: I013c2c15ee56a7b134d980da1aa1856778a1eb4c
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Reviewed-on: http://review.coreboot.org/450
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Marc Jones [Wed, 14 Dec 2011 22:59:02 +0000 (15:59 -0700)]
Add RS780 defaut graphics ID to AMD Mahogany mainboard.
Added the default ID to the mainboard Kconfig.
Change-Id: Ie5d39ccdda9d4f5a86214b5bd9ca629070ff152a
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/488
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Christian Ruppert [Sat, 17 Dec 2011 20:56:05 +0000 (21:56 +0100)]
Respect linker order
Linking fails when using -Wl,--as-needed and/or esp. when forcing --as-needed
through a compiler specs file.
A proper compile/link command would look like: $(CC) $(CFLAGS) $(LDFLAGS) -o foo
$(OBJS) $(LIBS). So the *FLAGS must be passed *before* the objects while the
libraries/dependencies must be passed *after* the objects.
For more details see: http://www.gentoo.org/proj/en/qa/asneeded.xml
Change-Id: I5a5b05e1cab8a2d88ce56c92d9b2f991ca1ee6c0
Signed-off-by: Christian Ruppert <idl0r@qasl.de>
Reviewed-on: http://review.coreboot.org/494
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Mathias Krause [Wed, 14 Dec 2011 07:40:48 +0000 (08:40 +0100)]
kbd: wait longer for self-test on keyboard reset
Some keyboards take pretty long to respond to a reset command, some even
delay the ACK to the command. To make the keyboard driver more robust,
increase the timeout for this special command. Also do an interface test
after the self-test to ensure the keyboard is functioning properly.
Another point is to reenable the keyboard *after* the scancode was set,
not before. We also set the system bit when enabling the keyboard
because this seems to be what older operating systems do expect.
One of the problematic keyboards, which will work with this patch
applied, is the DELL RT7D20. Without the patch an overly optimistic
operating system, read Linux 2.4, will not recognise the keyboard
because coreboot didn't fully initialize it.
Change-Id: I28c8e05bdde61f71b7de084c96bc2447c1b9575e
Signed-off-by: Mathias Krause <mathias.krause@secunet.com>
Reviewed-on: http://review.coreboot.org/486
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Marc Jones [Wed, 14 Dec 2011 18:24:00 +0000 (11:24 -0700)]
Persimmon audio codec verb patch.
Verb data is required for the HDA audio codec in the sb800 southbridge. Verb
data is not required for mainboards that use G-Series HDMI. It is also a setting
the may be boards specific. This fixes issues with Windows audio on Persimmon.
Change-Id: I067506871e92078d122cf79872363d8937d47e50
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/490
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Peter Stuge [Wed, 14 Dec 2011 06:32:15 +0000 (07:32 +0100)]
.gitignore util/crossgcc/build-* and unpacked source directories
Change-Id: I85b9dffbbe0c7f1ae8cc2b584196775ba2f816df
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/484
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Sven Schnelle [Wed, 7 Dec 2011 22:30:58 +0000 (14:30 -0800)]
Lenovo X60/T60: add first_battery setting
The EC allows to select the order in which batteries are (dis)charged.
Make this setting available to the user.
Change-Id: Id2a98192565419dbb53f3a7cf0b2c46b672a3ed8
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/475
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Peter Stuge <peter@stuge.se>
Florian Zumbiehl [Tue, 6 Dec 2011 09:31:10 +0000 (10:31 +0100)]
asus k8v-x: explicitly set RAM and bus voltages
Change-Id: I9426cafc252ee765d723af569c4a90e090d313d9
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/482
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Florian Zumbiehl [Sat, 10 Dec 2011 18:39:49 +0000 (19:39 +0100)]
k8: add CONFIG_K8_FORCE_2T_DRAM_TIMING and enable it for asus k8v-x
Change-Id: Ia457f92f6fb7e287defb838db07f12d0f1766757
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/481
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Stefan Reinauer [Tue, 13 Dec 2011 22:08:03 +0000 (23:08 +0100)]
Fix console output in real mode int10 implementation.
Checking RBIL, int10 AH=0x10 does never output a character.
The two output functions are AH=0x09 and AH=0x0e.
Change-Id: Id7f4d260b63024748ef771f949e8b60f934bacbc
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/483
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Patrick Georgi [Tue, 22 Nov 2011 12:07:45 +0000 (13:07 +0100)]
libpayload: add set_option() function
It allows to change CMOS values from payloads
Change-Id: I4872fc27476923adafe13504126235b92b30de85
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/445
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Patrick Georgi [Tue, 22 Nov 2011 09:27:24 +0000 (10:27 +0100)]
Fix CMOS handling for non-USE_OPTION_TABLE configuration
The read_option macro still emitted CMOS_VSTART_*/CMOS_VEND_* symbols,
which fail without an option table (as no option_table.h defines them).
Discard them by using a macro instead of a static inline function.
Change-Id: I8d001f971681277a344b6788725746491546b607
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/442
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Marc Jones [Thu, 24 Nov 2011 00:49:19 +0000 (17:49 -0700)]
Use MMCONF for all AMD family 10 CPUs.
This fixes problems in AP init when multiple APs are trying to access
PCI config space. All Fam10 CPUs setup and support MMCONF.
Change-Id: I00a25bbf4e4152c89024f14a3c4c1c36b48d0128
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/455
Tested-by: build bot (Jenkins)
Reviewed-by: Alec Ari <neotheuser@ymail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Alec Ari [Wed, 7 Dec 2011 07:50:52 +0000 (01:50 -0600)]
Change DSDT Table ID for M4A785T-M board
Change the DSDT Table ID for M4A785T-M
from M4A785-M to M4A785T-M.
This fixes a small copypasta.
This is an updated patch set.
Change-Id: I43ee024222cf04d03685ffaee616971100cc9e6c
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/474
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Kyösti Mälkki [Wed, 23 Nov 2011 14:33:12 +0000 (16:33 +0200)]
Fix ldscript for bootblock .rom section
Allocation size for the section was miscalculated, so the section
did not honour its upper-bound address.
Also align the section start to 4 bytes, so it starts with code
instead of pad bytes.
Change-Id: Ic2a43981836a0873b50abecfcad2def7b6586a5d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/453
Tested-by: build bot (Jenkins)
Reviewed-by: Alec Ari <neotheuser@ymail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Kyösti Mälkki [Sat, 3 Dec 2011 09:30:26 +0000 (11:30 +0200)]
Fix AMD 8132 and 8151 southbridge builds
Untested, changes ramstage build for boards:
supermicro/h8qme_fam10
amd/serengeti_cheetah
amd/serengeti_cheetah_fam10
AMD 8132 was not built for any mainboard due to a typo.
AMD Serengeti Cheetah:
Chip 8151 is referenced in devicetree.cb but was not built.
AMD Serengeti Cheetah Family10:
There are indications the board has 8151, but it is not listed
in the devicetree.cb. The 8151 chip is not added in the build.
Change-Id: I03acdfcc3f3440bd32e81a9a696159903bbbcb50
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/471
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Kyösti Mälkki [Tue, 22 Nov 2011 17:44:45 +0000 (19:44 +0200)]
Bootblock does not need a unique boot_cpu()
Detection of a CPU being a BSP CPU is not dependent of the existence
of northbridge and/or southbridge init code in the bootblock.
Even if CONFIG_LOGICAL_CPUS==0, boot_cpu() can get executed on an AP
CPU of a hyper-threading CPU and needs to return actual BSP bit from
MSR.
Change-Id: I9187f954bb357ba1dbd459cfe11cc96cb7567968
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/447
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Denis 'GNUtoo' Carikli [Sun, 27 Nov 2011 12:43:16 +0000 (13:43 +0100)]
RS780: print the vgainfo
With this commit the vgainfo is printed and looks like that on the serial console:
vgainfo:
ulBootUpEngineClock:50000
ulBootUpUMAClock:66700
ulBootUpSidePortClock:0
ulMinSidePortClock:0
ulSystemConfig:0
ulBootUpReqDisplayVector:0
ulOtherDisplayMisc:0
ulDDISlot1Config:0
ulDDISlot2Config:0
ucMemoryType:0
ucUMAChannelNumber:1
ucDockingPinBit:0
ucDockingPinPolarity:0
ulDockingPinCFGInfo:0
ulCPUCapInfo: 2
usNumberOfCyclesInPeriod:0
usMaxNBVoltage:0
usMinNBVoltage:0
usBootUpNBVoltage:0
ulHTLinkFreq:20000
usMinHTLinkWidth:8
usMaxHTLinkWidth:8
usUMASyncStartDelay:100
usUMADataReturnTime:300
usLinkStatusZeroTime:600
ulHighVoltageHTLinkFreq:20000
ulLowVoltageHTLinkFreq:20000
usMaxUpStreamHTLinkWidth:8
usMaxDownStreamHTLinkWidth:8
usMinUpStreamHTLinkWidth:8
usMinDownStreamHTLinkWidth:8
Change-Id: I17c2a13ab52a0f78588f812d4f42f45f9a7b7524
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/456
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Florian Zumbiehl [Tue, 1 Nov 2011 19:19:41 +0000 (20:19 +0100)]
adding support for the Asus K8V-X
This pulls it all together and adds the real board-specific code.
Confirmed to be working:
- IDE
- SATA
- floppy
- USB1.1
- USB2.0
- PS/2 keyboard
- PS/2 mouse
- serial
- parport
- sound
- ethernet
- PCI slots
- AGP
- powernow
- fan speed monitoring
- flashrom write
Change-Id: Ifb97714c2f009d688be0ca3c38ddc01599ffd799
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/390
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Tested-by: build bot (Jenkins)
Rudolf Marek [Tue, 22 Nov 2011 23:23:43 +0000 (00:23 +0100)]
Fix Asus A8V-E SE DIMM slot mapping
Fix the DIMM mappings, channel 0 is "B" on board,
and secondary channel is on 0x51,0x53
Change-Id: I8c49c4efb90a4297aaea0be2159435dadab9ac0a
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/449
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Florian Zumbiehl [Tue, 1 Nov 2011 19:19:37 +0000 (20:19 +0100)]
make GPIOs and misc configurable via devicetree
Change-Id: I9f70da76b5ea451f28a1ad9252c5d879fc4fe315
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/387
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Florian Zumbiehl [Mon, 21 Nov 2011 02:10:47 +0000 (03:10 +0100)]
make INT[EFGH]# of vt8237 configurable as gpio via devicetree
Change-Id: I70202d81ddd1b0a00eddca4acabc621e5783e805
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/386
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Florian Zumbiehl [Tue, 1 Nov 2011 19:19:40 +0000 (20:19 +0100)]
copied asus a8v-e_se to k8v-x
Change-Id: Ib66e8c5102ad45e73977a06aea109ed9544f4d08
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/389
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Florian Zumbiehl [Tue, 1 Nov 2011 19:19:38 +0000 (20:19 +0100)]
some black magic for initializing the old version of the k8t800
Change-Id: I1b5d23cee9f933aa090c9bd09890c7b335567e17
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/388
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Florian Zumbiehl [Tue, 1 Nov 2011 19:19:35 +0000 (20:19 +0100)]
implement usb2 termination and dpll delay setting for vt8237r
Change-Id: I830c9a3daf5ac2e1ecd9a3e725a0b98f06509769
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/385
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Sven Schnelle [Fri, 2 Dec 2011 15:33:30 +0000 (16:33 +0100)]
i3100: Add HAVE_HARD_RESET
and remove it from mainboard/intel/mtarvon, as this function
is implemented in the southbridge code.
Change-Id: Id3669aaf99b96b4a7a965f4957e5de7c365acaa6
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/469
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
QingPei Wang [Tue, 22 Nov 2011 07:24:12 +0000 (15:24 +0800)]
Mirror Fix coreinfo usage of cb_info
fix cb_info.serial.ioport to cb_info.serial.baseaddr
Change-Id: I32f261e4be927555979eb833d0251fce2c6a5c47
Signed-off-by: QingPei Wang <wangqingpei@gmail.com>
Reviewed-on: http://review.coreboot.org/441
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Denis 'GNUtoo' Carikli [Sun, 27 Nov 2011 21:04:02 +0000 (22:04 +0100)]
M4A785T-M: fix ACPI's P-States Table
Without that fix the linux kernel cannot change the frequency
of the CPUs with cpufreq.
Change-Id: Ie00e4b11b2561356952d8ae28bd0a00523b6d85f
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/458
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Denis 'GNUtoo' Carikli [Sun, 27 Nov 2011 14:58:38 +0000 (15:58 +0100)]
Add ASUS M4A785T-M mainboard support
This mainboard is very similar to the M4A785-M, but it has
DDR3 instead of DDR2.
That's why most of the code was copied or included from
the m4a785-m directory
Notable changes between the two mainboards include:
* the selection of the last microcode (mc_patch_010000b6.h)
which made it pass the CPU init.
* the selection of DDR3 which made it pass the ram init
This change was tested with the Trisquel 5.0 GNU/Linux distribution
which uses the linux-libre version 2.6.38-12-generic
The mainboard boots fine, however some special care is required for
the onboard sound CODEC, and the onboard video chip:
* the onboard sound CODEC(snd-hda-* has to be blacklisted), the issue
is the same than the ASUS M4A785-M mainboard:
It causes a flood of interupts which prevents booting
* The internal video chip currently requires pci=nocrs, else
the graphics are frozen as soon as the radeon module loads,
and dmesg would print the following(the card only has 256M,
and the mainboard was equiped with 2G of RAM):
[ 3.674762] [drm] radeon: 3584M of VRAM memory ready
[ 3.679863] [drm] radeon: 512M of GTT memory ready.
instead of :
[ 45.876088] [drm] radeon: 256M of VRAM memory ready
[ 45.876089] [drm] radeon: 512M of GTT memory ready.
* The screen(both VGA and HDMI) flickers at high resolution
* Sometimes the computer freeze while changing the resolution
(even the serial console stops responding)
The following peripherals were tested:
* The ath9k PCI wireless card was tested
* The SATA hard disk works fine
* the USB keyboard and mouse work fine
* htop see 2 cores
* serial port works under coreboot and GNU/Linux
* power off and reboot works
CPU frequency cannot be changed yet, this is addressed
in a new commit.
More detail are available here:
http://www.coreboot.org/ASUS_M4A785T-M
dmesg is available here:
http://www.coreboot.org/pipermail/coreboot/2011-November/067604.html
The mailing list thread on the graphic problem is here:
http://www.coreboot.org/pipermail/coreboot/2011-November/067466.html
Change-Id: I5df0bc1f9f0071b1e1ee7c8a356bf517aa8cf732
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/457
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Kyösti Mälkki [Fri, 2 Dec 2011 16:05:46 +0000 (18:05 +0200)]
Remove obsolete TINY_BOOTBLOCK
Change-Id: I0edc69dc5f95cc32ee648eb094c9e5387f80db47
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/470
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Kyösti Mälkki [Thu, 1 Dec 2011 15:49:43 +0000 (17:49 +0200)]
Change AMD vendorcode build
Apply the normal method of recursively including subdirectories
for src/vendorcode. Remove redundant references under
mainboard and northbridge.
Change-Id: I914a6e262ed2abe83f407df36fe5c1af5eb4bcb0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/468
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Sven Schnelle [Mon, 28 Nov 2011 20:12:11 +0000 (21:12 +0100)]
X60/T60: reset baudrate loglevel to sane values
Change-Id: Iaf5861e9db0a41a184da6d2e515e3b9afe0655d6
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/459
Tested-by: build bot (Jenkins)
Kyösti Mälkki [Tue, 22 Nov 2011 18:21:06 +0000 (20:21 +0200)]
Remove unused code files and cosmetic changes
Following files were no longer used in the build and are deleted:
src/arch/x86/init/entry.S
src/arch/x86/init/ldscript.ld
Also fix ugly whitespace in code copyrights and comments.
Change-Id: Ia6360b0ffc227f372d5f997495697a101f7ad81b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/440
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Florian Zumbiehl [Tue, 1 Nov 2011 19:19:04 +0000 (20:19 +0100)]
vt8237: add support for setting the power state after loss of power
Change-Id: Ia7e3e77235530e952b2e84fdec8373b90fa59b7a
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/437
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Florian Zumbiehl [Tue, 1 Nov 2011 19:18:29 +0000 (20:18 +0100)]
k8 raminit: fix bug, improve clock selection, add clock limit for sock754
in amdk8 raminit:
- fix DDR SPD offset for (CLX - 1) (25 instead of 26)
- improve clock/CL selection algorithm
- implement load-dependent clock limiting for socket 754
Change-Id: I5eb8a3e02eaca18f3bef9a98de22f23b23650762
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/377
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Florian Zumbiehl [Tue, 1 Nov 2011 19:19:06 +0000 (20:19 +0100)]
implement hwmon fan divisor setting for w83697hf
Change-Id: I887ac1142875ca1dc1a1eb8eebec402fbe7512c3
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/384
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Tested-by: build bot (Jenkins)
Florian Zumbiehl [Tue, 22 Nov 2011 20:32:31 +0000 (21:32 +0100)]
k8 raminit: add workaround for erratum #181 on non-fam-f
Disable DRAM controller on non-fam-f CPUs not using fam-f register layout.
Change-Id: I2cc87857452555011d69bfebe9f9c4c17cef8f6c
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/448
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Kyösti Mälkki [Mon, 21 Nov 2011 06:16:20 +0000 (08:16 +0200)]
Fix post_code in 16bit entry
Relocate early post_code() so it gets executed and does not corrupt
BIST at %eax.
Change-Id: Ieeebcb23f7c327e501b410eaa60d1e49110ee988
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/439
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Kerry Sheh [Tue, 15 Nov 2011 13:27:57 +0000 (21:27 +0800)]
mainboard: Add AMD unionstation RDK support
AMD unionstation Reference Design Kit is Designed for hd settop box application.
This platform using family14 APU, SB800 southbridge.
Vgabios is required, can download vgabios from AMD NDA website.
Verified Feature:
HDMI, LAN, mini-pcie slots, sata, usb, analog audio and
optical fiber digital audio output.
Change-Id: Ib1d1d8c889d6fb29f4298b57dfe5c5c1cea1431c
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/434
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Kerry Sheh [Tue, 15 Nov 2011 13:27:07 +0000 (21:27 +0800)]
mainboard: Add AMD southstation RDK support
AMD southstation Reference Design Kit is designed for NAS application.
This platform using family14 RevC0 processor, SB850 southbridge.
Vgabios and Promise RAID Option ROM is required for hardware RAID support,
can retrieve from the AMD NDA website.
Verified feature:
HDMI, LAN, usb and mini-pcie slot.
RAID0, RAID1 RAID10 and RAID5 upto 6 sata hard drive with ubuntu server 10.10.
Change-Id: I16e6f5dab8b0d634e186068c81436db77fb4475a
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/433
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Florian Zumbiehl [Tue, 1 Nov 2011 19:18:28 +0000 (20:18 +0100)]
fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminit
Change-Id: Ibdce9712f5019863b1cd61b68da11d7c46c6b6f8
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/376
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Patrick Georgi [Fri, 11 Nov 2011 10:05:42 +0000 (11:05 +0100)]
libpayload: Enable colors in PDcurses
PDcurses wants set_blink to determine color count. Not exactly
obvious.
Change-Id: I8b2a32f0095d5900fa7e01f04f3f1d565dc2bedf
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/432
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Florian Zumbiehl [Tue, 1 Nov 2011 19:17:41 +0000 (20:17 +0100)]
compile code for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD
make code dependent on CONFIG_SOUTHBRIDGE_VIA_K8T800 also be included
for CONFIG_SOUTHBRIDGE_VIA_K8T800_OLD
Change-Id: I9f4624d08de2790fb513a88ed6207e28e7fbc733
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/374
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Florian Zumbiehl [Tue, 1 Nov 2011 19:17:14 +0000 (20:17 +0100)]
support for different location of HT registers in old version of K8T800
Change-Id: I2ad82b8059efb09f0593933cb6f53b51b653d494
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/373
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Patrick Georgi [Thu, 10 Nov 2011 14:48:37 +0000 (15:48 +0100)]
libpayload: Fix handling of CAPS LOCK key on PS/2 keyboards
The PS/2 keyboard driver set and reset the caps LED to show the
keyboard status. Unfortunately, that configuration happens over
the same path used to transmit keypresses.
In face of certain error conditions, the keyboard stopped working.
This change makes keyboard handling more robust.
Change-Id: I0489a9983ea7dab00357220e09398dd1a8538839
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/430
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Oskar Enoksson [Mon, 7 Nov 2011 17:31:33 +0000 (18:31 +0100)]
Fixed whitespace and indentation
Code style fixes for the hp/dl145_g1 system board code.
Change-Id: I3c1a175d954e2d340e82c03c9f984699dcff865e
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Reviewed-on: http://review.coreboot.org/428
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Patrick Georgi [Fri, 4 Nov 2011 20:37:14 +0000 (21:37 +0100)]
buildgcc: Add option to use ccache
This mimicks abuild: -y enables ccache.
Change-Id: I3ac1f809729af816efbc64f5789ab430e1a6a6b2
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/400
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Florian Zumbiehl [Tue, 1 Nov 2011 19:19:02 +0000 (20:19 +0100)]
make w83697hf_set_clksel_48() non-static and add a prototype
make w83697hf_set_clksel_48() non-static and add a prototype so as to
get rid of warnings about it being unused
Change-Id: I8ae94cfd61ae4774a367f83dd37e488987e2451a
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/380
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Stefan Reinauer [Mon, 7 Nov 2011 21:16:38 +0000 (13:16 -0800)]
selfboot: Don't include unneeded ip_checksum.h
Change-Id: I09b888e70f7432f7025b0b851acfb0279553400f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/426
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Stefan Reinauer [Mon, 7 Nov 2011 20:56:12 +0000 (12:56 -0800)]
selfboot: fix bug in valid_area()
valid_area will accept a region as valid for the payload if only a part
of coreboot fits in that region. This means if a payload reaches into a
neighboring RESERVED region, coreboot would not care and happily
overwrite that region, as long as the payload also writes to some RAM.
Change-Id: Ie263f83be18009b01a31c71e7285c998747d097f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/425
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Stefan Reinauer [Tue, 8 Nov 2011 17:58:29 +0000 (09:58 -0800)]
move function from header file to .c file
http://review.coreboot.org/#change,378 introduced a function in k8x8xx.h
move this function to ctrl.c and add a prototype to the header file instead.
Change-Id: I0919ffb2030c53669b95f58b649d4a160f660923
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/429
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Marc Jones [Tue, 8 Nov 2011 06:26:14 +0000 (23:26 -0700)]
Cleanup Persimmon mainboard whitespace.
Change-Id: I389bde86c5583a4fb37a699162b65b475ed94ddc
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/427
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Stefan Reinauer [Mon, 7 Nov 2011 20:43:03 +0000 (12:43 -0800)]
selfboot: cleanup
- move cbfs_load_payload to the end so we can drop the prototype
- move lb_start and lb_end to the beginning so they can be used
in other functions.
- drop two unused function declarations
- break a 80+ characters line
- fix a comment
Change-Id: I460aa1e2ccf9d95ac12233af001076f73ab0268e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/424
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Oskar Enoksson [Tue, 4 Oct 2011 20:15:51 +0000 (22:15 +0200)]
Added RAMINIT_SYSINFO and declared the necessary structs
Using RAMINIT_SYSINFO should be beneficial for this platform.
It is also more clean/safe to put data in struct mb_sysconf_t.
It's more consistent with other MB's and I've tested it
thoroughly on my DL145.
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Change-Id: Ie90a134a1efc9605b3fe17a5b5008856226984be
Reviewed-on: http://review.coreboot.org/236
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Idwer Vollering [Mon, 7 Nov 2011 16:48:33 +0000 (17:48 +0100)]
Add code to set the clock speed for Winbond W83627THF/THG.
Change-Id: I984404dd1df50b3ba423ac610283b9bf8bca5a31
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/412
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Jonathan A. Kollasch [Mon, 7 Nov 2011 16:56:42 +0000 (10:56 -0600)]
superiotool: add detection and dump of Infineon SLB9635 TPM
Change-Id: If94ea5f45135a4b65bdd37532851fa0ba864bb73
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/421
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Jonathan A. Kollasch [Mon, 7 Nov 2011 19:05:18 +0000 (13:05 -0600)]
buildgcc: don't download python and expat if disabled
Change-Id: I18cb1426e935c46ead30c72685829c20d186f9d8
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/423
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Patrick Georgi [Mon, 7 Nov 2011 18:01:54 +0000 (19:01 +0100)]
abuild: Don't try to use files that don't exist
Collecting per-board abuild.xml is bound to fail if there
are no such files.
Change-Id: I6bd6b4389beda51654005e0380f0e52f006642db
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/422
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Florian Zumbiehl [Tue, 1 Nov 2011 19:19:01 +0000 (20:19 +0100)]
rename vt8237r_cfg() to k8x8xx_vt8237r_cfg() and make publicly accessible
Change-Id: I82d1ec5117a58aaa8cfd2a342b7172a2786f5680
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/379
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Florian Zumbiehl [Tue, 1 Nov 2011 19:18:30 +0000 (20:18 +0100)]
factor out common config for k8x8xx's dram_enable() and vt8237r_cfg()
Instead of writing to config registers in k8x8xx's dram_enable()
and reading those back in vt8237r_cfg(), factor out generation of
the values and reuse that in both places.
Change-Id: I87a37398efe84b33e6678df74cd40b5abfe4f879
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/378
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Florian Zumbiehl [Tue, 1 Nov 2011 19:19:02 +0000 (20:19 +0100)]
add support for 1106:3188 (host controller of the old version of k8t800)
Change-Id: Id61678f03e1f7d964f7180a062dd6a689852d4ac
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/401
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Jonathan A. Kollasch [Mon, 7 Nov 2011 16:43:05 +0000 (10:43 -0600)]
Avoid false detection of SMSC FDC37N972 when Infineon TPM is present
Change-Id: Ibfb3af4c5d7675a5d4e27021cbb988c2ce00fd9f
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/420
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Florian Zumbiehl [Tue, 1 Nov 2011 19:16:16 +0000 (20:16 +0100)]
in vt8237r_enable(), write function enables only to ISA bridge config space
vt8237r_enable() so far wrote the function enable values to the same
offset in the config space of every one of the vt8237's functions,
even though the register is located in the ISA bridge only.
Change-Id: I639586dc238132f5b8d2f320b794948718281b9c
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/368
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Florian Zumbiehl [Tue, 1 Nov 2011 19:17:12 +0000 (20:17 +0100)]
Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26
Change-Id: Ic77854130ad43715daa7c0eb462291db48df9f84
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/370
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Patrick Georgi [Fri, 4 Nov 2011 20:30:49 +0000 (21:30 +0100)]
buildgcc: Explicitely state CC everywhere
This should fix issues with the iasl Makefile on Debian and
prepares ccache support for buildgcc.
Change-Id: Id9e6b2044b159b19bf013ec5c47b60ca1c2f2991
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/399
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Patrick Georgi [Sat, 5 Nov 2011 13:39:56 +0000 (14:39 +0100)]
kconfig: Use more collision resistant temporary filenames
kconfig creates reasonably safe filenames for its temporary files
except for two of them.
Change-Id: I6861f55ae2a5311e3fb7919333ce9af1e39ce78b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/408
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Patrick Georgi [Sat, 5 Nov 2011 12:21:14 +0000 (13:21 +0100)]
abuild: Write XML/JUnit files per board
Write them per-board and merge them after everything is done.
This prepares for build parallelization.
Change-Id: Ia4e7ce03473bcf8861fb9ae06e9c1270292401ac
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/407
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>